JPS60177549U - Video signal processing circuit in display device - Google Patents

Video signal processing circuit in display device

Info

Publication number
JPS60177549U
JPS60177549U JP1984064657U JP6465784U JPS60177549U JP S60177549 U JPS60177549 U JP S60177549U JP 1984064657 U JP1984064657 U JP 1984064657U JP 6465784 U JP6465784 U JP 6465784U JP S60177549 U JPS60177549 U JP S60177549U
Authority
JP
Japan
Prior art keywords
primary color
signal
video signal
color signals
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984064657U
Other languages
Japanese (ja)
Inventor
沢田 繁
Original Assignee
日本ビクター株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本ビクター株式会社 filed Critical 日本ビクター株式会社
Priority to JP1984064657U priority Critical patent/JPS60177549U/en
Publication of JPS60177549U publication Critical patent/JPS60177549U/en
Pending legal-status Critical Current

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  • Color Television Systems (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案回路の一実施例を示すブロック系統図、
第2図は第一1図図示ブロック系統の動作説明用信号波
形図である。 1・・・テレビジョン受像機、2・・・輝度信号入力端
     5子、3・・・搬送色信号入力端子、7〜9
・・・スイッチ回路、10〜12・・・三原色信号入力
環子、13・・・高速切換信号入力端子、14・・・ハ
ーフブランキング制御信号入力端子、15・・・レベル
制御電圧入力端子、16・・・制御電圧発生回路、17
〜19,20−1〜20−3・・・レベル制御回路、2
1・・・陰極線管(CRT)。 第2図   −− I ・十 1 一゛−1 、C−1 1−− d−」− 1 II °徂− C 1 f   +1 □1ト 」下 9目 i ・十− 一1H−m1      ゛ ■
FIG. 1 is a block diagram showing an embodiment of the circuit of the present invention;
FIG. 2 is a signal waveform diagram for explaining the operation of the block system shown in FIG. 11. 1... Television receiver, 2... Brightness signal input terminal 5 children, 3... Carrier color signal input terminal, 7 to 9
...Switch circuit, 10-12... Three primary color signal input ring, 13... High speed switching signal input terminal, 14... Half blanking control signal input terminal, 15... Level control voltage input terminal, 16... Control voltage generation circuit, 17
~19,20-1~20-3...Level control circuit, 2
1...Cathode ray tube (CRT). Figure 2 -- I ・11 1゛-1, C-1 1-- d-"-1 II °- C 1 f +1 □1t" Lower 9th i ・11-11H-m1 ゛■

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)三原色信号と高速切換信号とハーフブランキング
制御信号とが夫々外部入力端子を介して供給され、該三
原色信号による画像を画面内にスーパーインポーズする
機能を有するディスプレイ装置における映像信号処理回
路であって、該三原色信号に対するレベル制御信号と該
ノ1−フブランキング制御信号との加算混合信号に基づ
いて、該ハーフブランキング制御信号の入来期間は非入
来期間に比し該三原色信号を相対的にレベル増強して出
力する第1のレベル制御手段と、該ディスプレイ装置の
内部で複合映像信号より復調して得た復調映像信号と該
第1のレベル制御手段よりの三原色信号の各々とが夫々
供給され、該高速切換信号入来時には該第1のレベル制
御手段よりの三原色信号を選択出力し、該高速切換信号
非入来時には該復調映像信号を□・ 選択出力するスイ
ッチ回路と、該ハーフブランキング制御信号の入来期間
は非入来期間に比し該スイッチ回路の出力信号を相対的
にレベル減衰して画像表示部へ出力する第2のレベル制
御手段とより構成したディスプレイに装置における映像
信号処理回路。
(1) A video signal processing circuit in a display device which has a function of supplying three primary color signals, a high speed switching signal, and a half blanking control signal via external input terminals, and superimposing an image based on the three primary color signals on the screen. Based on the addition mixed signal of the level control signal for the three primary color signals and the half blanking control signal, the incoming period of the half blanking control signal is greater than the non-incoming period of the three primary color signals. a demodulated video signal obtained by demodulating the composite video signal within the display device, and each of the three primary color signals from the first level control device; a switch circuit which selectively outputs the three primary color signals from the first level control means when the high-speed switching signal is received, and selectively outputs the demodulated video signal when the high-speed switching signal is not received; , a display comprising a second level control means for outputting the output signal of the switch circuit to the image display unit with the output signal of the switch circuit attenuated in level relatively during the input period of the half blanking control signal compared to the non-input period; video signal processing circuit in the device.
(2)該復調映像信号は、該外部入力端子よりの該三原
色信号とは異なる復調された三原色信号である、実用新
案登録請求の範囲第1項記載のデ、  イスプレイ装置
における映像信号処理回路。   −(3)該復調映像
信号は、復調された三種の色差信号と輝度信号であり、
該スイッチ回路は該三種の色差信号と該第1のレベル制
御手段よりの対応する三原色信号とが美々供給され該三
種の色差信号又は該三原3色信号を選択出力すると共−
に、該輝度信号に対しては該三原色信号選択出力時には
伝送を阻止する回路である、実用新案登録請求の範囲第
1項記載のディスプレイ装置における映像信号処理回路
(2) The video signal processing circuit in the display device according to claim 1, wherein the demodulated video signal is a demodulated three primary color signal different from the three primary color signals from the external input terminal. - (3) the demodulated video signal is a demodulated three types of color difference signals and a luminance signal;
The switch circuit is supplied with the three color difference signals and the corresponding three primary color signals from the first level control means, and selectively outputs the three color difference signals or the three primary color signals.
2. The video signal processing circuit for a display device according to claim 1, which is a circuit that blocks transmission of the luminance signal when the three primary color signals are selectively output.
JP1984064657U 1984-05-01 1984-05-01 Video signal processing circuit in display device Pending JPS60177549U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984064657U JPS60177549U (en) 1984-05-01 1984-05-01 Video signal processing circuit in display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984064657U JPS60177549U (en) 1984-05-01 1984-05-01 Video signal processing circuit in display device

Publications (1)

Publication Number Publication Date
JPS60177549U true JPS60177549U (en) 1985-11-26

Family

ID=30595946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984064657U Pending JPS60177549U (en) 1984-05-01 1984-05-01 Video signal processing circuit in display device

Country Status (1)

Country Link
JP (1) JPS60177549U (en)

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