JPS60177500A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To lower a cell voltage, to improve writing efficiency and to stabilize a characteristic by forming a memory cell on the well of a semiconductor substrate, and changing over the supply voltage to its well at the time of writing and reading. CONSTITUTION:A memory cell 2 of a MIS structure is formed on a P well of an N silicone substrate. When a negative signal is applied to a write enable-WE at the time of writing, and a selecting signal is supplied from an X decoder X-DEC and a Y decoder Y-DEC, the a selecting MISFET19 is conducted and a voltage VD is applied from a write circuit W-CIR to a data line DL. At this time, the well is supplied with -3V, VBB, and a relative electric field becomes larger between a drain area of the cell 2 and the well and also between the well and a control gate. And injection/trapping of charge to a floating fate increase. At the time of reading, -WE is considered to be a positive signal, the well is supplied with the VBB of ''0''V, and reading is executed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an E P ROM (erasable pro
The present invention relates to a semiconductor memory device that is applied to a semiconductor memory device represented by gram ROM to improve its write efficiency.

[Background technology]

Semiconductor storage devices such as EFROM have been proposed that use MISFETs (MIS field effect transistors) in memory cells to achieve higher speed and higher integration.
g gate Avalanche injection
OnMO8) memory cells are used relatively often. The FAMO3 configuration includes an insulated floating gate between the semiconductor substrate and the gate (control gate), which causes an avalanche between the substrate and the drain or source, and the hot carriers generated thereby dissipate the charge by 70%. - It is possible to capture information in the ting gate and write information on it. Furthermore, information can be read out using the threshold voltage (■th) that is changed by trapping charges (for example, magazines [Nikkei Electronics J, January 5, 1981 issue, p. 181 - etc.).

In this type of memory cell, for example, in the case of an N-channel MI 5FET structure constructed on a P-type semiconductor substrate, a control and roll gate voltage Vo = 21 V is required for writing information.
, drain 4 y voltage V, "12V, source voltage vs = O
v is applied to each, but the integration is high.

Gate voltage V for miniaturization. and drain voltage■.

There has been a demand for lower voltages such as
There is a request for 0V. One possible measure to meet this demand for lower voltages is to scale down memory cells (reducing gate insulating film thickness, channel length, channel width, etc.). However, for this purpose, it is necessary to control and manufacture the dimensions of each part with high precision, and there is a problem that it is difficult to obtain a storage device with stable characteristics.

[Purpose of the invention]

An object of the present invention is to enable lower voltage of memory cells, and
It is an object of the present invention to provide a semiconductor memory device in which the writing speed is increased to improve the writing efficiency and the characteristics are stabilized.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by forming a memory cell of the MIS47 structure on a well of a semiconductor substrate and configuring the well so that the voltage supplied to the well can be switched between when writing and reading information to the memory cell, the gate voltage during writing can be changed. By achieving low voltage, drain voltage, etc., it is possible to improve the writing speed and writing efficiency, and to stabilize the characteristics.

〔Example〕

1 and 2 show a semiconductor memory device of the present invention, with FIG. 1 being a cross-sectional configuration diagram of a memory cell, and FIG. 2 being an overall circuit diagram. In this embodiment, the memory cell M-CEL is constituted by a large number of floating gate type MO8FETs, and the memory cell element 2 is formed on a Nm silicon substrate 1 as shown in FIG. That is, N-type silicon substrate 1
A P-type well 3 is formed by doping with B (boron), and a field insulating film 4 is provided on the P-type well 3 to define an element region. A gate insulating film 5 is formed on this single element region, a floating gate 6 is formed thereon, and a control gate 8 is further formed thereon via a space 111i7. Further, in the P-type well 3 under the gate insulating film 5, AS
, P (phosphorous), etc. to form an N-type source region 9.
A drain region 10 is formed. After forming an interlayer insulating film 11 such as PSG (phosphosilicate glass) by a conventional method, AA'r[poles 12 and 13 are formed on the source and drain regions 9 and 10, respectively, and at the same time, the AJi! also applies to the P+ type well contact portion 14 formed in a part of the P type well 3! There are 15 poles and 15 total. In the figure, 16 is a vaccination membrane.

Memory cell M-CE'L consisting of elements with such a configuration
As shown in FIG. 2, there are a plurality of word lines WL.

X decoder X-DEC and Y using data #JDL
Connected to decoder Y-DEC. In this case, the word line WL is partially formed by the control gate 8, and the data line DL is formed by the drain region 100A! The two X-decoders X-DEC and Y, a part of which is formed by the electrode 13,
Decoder Y-DEC is complementary MO8FET (CMO8)
An address buffer (not shown) supplies a selection signal dts of, for example, 5V voltage to the selected word line WL and data aDL, respectively, using a signal.

On the other hand, a write circuit W-CIR is connected to the word line WL via a pull-up resistor R, and a voltage of 12.5V is applied thereto. ! Pressure can be supplied to word iWL. Similarly, the data line DL is also connected to the write circuit W-CIH, and from here 8 to
A VD voltage of 10μ is supplied. Furthermore, the P-type well 3
Mohe! It is connected to the write circuit W-CIH through the electrode 15, but the P-type well 3 is connected to -'3 during information writing by a switching circuit provided inside the write circuit W-CIH.
V is supplied as the well voltage ■BB, and Ov is supplied as the well voltage ■BB during reading. Note that the source region 9 is connected to ground (OV potential).

Furthermore, sense amplifiers S and A can be connected to the data line DL to read predetermined information.

Note that 17, 18, and 19 are word line WL and data line DL.
A selection MISFET is interposed in the line, and WE is a write enable signal line.

According to the above configuration, when writing, the write enable WE
If a negative signal is input to , and a selection signal of 5■ is output from the X decoder X-DEC to one of the word lines WL,
The corresponding selection MISFET 17 is cut off and the level of the word line WL is supplied from the write circuit W-CIR. It is set to 12.5V. At the same time, Y-decoder Y-DEC
If a 5V selection signal is supplied to any of the selection MISFETs 18 from , the corresponding selection MISFET 18 will be cut off, and the corresponding selection MISFET 1 will be cut off.
A voltage is applied to the gate of this selection MISFET.
19 is brought into conduction. As a result, any data) IDL is transferred from the write circuit W-CIR to VD 8 to I
OV is supplied. At this time, the P-type well 3 is supplied with v8B of the write circuit W-CIR.

As a result, the relative electric field between the drain region 10 of the memory cell element and the P-type well 3 is the same drain voltage (2) as compared to the case where the substrate is simply at Ov potential. becomes larger than when . The same holds true between the P-type well 3 and the control gate 8. As a result, the drain voltage V. =8~10■, gate voltage V. Even if ≦12.5V,
A large amount of hot carriers are generated, and the injection and trapping of charges into the floating gate 6 increases. therefore,
It is possible to achieve a lower voltage, increase the writing speed, and improve the writing efficiency. On the other hand, since variations in characteristics of the element due to manufacturing variations can be reduced, stabilization of characteristics can be achieved.

When reading, the write enable WE is made a positive signal, while
If a low voltage is applied to one of the word lines WL in the X decoder is output and read out by sense amplifiers S and A. At this time, the P-type well 3 is
Since it is set to B-0■, reading can be performed in the same way as in the conventional case.

〔effect〕

A memory cell element with a 111 FAMO8 structure is formed on a P-type well, and -3V is supplied to this P-type well during writing and OV during reading, so that the gate voltage V during writing. and drain voltage■. The voltage can be lowered from the conventional 21V and 12V to 12.5V and 9 to IOV, respectively. Further, - reading can be performed in exactly the same manner as in the prior art.

12) By forming the memory cell element in a P-type well and supplying 13cm to the P-type well during writing, the gate voltage can be reduced.
Since the drain voltage can be lowered, it is possible to improve the 1 write speed and improve the write efficiency.

By changing the voltage supplied to the 13J P-type well, a lower voltage can be achieved, so stable memory element characteristics can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the BB voltage supplied to the P-type well during writing may be a voltage other than 13.

In some cases, P-channel MI in the N-well
The memory cell element may be configured with an SFET. Furthermore, the memory cell structure and circuit may have a configuration other than that in the embodiment.

[Application field]

The above explanation mainly focuses on the invention made by the present inventor, which is the field of application which is the background of the invention, which is the E of the FAMO8 structure.
Although the case where it is applied to pROM has been described, it is not limited thereto; for example, EEPROM
(erasable electrical program
am ROM).

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a memory cell element structure, and FIG. 2 is an overall circuit diagram. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Memory element, 3... P-type well, 6... Floating) l-t, 8... Control gate, 9-... Source region, 10... Drain region, 14... Well contact, 17, 18, 19...
MISFET for selection, M-CEL... memory cell, X-
DEC...X decoder, Y-DEC...Y decoder, W-CIR...write circuit, S, A...sense amplifier, WL...word line, DL...data line, R...pull amplifier Resistance, WE... 2-ite enable. Figure 1 Pide El

Claims (1)

[Claims] 1. A semiconductor characterized in that a memory cell having an MIS structure in which information can be written is formed in a well of a semiconductor substrate, and the voltage supplied to this well can be changed when writing information. Storage device. 2. The semiconductor memory device according to claim 1, wherein the memory cell has a 70-inch gate between the semiconductor substrate and the control gate. 8. NMIS on the P-type well formed on the N-type semiconductor substrate
3. The semiconductor memory device according to claim 1, wherein a memory cell having a structure is formed, and a voltage of 1V1 is supplied to the P-type well during information writing and OV during reading.