JPH02206094A - Voltage supply circuit for nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To supply a program voltage by a single power source by providing a power source circuit for supplying a power supply voltage, and a polarity inverting circuit having the opposite polarity of the power supply voltage, and also, for supplying a voltage whose difference to the power supply voltage becomes the program voltage. CONSTITUTION:To a gate G and a drain D of an EPROM element 1, a power supply voltage VDD is applied from a power source circuit 2. Also, to a well 5 and a source S of a semiconductor substrate 4, of the EPROM element 1, a voltage -(VPP-VDD) having the opposite polarity to the power supply voltage VDD, and also, whose difference to the power supply voltage VDD becomes a program voltage VPP is applied from a polarity inverting circuit 3. Therefore, consequently, the program voltage is applied between the gate and the source and between the source and the drain. Accordingly, the program voltage VPP can be supplied by a single power source.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage supply circuit for a nonvolatile semiconductor memory device that is rewritable, eg, electrically programmable, and erasable by ultraviolet light.

[Conventional technology]

In recent years, with the rapid spread of 04 devices and microprocessors, rewritable ROMs such as EFROM
(Electrically Programmab
In response to the demand for larger capacity (LE ROM), even 1M bit class products have appeared on the market.

[Problem to be solved by the invention]

The technical challenges required of chip suppliers to increase the capacity of nonvolatile semiconductor memory devices can be summarized in the following three items.

That is, reduction of chip area by miniaturization of +IIEFROM elements, (2) reduction of programming voltage and high-speed programming, and (3) CMO5 implementation of peripheral circuits to enable lower power consumption.

For the sake of explanation below, the gate threshold voltage of the EPROM element in the data erased state will be abbreviated as VTMψ, and the threshold voltage in the data programmed state will be abbreviated as VTMI. VTM
φ depends on the shape of the EPIIOM element and the substrate concentration, and since the cell shape is also limited as the EPROM element becomes finer as described in (1) above, the contribution of the substrate concentration becomes large. (2) In order to lower the programming voltage, a low VTMφ is required to ensure the operating margin of products using EPROM elements.
Since the substrate concentration becomes thinner, it becomes disadvantageous in terms of programming time. In other words, it is preferable to have a high substrate concentration for high-speed programming, and in that case, VTMφ will inevitably increase and the programming characteristics will improve, but the operating margin will be high and narrow, which is not compatible with lowering the programming voltage. It happens.

Also, when programming a normal EPROM element, a programming voltage is applied to the gate and drain, and the EPROM
A programming voltage applied to the gate causes the channel phototrectron flowing in the channel region of the device to penetrate the oxide film and accumulate in the intermediate layer. In this way, EP
In order to supply a program voltage to the ROM element, two types of external power supply systems, a power supply circuit and a high-voltage power supply circuit, are required, which makes it difficult to convert the peripheral circuitry described in (3) into a CMO3.

Furthermore, the presence of two types of external power supply systems is a cause of damage to miniaturization of EPROM elements and reduction in voltage and speed of programming.

Therefore, an object of the present invention is to provide a voltage supply circuit for a nonvolatile semiconductor memory device that can be used as a single power supply.

[Means to solve the problem]

The voltage supply circuit of the nonvolatile semiconductor memory device of the present invention includes:
an EPROM element, a power supply circuit that supplies a power supply voltage to the gate and drain of the EPROM element;
The device includes a polarity inverting circuit that supplies a voltage having a polarity opposite to the power supply voltage to the well and source of the semiconductor substrate of the OM element, and whose difference from the power supply voltage is a programming voltage.

[Effect]

According to the structure of the present invention, a power supply voltage is applied to the gate and drain of the EPROM element from the power supply circuit, and
A voltage having a polarity opposite to the power supply voltage and whose difference from the power supply voltage is a program voltage is applied by a polarity inversion circuit to the well and source of the semiconductor substrate of the ROM element.

Therefore, a program voltage is applied between the gate and source and between the source and drain. Therefore, the program voltage can be supplied by a single power supply.

Also, the program voltage is applied to each MOS of the EPROM element.
) Since the voltage is not applied to the transistor, there is no need for any special measures to increase the voltage for the MOS transistor.

〔Example〕

An embodiment of the present invention will be described based on FIGS. 1 to 4. That is, the voltage supply circuit of this nonvolatile semiconductor memory device includes an EPROM element 1, a power supply circuit 2, and a polarity inversion circuit 3.

The EPROM element 1 is formed in a p-type well 5 in an n-type semiconductor substrate 4, as shown in FIG.
This is an element consisting of an oxide film, a second conductor, an oxide film, and a semiconductor substrate. The peripheral circuit of the EPROM element 1 is composed of a CMO5 (complementary MO3) logic circuit, and the nonvolatile semiconductor device is an EPI? The leaf element 1 is used as a memory cell Qm and is configured to be erasable by ultraviolet light and electrically programmable. memory cell Q
m is a type of n-channel type MO3 field effect transistor having an n1 source/drain diffusion layer region 6,
Between the gate G and the channel region, there is a floating layer completely insulated from the surroundings by a silicon oxide film 7.
A gate (conductive type semiconductor) 8 is located.

9 is an element isolation film.

The power supply circuit 2 supplies a power supply voltage VDI) to the gate G and drain D of the EPROM element 1, as shown in FIG.

This power supply circuit 2 is used for peripheral CMO8 circuits.

As shown in FIG. 2, the polarity reversing circuit 3
A power supply voltage V is applied to the well 5 and source S of the semiconductor substrate 4 of
A voltage that has the opposite polarity to DD and whose difference from the power supply voltage VDD is the program voltage VpP ■BB-”PP-■DD
＞ is supplied. As a result, the program voltage VPP is substantially applied between the gate G and eight sources and between the source S and drain D of the EPROM element 1, and programming becomes executable. In this case, the voltage VBB-(
(2) The absolute value of PP-VDD) is a value that corresponds to the capability of the program element of the EPIIOM element 1, and if the element is programmed with a low voltage, -(2,.

■The absolute value of DD) inevitably becomes smaller. Note that, as shown in FIG. 2, the well 6 is fixed at a voltage VBB having a polarity opposite to the power supply voltage VDD.

FIG. 3 is a logic diagram showing an example of a polarity inversion circuit. In this circuit, charge is accumulated in the capacitor 10, and by switching the power supply voltage DD applied to the capacitor to the ground potential, the polarity of the voltage at the other electrode is reversed. The voltage VBB=(VPP VDD) which is output with its polarity inverted is determined by circuit constants and conforms to the programming characteristics of the EPROM element 1.

FIG. 4 shows the X decoder 11. The configuration of an array of Y decoder 12, polarity inversion circuit 3, and EPROM element 1 is shown. X
A predetermined E is determined by the signals from the decoder 11 and Y decoder 12.
PROM element l is selected. At this time, the well 5 and source S of all EPRO gate elements 1 are -(V,).

VDD) is applied.

According to this embodiment, a power supply voltage VDD is applied from a power supply circuit 2 to the gate G and drain D of the EPROM element 1, and a polarity inverting circuit 3 applies a power supply voltage VDD to the well 5 and source S of the semiconductor substrate 4 of the EPROM element 1. A voltage −(VPP 'DD> is applied that has the opposite polarity to the power supply voltage vDD and whose difference from the power supply voltage DD is the program voltage VPP. Therefore, the program voltage is applied between the gate and source and between the source and drain. is applied. Therefore, the program voltage VPP can be supplied by a single power supply. Also, the program voltage VpP is
Since the voltage is not applied to the individual MOS transistors of the M element 1, no special measures are required to increase the voltage of the MOS transistors.

Furthermore, this embodiment can respond to the program characteristics of the EPROM element 1 by changing the circuit constants of the power supply circuit 2 and the polarity inverting circuit 3. Further, the power supply circuit 2 can be simplified, and a CMOS logic circuit can be constructed using, for example, a normal CMOS manufacturing process.

In the above embodiment, the semiconductor substrate 4 is of n-type and the well 5 is of p-type, but the semiconductor substrate 4 may be of p-type and the well 5 may be of n-type.

〔Effect of the invention〕

According to the nonvolatile semiconductor memory device of this invention, EFRO
A power supply circuit that supplies a power supply voltage to the M element, the gate and drain of this EFROM element, and a well and source of a semiconductor substrate of the EFROM element having a polarity opposite to the power supply voltage and a difference from the power supply voltage programmed. Equipped with a polarity reversal circuit that supplies the voltage,
Program voltage can be supplied by a single power supply. Also, the program voltage is applied to each MOS of the EFROM element.
) Since the voltage is not applied to the transistor, there is an advantage that there is no need for special measures to increase the voltage of the MOS transistor.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a semiconductor according to an embodiment of the present invention, FIG. 2 is a wiring diagram for applying voltage, FIG. 3 is a polarity inversion circuit diagram, and FIG. 4 is an overall schematic wiring diagram. 1...EFROM element, 2...power supply circuit, 3...
Polarity inversion circuit, 4... semiconductor substrate, 5... well,
G...gate, D...drain, S...source,
VDD...power supply voltage, ■pp...program voltage,
■BB...voltage with opposite polarity

Claims (1)

[Claims] an EPROM element, a power supply circuit that supplies a power supply voltage to the gate and drain of the EPROM element;
Voltage supply for a non-volatile semiconductor memory device, comprising: a polarity inverting circuit that supplies a voltage having a polarity opposite to the power supply voltage to the well and source of a semiconductor substrate of an OM element and whose difference from the power supply voltage is a programming voltage. circuit.