JPS60171827A - Pulse width modulation circuit - Google Patents
Pulse width modulation circuitInfo
- Publication number
- JPS60171827A JPS60171827A JP59027741A JP2774184A JPS60171827A JP S60171827 A JPS60171827 A JP S60171827A JP 59027741 A JP59027741 A JP 59027741A JP 2774184 A JP2774184 A JP 2774184A JP S60171827 A JPS60171827 A JP S60171827A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse
- pulse width
- width modulation
- waveform
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 claims abstract description 9
- 239000003990 capacitor Substances 0.000 abstract description 6
- 239000000872 buffer Substances 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract 2
- 230000005284 excitation Effects 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
Landscapes
- Control Of Motors That Do Not Use Commutators (AREA)
Abstract
Description
【発明の詳細な説明】
(技術分野)
本発明は入力パルスをパルス幅変調するパルス幅変調回
路に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a pulse width modulation circuit that pulse width modulates an input pulse.
(従来技術)
従来、パルス幅変調回路は第1図に示すように入力パル
スを抵抗1及びコンデンサ2よりなる第1の積分器で積
分してコンパレータ3により基準電圧で2値化し、その
出力パルスを抵抗4及びコンデンサ5よりなる第2の積
分器で積分してコンパレータ3に基準電圧として加える
と共にコンパレータ6により第1の積分器の出力信号を
第2の積分器の出力電圧で2値化している。(Prior art) Conventionally, as shown in FIG. 1, a pulse width modulation circuit integrates an input pulse using a first integrator consisting of a resistor 1 and a capacitor 2, converts it into a binary value using a reference voltage using a comparator 3, and outputs the resulting pulse. is integrated by a second integrator consisting of a resistor 4 and a capacitor 5 and applied as a reference voltage to a comparator 3, and the output signal of the first integrator is binarized by the output voltage of the second integrator by a comparator 6. There is.
しかしこのパルス幅変調回路にあってはコンパレータ3
,6はリニアICLか用いることができずロジックIC
を用いることができないので、コスト高になる。また積
分器を2つ用いるので、大型になってしまう。However, in this pulse width modulation circuit, comparator 3
, 6 is a linear ICL or a logic IC that cannot be used.
cannot be used, resulting in high costs. Furthermore, since two integrators are used, the size becomes large.
(目 的)
本発明は上記欠点を改善し、コストダウン及び小型化を
計ることができるパルス幅変調回路を提供することを目
的とする。(Objective) It is an object of the present invention to provide a pulse width modulation circuit that can improve the above-mentioned drawbacks and achieve cost reduction and miniaturization.
(構 成)
以下図面を参照しながら本発明を実施例に基づき説明す
る。(Structure) The present invention will be described below based on examples with reference to the drawings.
第2図は本発明を応用したグラ/レスモータ位相制御方
式の一例を示す。FIG. 2 shows an example of a graph/less motor phase control system to which the present invention is applied.
ブラシレスモータは2極の永久磁石よりなるロータ11
を4相コイル12〜15の発生する回転磁界で回転させ
、2個のホール素子16.17よりなる位置検出器でロ
ータ11の回転位置を検出する。速度検出器18はロー
タ11に連結された多極の永久磁石19と検出コイル2
0よりなり、検出コイル20が永久磁石19の回転を検
出して速度信号を発生する。A brushless motor has a rotor 11 made of two-pole permanent magnets.
is rotated by the rotating magnetic field generated by the four-phase coils 12 to 15, and the rotational position of the rotor 11 is detected by a position detector consisting of two Hall elements 16 and 17. The speed detector 18 includes a multipolar permanent magnet 19 connected to the rotor 11 and a detection coil 2.
0, the detection coil 20 detects the rotation of the permanent magnet 19 and generates a speed signal.
この速度信号は波形整形回路−21で矩形波に整形され
、位相比較器22において水晶振動子23及び分周器2
4よりなる基準信号発生器からの基準信号(クロックパ
ルス)と位相比較される。この位相比較器22の出力パ
ルスはパルス幅変調器25によりパルス幅変調されてパ
ルス幅が広くなり、オア回路26で位相比較器22の出
力パルスがパルス幅変調器25の出力パルスに加算され
てパルス幅変調器25による位相遅れが補正される。ま
たホール素子16.17からの7r/2ずれた2相信号
は波形整形回路27.28で矩形波に整形され、インバ
ータ29゜30で反転される。分配回路31は波形整形
回路27゜28及びインバータ29.30の出力信号を
エンコーダでエンコードして各相コイル12〜15の励
磁信号を順次に作り、オア回路26からアンド回路32
を介して入力される制御信号と上記励磁信号とのアンド
をとることにより励磁信号を制御信号でオンオフ制御し
てl相ユニポーラ駆動回路33に出力する。駆動回路3
3は分配回路31がらの各相の励磁信号によりコイル1
2〜15を順次に励磁してロータ11を回転させる。し
たがってロータ11の回転は分周器24からの基準信号
に基づいて位相制御される。tたブラシレスモータの起
動時はオア回路26の出力パルス幅が大きくてコイル1
2〜15に大きな電流が流れるが、この電流が電流検出
抵抗34で検出されてその検出信号が起動回路35でオ
ンオフされアンド回路32を介して分配回路31に加え
られる。したがって分配回路31は起動回路35の出力
信号によりコイル励磁信号をオンオフ制御してコイル電
流を制限する。This speed signal is shaped into a rectangular wave by a waveform shaping circuit 21, and a crystal oscillator 23 and a frequency divider 2 are passed through a phase comparator 22.
The phase of the clock pulse is compared with a reference signal (clock pulse) from a reference signal generator consisting of four clock pulses. The output pulse of this phase comparator 22 is pulse width modulated by a pulse width modulator 25 to widen the pulse width, and the output pulse of the phase comparator 22 is added to the output pulse of the pulse width modulator 25 in an OR circuit 26. The phase delay caused by the pulse width modulator 25 is corrected. Further, the two-phase signals shifted by 7r/2 from the Hall elements 16 and 17 are shaped into rectangular waves by waveform shaping circuits 27 and 28, and inverted by inverters 29 and 30. The distribution circuit 31 encodes the output signals of the waveform shaping circuits 27 and 28 and the inverters 29 and 30 with an encoder to sequentially generate excitation signals for each phase coil 12 to 15, and outputs them from an OR circuit 26 to an AND circuit 32.
By ANDing the control signal inputted through the control signal and the excitation signal, the excitation signal is turned on and off with the control signal and outputted to the l-phase unipolar drive circuit 33. Drive circuit 3
3, the coil 1 is activated by the excitation signal of each phase from the distribution circuit 31.
2 to 15 are sequentially excited to rotate the rotor 11. Therefore, the rotation of rotor 11 is phase controlled based on the reference signal from frequency divider 24. When the brushless motor is started, the output pulse width of the OR circuit 26 is large and the coil 1
A large current flows through circuits 2 to 15, and this current is detected by a current detection resistor 34, and a detection signal thereof is turned on and off by a starter circuit 35 and applied to a distribution circuit 31 via an AND circuit 32. Therefore, the distribution circuit 31 controls the coil excitation signal on and off based on the output signal of the starting circuit 35 to limit the coil current.
第3図は本発明の一実施例を示し、この実施例は上記パ
ルス幅変調器25及びオア回路26を構成している。パ
ルス幅変調器25はバッファ36.17、抵抗38.3
9、コンデンサ40.41、インバータ42゜43によ
り構成され、オア回路26はノア回路44が用いられて
いる。位相比較器22がらの入力パルスはバッファ36
.37を通って抵抗38及びコンデンサ40よりなる積
分器で積分され、インバータ42及び抵抗39よりなる
増幅器で増幅されてインバータ43よりなる波形整形回
路でパルス波形に整形される。このインバータ43の出
力パルス及び位相比較器22からの入力パルスはノア回
路44で加算及び反転をされてアンド回路32へ加えら
れる。ここにバッファ36.37及びインバータ42.
43はロジックICであり、バッファ36.37は必要
に応じて用いられる。FIG. 3 shows an embodiment of the present invention, in which the pulse width modulator 25 and the OR circuit 26 are configured. The pulse width modulator 25 includes a buffer 36.17 and a resistor 38.3.
9, capacitors 40 and 41, and inverters 42 and 43, and a NOR circuit 44 is used as the OR circuit 26. The input pulse from the phase comparator 22 is sent to the buffer 36.
.. 37, is integrated by an integrator made up of a resistor 38 and a capacitor 40, amplified by an amplifier made up of an inverter 42 and a resistor 39, and shaped into a pulse waveform by a waveform shaping circuit made up of an inverter 43. The output pulse of the inverter 43 and the input pulse from the phase comparator 22 are added and inverted by a NOR circuit 44 and then applied to an AND circuit 32. Buffers 36, 37 and inverters 42.
43 is a logic IC, and buffers 36 and 37 are used as necessary.
(効 果)
以上のように本発明によれば入力パルスを積分器で積分
して増幅器で増幅し波形整形回路で波形整形するので、
ロジックICを用いて安価に構成することができ、積分
器は1つだけで2つ用いる必要がないから小型にできる
。(Effects) As described above, according to the present invention, the input pulse is integrated by the integrator, amplified by the amplifier, and waveform-shaped by the waveform shaping circuit.
It can be constructed at low cost using a logic IC, and it can be made smaller because it only uses one integrator and there is no need to use two.
第1図は従来のパルス幅変調回路を示す回路図、第2図
はブランレスモーフ位相制御方式の一例を示すブロック
図、第3図は本発明の一実施例を示す回路図である。
38、39・・・抵抗、40・・コンデンサ、42、
43・インバータ。FIG. 1 is a circuit diagram showing a conventional pulse width modulation circuit, FIG. 2 is a block diagram showing an example of a blurless morph phase control method, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. 38, 39...Resistor, 40...Capacitor, 42,
43. Inverter.
Claims (1)
が入力される増幅器と、この増幅器の出力信号をパルス
波形に整形する波形整形回路とを備えたパルス幅変調回
路。A pulse width modulation circuit comprising an integrator that integrates an input pulse, an amplifier to which the output signal of the integrator is input, and a waveform shaping circuit that shapes the output signal of the amplifier into a pulse waveform.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59027741A JPS60171827A (en) | 1984-02-16 | 1984-02-16 | Pulse width modulation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59027741A JPS60171827A (en) | 1984-02-16 | 1984-02-16 | Pulse width modulation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60171827A true JPS60171827A (en) | 1985-09-05 |
Family
ID=12229454
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59027741A Pending JPS60171827A (en) | 1984-02-16 | 1984-02-16 | Pulse width modulation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60171827A (en) |
-
1984
- 1984-02-16 JP JP59027741A patent/JPS60171827A/en active Pending
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