JPS60171730A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60171730A
JPS60171730A JP2902884A JP2902884A JPS60171730A JP S60171730 A JPS60171730 A JP S60171730A JP 2902884 A JP2902884 A JP 2902884A JP 2902884 A JP2902884 A JP 2902884A JP S60171730 A JPS60171730 A JP S60171730A
Authority
JP
Japan
Prior art keywords
etching
opening
semiconductor layer
region
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2902884A
Other languages
Japanese (ja)
Inventor
Kazuyuki Kurita
栗田　和行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2902884A priority Critical patent/JPS60171730A/en
Publication of JPS60171730A publication Critical patent/JPS60171730A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE:To enable the formation of an aperture having a large aspect ratio, by introducing an impurity into a semiconductor layer exposed by forming an aperture on an etching mask layer on the semiconductor layer, and then etching the semiconductor layer region where the impurity is introduced. CONSTITUTION:An etching mask layer 2 is formed on a semiconductor layer 1 with a material such as PSG which is strong enough to sustain several times of dry etching. After a resist film 3 is provided thereon, an aperture 4 is formed in the etching mask layer 2 by means of photolithography. The semiconductor layer 1 is subjected to dry etching through the opening so that the opening is deepened. Ions of arsenic or boron are implanted at a relatively high temperature, whereby the etching grade is raised only in the region as indicated by the marks (+) in the drawing where the atoms are implanted. Subsequently, the semiconductor layer 2 is again subjected to dry etching through the opening 4 so as to further deepen the aperture. In this etching process, side etching is inhibited since the etching grade is raised only in the direction of depth.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明は、半導体装置の製造方法に関する。特に、半導
体層に、アスペクト比（開口の深さと幅との比）の大き
な開口を形成する工程を有する半導体装置の製造方法と
、半導体層に、深さの異なる複数の開口を１回の（共通
の）エツチング工程をもって形成する工程を有する半導
体装置の製造方法とに関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, there is a method for manufacturing a semiconductor device that includes a step of forming an opening with a large aspect ratio (the ratio of the depth to width of the opening) in a semiconductor layer, and a method for manufacturing a semiconductor device that includes a step of forming an opening with a large aspect ratio (ratio of the depth to width of the opening) in the semiconductor layer, and a method for manufacturing a semiconductor device that includes the step of forming an opening with a large aspect ratio (ratio of the depth to width of the opening) in the semiconductor layer. The present invention relates to a method of manufacturing a semiconductor device including a step of forming it using a common etching step.

（２）技術の背景 コ１′・導体装置の製造方法には、アスペクト比の大き
な開【１を形成する要請がある。バイポーラトランジス
タのｄ重体素子分離等を可能にするためである。また、
′深さの異なる複数の開口を形成する波請もある。ウォ
ールドエミッタ型バイポーラトランジスタの製造工程等
に必要だからである。(2) Background of the Technology In the method of manufacturing a conductor device, there is a need to form an aperture with a large aspect ratio. This is to enable separation of d-heavy elements of bipolar transistors. Also,
'There are also ripples that form multiple openings with different depths. This is because it is necessary for the manufacturing process of walled emitter type bipolar transistors.

（３）従来技術と問題点 従来技術におけるアスペクト比の大きな開口を形成する
方法、特に、１回の（共通の）エツチング」程をもって
深さの異なる複数の開口を形成する方法は、従来技術に
おいては知られていない。(3) Prior Art and Problems The method of forming openings with a large aspect ratio in the prior art, especially the method of forming multiple openings with different depths in one (common) etching process, is not known.

しかし、か−る要請の存在することは１以上のとおり、
明らかである。However, the existence of such a request is as follows:
it is obvious.

（４）発明の目的 本発明の［」的は、か−る要請にこたえるものであり、
アスペクト比の大きな開口を形成する工程を４１する半
導体装置の製造方法と、半導体層に、深さの異なる複数
の開口を１回の（共通の）エツチング工程をもって形成
する工程を有する半導体装置の製造方法とを提供するこ
とにある。(4) Purpose of the Invention The purpose of the present invention is to meet the above requirements.
A method for manufacturing a semiconductor device that includes a step of forming an opening with a large aspect ratio; and a method for manufacturing a semiconductor device that includes a step of forming a plurality of openings with different depths in a semiconductor layer in one (common) etching step. The purpose is to provide a method.

（５）発明の構成 本発明の構成は、半導体層上にエツチング用マスク層を
形成し、該エツチング用マスク層を開口し該半導体層を
露出し、前記露出した半導体層に対して前記開口を介し
て不純物を導入し、該不純物が導入された半導体層をエ
ツチングする工程を含むことを特徴とする半導体装置の
製造方法と、半導体層」二にマスク膜を形成し、該マス
ク膜を開目し該半導体層の深い開口の形成予定領域を露
出し、前記露出した半導体層に前記開口を介して不純物
を４人し、該半導体層の深い開口の形成予定領域と浅い
開口との形成予定領域に対してエツチングをなす工程を
有する半導体装置の製造方法とにある。(5) Structure of the Invention The structure of the present invention is to form an etching mask layer on a semiconductor layer, open the etching mask layer to expose the semiconductor layer, and open the opening to the exposed semiconductor layer. A method for manufacturing a semiconductor device comprising the steps of introducing an impurity through a semiconductor layer and etching the semiconductor layer into which the impurity has been introduced, forming a mask film on the semiconductor layer, and opening the mask film. and exposing a region of the semiconductor layer where a deep opening is to be formed, and applying impurities to the exposed semiconductor layer through the opening, and forming a region of the semiconductor layer where a deep opening is to be formed and a region where a shallow opening is to be formed. A method of manufacturing a semiconductor device includes a step of etching the semiconductor device.

換言すれば１本発明は、不純物を含む半導体に対するド
ライエツチングのエツチングレートが。In other words, one aspect of the present invention is that the etching rate of dry etching for semiconductors containing impurities is improved.

不純物を含まない半導体に対するドライエツチングのエ
ツチングレートよりはるかに高いという白熊法則を利用
したものであり、ドライエツチング法をもって開口を形
成しようとする領域のみに。This method takes advantage of the polar bear law, which states that the etching rate is much higher than the etching rate of dry etching for semiconductors that do not contain impurities, and is applied only to areas where openings are to be formed using the dry etching method.

イオン注入法等を使用して不純物を導入してその領域の
みの不純物濃度を増大しておくものである。そして、ア
スペクト比の大きな開口を形成する（」的のためには、
まず、エツチングマスクを形成した後、不純物の導入と
エツチングとの組み合わせ工程を必要に応じて繰り返す
こととし、サイドエツチングの発生を抑制しながら、深
さ方向のみにエツチングをなさしめるものであり、半導
体層に、深さの異なる複数の開口を１回の（共通の）Ｊ
工程をもって形成する目的のためには、まず、深い開口
の形成予定領域のみに不純物を導入してこの領域のみの
エツチングレートを上昇してから、半導体層全面にエツ
チング用マスク層を形成し、このエツチング用マスク層
の所望の領域に開「１を形成し、これをエツチングマス
クとしてエツチングをなし、上記の不純物が導入されて
エツチングレートの上昇している領域には深い開ＩＩＩ
を、不純物が導入されていない領域には浅い開１」を形
成するものである。Impurities are introduced using ion implantation or the like to increase the impurity concentration only in that region. Then, for the purpose of forming an aperture with a large aspect ratio,
First, after forming an etching mask, the process of introducing impurities and etching is repeated as necessary, and etching is performed only in the depth direction while suppressing the occurrence of side etching. Multiple openings with different depths in one (common) J
In order to form the etching through a process, first, impurities are introduced only into the region where the deep opening is to be formed to increase the etching rate only in this region, and then an etching mask layer is formed over the entire surface of the semiconductor layer. An opening 1 is formed in a desired region of the etching mask layer, and etching is performed using this as an etching mask.A deep opening III is formed in the region where the above impurity is introduced and the etching rate is increased.
A shallow opening 1'' is formed in the region where no impurity is introduced.

（６）発明の実施例 以下、図面を参照しつ−、本発明のそれぞれの実施例に
係る開口形成工程を説明する。(6) Embodiments of the Invention Hereinafter, an opening forming process according to each embodiment of the invention will be explained with reference to the drawings.

第１図本読 半導体層ｌに、ＰＳＧ等複等四数回ライエツチングに酎
える強靭な材料をもって、　１．５ＪＬ塵程度の厚さに
エツチング用マスク層２を形成する。An etching mask layer 2 is formed on the semiconductor layer 1 of FIG. 1 to a thickness of about 1.5 JL using a strong material such as PSG that can be etched several times.

フォトリソグラフィー法を使用して、開口形成予定領域
のみから上記のエンチング用マスク層２を除去して、幅
が１ＩＬＩ１１以下の開口４をエツチング用マスク層２
に形成する。図において、３はフォトリソグラフィー法
に使用したレジスト膜であり、厚さｌＩＬ鵬程度である
。Using a photolithography method, the etching mask layer 2 is removed only from the region where the opening is to be formed, and the etching mask layer 2 is formed to form an opening 4 having a width of 1ILI11 or less.
to form. In the figure, numeral 3 is a resist film used in the photolithography method, and its thickness is about 1L.

第２図参照 開口を介して、半導体層ｌにドライエツチングを実行し
て、開口４の深さを深くする。このエツチングによって
は、サイドエッチの発生を抑制するためエツチング深さ
は２．５１Ｌｍ以下に止めることがよい。Dry etching is performed on the semiconductor layer 1 through the opening shown in FIG. 2 to increase the depth of the opening 4. Depending on this etching, the etching depth is preferably limited to 2.51 Lm or less in order to suppress the occurrence of side etching.

ヒ素、ポロン等を比較的高濃度にイオン注入する。この
イオン注入はウェーハの全面になしてさしつかえないが
、注入された原子は、開口４以外の領域においては当然
レジストｌ１５Ｉ３に吸収されるので、開口４内におい
てのみ半導体層ｌ中の不純物濃度が上昇し、図に「＋」
をもって示す原子の注入された領域においてのみエツチ
ングレートが１ユ昇する。この工程に使用する不純物に
は全く制限はない。Arsenic, poron, etc. are ion-implanted at a relatively high concentration. This ion implantation can be carried out over the entire surface of the wafer, but since the implanted atoms are naturally absorbed by the resist l15I3 in areas other than the opening 4, the impurity concentration in the semiconductor layer l increases only in the opening 4. and mark "+" on the diagram.
The etching rate increases by 1 unit only in the region where atoms are implanted, which is indicated by . There are no restrictions on the impurities used in this step.

つりいて、再び開口４を介して、半導体層ｌにドライエ
ツチングを実行して、開口４の深さを深くする。このエ
ツチングによっては、深さ方向のみのエツチングレート
が上昇しているので、サイドエッチが抑制される。Then, dry etching is again performed on the semiconductor layer l through the opening 4 to increase the depth of the opening 4. This etching increases the etching rate only in the depth direction, so side etching is suppressed.

第３図参照 所望により、不純物導入工程（イオン注入工程）とドラ
イエツチング工程とを複数回繰り返す、たり、開口４の
上部では僅かながらサイドエッチが進行するから、あま
りに多数回繰り返すことは意味がないことは云うまでも
ない。Refer to Figure 3. If desired, the impurity introduction step (ion implantation step) and dry etching step may be repeated multiple times, or there is no point in repeating them too many times since side etching will progress slightly in the upper part of the opening 4. Needless to say.

以上の工程によって、アスペクト比が大きな開口を形成
することができる。Through the above steps, an opening with a large aspect ratio can be formed.

以下１例えば、開口４の内面を酸化（Ｕ溝酸化）し、開
口４を多結晶シリコン層をもって埋め込めば、良＆イな
素子分離が可能である（図示せず）、上記のアスペクト
比の大きな開口を如何様に利用するかは自由である。Below 1 For example, if the inner surface of the opening 4 is oxidized (U-groove oxidation) and the opening 4 is filled with a polycrystalline silicon layer, it is possible to achieve good element isolation (not shown). You are free to use the opening in any way you like.

第４図参照 半導体層ｌ上に、レジス）　ＩＩ！２３を厚さｌル履程
度に形成した後、フォトリソグラフィ一工程を使用して
、このレジスト膜３を深い開口（例えば素子分離用開口
）の形成予定領域上から除去して開口５を形成し５この
間口５を介してヒ素、ポロン等を半導体層ｌ中にイオン
注入する。この工程により１図に「＋」をもって示す原
子の注入された領域においてのみエツチングレートが上
昇する。(Refer to FIG. 4, on the semiconductor layer l, there is a resist) II! After forming the resist film 23 to a thickness of approximately 1.5 mm, the resist film 3 is removed from the region where a deep opening (for example, an opening for element isolation) is to be formed using a photolithography process to form an opening 5. 5 Arsenic, poron, etc. are ion-implanted into the semiconductor layer 1 through this opening 5. Through this step, the etching rate increases only in the region where atoms are implanted, which is indicated by "+" in FIG.

第５図参照 使用済みのレジスト膜３を除去した後、モリブデンシリ
サイド等よりなるエツチング用マスク層６を　１．５４
ｍ程度の厚さに形成する。この工程に使用する方法には
制限はない、ＣＶＤ法でもスパッター法でも使用可能で
ある。Refer to FIG. 5. After removing the used resist film 3, an etching mask layer 6 made of molybdenum silicide, etc.
It is formed to a thickness of about m. There are no restrictions on the method used in this step; either the CVD method or the sputtering method can be used.

１５６図参照 フォトリソグラフィー法を使用して、深い開口（例えば
素子分離用開口）と浅い開口（例えばウォールドエミッ
タ型バイポーラトランジスタのエミッタ拳ベースとコレ
クタとの隔壁用開口）との形成予定領域上から、上記の
エツチング用マスク層６を除去して、開口５°を形成す
る０図において、７は厚さがｌＪＬｍ程度のレジスト膜
である。Using a photolithography method (see Figure 156), from above the area where deep openings (for example, openings for element isolation) and shallow openings (for example, openings for partitions between the emitter base and the collector of a walled emitter type bipolar transistor) are to be formed, In Figure 0, in which the etching mask layer 6 is removed to form an opening of 5°, 7 is a resist film having a thickness of about 1JLm.

第７図参照 開１５′を介して、半導体層ｌにドライエツチングを実
行して、半導体層１中に深さの異なる開１１８．８゛を
形成する。このドライエツチング工程において、前工程
で不純物が導入されてエツチングレートが上昇している
領域（図に「＋」をもって示す原子の注入された領域）
においてエツチングは急速に進行するから、深い開口８
と浅い開口８°　とが同時に形成される。Dry etching is performed on the semiconductor layer 1 through the openings 15' in FIG. 7 to form openings 118.8' in the semiconductor layer 1 with different depths. In this dry etching process, there is a region where impurities are introduced in the previous step and the etching rate is increased (the region where atoms are implanted, indicated by "+" in the figure).
Since etching progresses rapidly in the deep opening 8
and a shallow opening of 8° are formed at the same time.

第８図参照 使用済みのレジスト膜７とエツチング用マスク層６とを
除去する。Referring to FIG. 8, the used resist film 7 and etching mask layer 6 are removed.

以上の工程をもって、深さの異なる複数の開口が１回の
（共通の）エツチング工程をもって形成される。Through the above steps, a plurality of openings having different depths are formed in one (common) etching step.

第９図参照 以下、公知の工程により、例えば、図示するように、ウ
ォールドエミッタ型バイポーラトランジスタ等を製造す
ることができる０図において、ｌ゛はｎ型のコレクタ領
域であり、９は上記の深い開口８の内面を酸化した後、
この間口８を多結晶シリコン層をもって埋めて形成した
素子分離であり、１０は素子分離と同様の工程をもって
開［］８゛を埋めて形成したエミッタｅベースとコレク
タとの隔壁であり、１１はｐ型のベースであり、１２は
ｎ型のエミー２夕である。１３はフィールド絶縁膜であ
り、１４．１５．１６は、それぞれ、エミッタ電極、ペ
ース電極、コレクタ電極である。１７は本発明に係る開
口形成工程に先立ち、半導体層１中に、ｎ型のコレクタ
領域１′より深く形成された高濃度不純物理め込み層で
ある。Refer to FIG. 9. In FIG. 0, for example, as shown in the figure, a walled emitter type bipolar transistor, etc. can be manufactured by a known process. After oxidizing the inner surface of the opening 8,
Element isolation is formed by filling this opening 8 with a polycrystalline silicon layer, 10 is a partition between the emitter e base and the collector formed by filling the opening 8' in the same process as the element isolation, and 11 is a partition wall between the emitter e base and the collector. It is a p-type base, and 12 is an n-type emmy 2 base. 13 is a field insulating film, and 14, 15, and 16 are an emitter electrode, a pace electrode, and a collector electrode, respectively. Reference numeral 17 denotes a high-concentration impurity physical implantation layer formed in the semiconductor layer 1 deeper than the n-type collector region 1' prior to the opening forming step according to the present invention.

なお、上記の深さの異なる複数の開口を如何様に利用す
るかは自由である。Note that it is free to use the plurality of openings having different depths.

７、発明の効果 以１−説明せるとおり、本発明によれば、アスペクト比
の大きな開口を形成する工程を有する半導体装４の製造
方法と、半導体層に、深さの異なるＩｎの開ＩＪを１回
のエツチング工程をもって形成［る工程をイ１する半導
体装置の製造方法とを提供することができる。7. Effects of the Invention 1- As explained, the present invention provides a method for manufacturing a semiconductor device 4 that includes a step of forming an opening with a large aspect ratio, and a method for manufacturing a semiconductor device 4 that includes a step of forming an opening with a large aspect ratio, and a method for forming an open IJ of In with different depths in a semiconductor layer. It is possible to provide a method for manufacturing a semiconductor device that can be formed by a single etching process.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図〜第３図は本発明の実施例に係るアスペクト比の
大きな開口を形成する主要工程を説明する基板断面図で
ある。第４１Δ〜第８図は本発明の実施例に係る深さの
異なる複数の開「１を１回の（）１：通の）エツチング
工程をもって形成する主要１程を説明する基板断面図で
あ°す、第、９図は、第８図に示す開口を利用して製造
したウォールドエミッタ型バイポーラトランジスタの基
板断面図である。 １・・・半導体層、１゛　・・・ｎ型のコレクタ領域、
２．６・・・エツチング用マスク層。 ３．７＃争ΦレジストＩＩＱ、４．５．５′　・ΦΦ閉
開口　８００．深い開口、８’　＊　ｅ　＊浅い開［１
、９・、・・素子分離、　１０・　・・隔壁、１１　・
Φ・ｐ型のベース領域、　１２・・・ｎ型のエミッタ領
域、１３−、−−フィールド絶縁膜。 １４　・　争拳エミッタ゛屯Ｊｉ、　１５・・・ベース
電極、　１６・・・コレクタ電極、　１７１１・・高濃
度第１図 第２図 第３図1 to 3 are cross-sectional views of a substrate illustrating the main steps of forming an opening with a large aspect ratio according to an embodiment of the present invention. 41Δ to 8 are substrate cross-sectional views illustrating the main step 1 in which a plurality of openings 1 having different depths are formed in one etching process according to an embodiment of the present invention. Figure 9 is a cross-sectional view of the substrate of a walled emitter bipolar transistor manufactured using the opening shown in Figure 8. 1... Semiconductor layer, 1'... N-type collector region. ,
2.6...Etching mask layer. 3.7# Conflict Φ resist IIQ, 4.5.5' ・ΦΦ closed opening 800. Deep opening, 8' * e * Shallow opening [1
, 9... Element isolation, 10... Partition wall, 11...
Φ·p-type base region, 12...n-type emitter region, 13-, --field insulating film. 14. Fighting emitter ゛tun Ji, 15...Base electrode, 16...Collector electrode, 1711...High concentration Figure 1 Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] （１）゛ｒ−導体層」二にエツチング用マスク層を形成
し、ｌＩＡエツチング用マスク層を開口し該半導体層を
露出し、 前記露出した半導体層に対して１１１１記開［１を介し
て不純物を導入し、該不純物が導入された半導体層をエ
ツチングする工程を含むことを特徴とする半導体装置の
製造方法。(1) Form an etching mask layer on the ``r-conductor layer'', open the IIA etching mask layer to expose the semiconductor layer, and open the exposed semiconductor layer through the 1111 opening [1]. 1. A method of manufacturing a semiconductor device, comprising the steps of introducing an impurity and etching the semiconductor layer into which the impurity has been introduced. （２）半導体層」二にマスク膜を形成し、該マスク１１
りを開目し該半導体層の深い開口の形成予定領域を宥出
し、＋ｉｉＪ記露出した半導体層に前記開口を介して不
純物を導入し、該半導体層の深い開口の形」表予定領域
と浅い開口との形成予定領域に対してエツチングをなす
工程を有する半導体装置の製造方法。(2) forming a mask film on the second semiconductor layer;
The region where the deep opening is to be formed in the semiconductor layer is cleared by opening the semiconductor layer, and impurities are introduced into the exposed semiconductor layer through the opening to form the deep opening in the semiconductor layer. A method for manufacturing a semiconductor device, comprising the step of etching a region where an opening is to be formed.
JP2902884A 1984-02-17 1984-02-17 Manufacture of semiconductor device Pending JPS60171730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2902884A JPS60171730A (en) 1984-02-17 1984-02-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2902884A JPS60171730A (en) 1984-02-17 1984-02-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60171730A true JPS60171730A (en) 1985-09-05

Family

ID=12264955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2902884A Pending JPS60171730A (en) 1984-02-17 1984-02-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60171730A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61258433A (en) * 1985-05-13 1986-11-15 Hitachi Ltd Etching process
JPS6358838A (en) * 1986-08-28 1988-03-14 Fujitsu Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61258433A (en) * 1985-05-13 1986-11-15 Hitachi Ltd Etching process
JPS6358838A (en) * 1986-08-28 1988-03-14 Fujitsu Ltd Manufacture of semiconductor device

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