JPS60170778U

JPS60170778U - Period measuring device

Info

Publication number: JPS60170778U
Application number: JP5948484U
Authority: JP
Inventors: 中山　芳信
Original assignee: 三菱電機株式会社
Priority date: 1984-04-23
Filing date: 1984-04-23
Publication date: 1985-11-12

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の周期測定器のブロック図、第２図は従来
の周期測定器の各部の信号及び動作説明図、第３図はこ
の考案の実施例を示すブロック図、第４図はこの考案の
各部の信号及び動作説明図である。図中、１は入力レベル調整回路、２はトリガ回路、３は
クロック発生回路、４はゲート回路、５及び６は計数回
路、７は表示回路、８は制御回路、９はメモリ回路、１
０は演算回路、Ａは入力レベル調整出力、Ｂはトリガ信
号、Ｃはクロック、Ｄ及びＥはゲーティング信号、Ｆは
計数回路５の動作タイミング、Ｇは計数回路６の動作タ
イミング、Ｈは表示回路７の動作タイミング、Ｊはメモ
リ回路９の計数値、Ｋはメモリ回路９のオーバーフロー
スティタス、ＴＭは測定区間である。なお、図中同一、あるいは相当部分には同一符号を付し
て示しである。Fig. 1 is a block diagram of a conventional period measuring instrument, Fig. 2 is an explanatory diagram of signals and operations of each part of the conventional period measuring instrument, Fig. 3 is a block diagram showing an embodiment of this invention, and Fig. 4 is a block diagram of the conventional period measuring instrument. FIG. 2 is an explanatory diagram of signals and operations of each part of the invention. In the figure, 1 is an input level adjustment circuit, 2 is a trigger circuit, 3 is a clock generation circuit, 4 is a gate circuit, 5 and 6 are counting circuits, 7 is a display circuit, 8 is a control circuit, 9 is a memory circuit, 1
0 is the arithmetic circuit, A is the input level adjustment output, B is the trigger signal, C is the clock, D and E are the gating signals, F is the operation timing of the counting circuit 5, G is the operation timing of the counting circuit 6, and H is the display. The operation timing of the circuit 7, J is the count value of the memory circuit 9, K is the overflow status of the memory circuit 9, and TM is the measurement interval. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims

[Scope of utility model registration request]

An input level adjustment circuit that sets the level of the input signal within an appropriate range; a trigger circuit that outputs a trigger signal when the output of the input level adjustment circuit matches a preset trigger level; a clock signal generation circuit that generates a clock signal to be used as a reference; a counting circuit that counts the clock signal; a memory circuit that stores the value of the counting circuit and overflow when the trigger signal is output; and the memory. A period measuring device comprising: an arithmetic circuit that calculates changes in values of the circuit; a display circuit that displays the calculated values of the arithmetic circuit; and a control circuit that performs initial settings and measurement settings for each circuit.