JPS601700A - Pseudo static memory circuit - Google Patents

Abstract

PURPOSE:To check a refresh action in a short time by applying two clocks having the same cycle and a prescribed relationship to a refresh control terminal and a row address strobe terminal in order to produce pulses of the same cycle. CONSTITUTION:Two clocks of cycle Tt having a combined signal waveform which is inhibited in a normal operation mode are impressed to a refresh control terminal (RFSH)' and a row address strobe terminal (RAS)' of a test timing circuit. When the clock (RFSH)' is changed to ''0'' from ''1'', an F/F1 is set. Then an F/F2 is set when the signal SE is set at ''1''. Then both F/F1 and F/F2 are reset to ''0'' when the internal refresh request signal RFQ appears. Thus a pulse phiT is obtained at an output terminal and used as a test signal for a test circuit of an internal refresh circuit.

Description

[Detailed description of the invention] The present invention relates to pseudo-static memory circuits.

A refresh circuit is built into the dynamic RAM to automatically refresh the internal memory as needed.
See 1↓) Similar to static RAM, pseudo-static memory, which can be used without external refresh, is becoming widely used.

To check that the internal refresh circuit of such pseudo-static memory is working properly,
Conventionally, a refresh operation is performed at high temperature or room temperature for a period longer than the hold time at which all memory cells fail (by loading 1 data into each memory cell and selling 6 pieces of data after the hold time has elapsed). is maintained and all internal refresh circuits are checked to ensure proper operation.

However, the hold time at which all memory cells fail at room temperature is very long (for example, 1 minute), and it is impractical to check the operation of the internal refresh circuit over a longer period of time than this hold time.

In addition, it is possible to shorten the test time by raising the temperature to a higher temperature because the hold time becomes shorter, but if the temperature is still raised, the BT processing (the semiconductor is exposed to a biased state at high temperature for a long period of time, resulting in poor reliability). (treatments that increase

On the other hand, in order to check the internal refresh cycle, it is necessary to provide a monitor terminal or observe the current waveform of an appropriate terminal, but in standardized memory ICs, the function of each input terminal is defined. Therefore, it is impossible to provide a terminal for monitoring the internal refresh cycle at just ν.Also, it is difficult to automate the measurement of the cycle by observing the current waveform, and manual measurement is time-consuming. It has the drawback of being too dark.

It is an object of the present invention to eliminate the above-mentioned conventional drawbacks, to make it possible to check the operation of the internal refresh circuit within a short time, and to measure the internal refresh cycle within a short time without attaching an external monitor terminal. The object of the present invention is to provide a pseudo-static memory circuit that enables.

The circuit of the present invention provides, in a pseudo-static memory,
The input of the first one-shot pulse generator is connected to the first input clock signal of the pseudo-static memory, and the output is connected to the first contact, and the input of the first inverter is connected to the first input clock signal of the pseudo-static memory. the drain of a first transistor having a first polarity to a second input clock signal of the pseudo-static memory, and the gate of the first transistor having a first polarity to a second input clock signal of the pseudo-static memory; A second transistor with a polarity of H<, 2 has a drain connected to the second manual clock signal, a gate connected to the second contact, and a source connected to the second contact. Third
and connect the input of the first flip-flop to the third stirring point. Further, the input of the second inverter is connected to the second input clock signal, the output is connected to the fourth contact, and a second one-shot signal is generated.
The input of the pulse generator is connected to the internal clock signal of the pseudo-static memory, and the output is connected to the fifth contact.The input of the inverter L and m3 is connected to the fifth contact, and the output is connected to the sixth contact. A third transistor having a first polarity has a drain connected to the fourth contact, a gate connected to the fifth contact, and a source connected to the seventh contact, and a third transistor having the second polarity connected to the fourth contact. The drain of the transistor is connected to the fourth contact, the gate is connected to the sixth contact, and the source is connected to the seventh contact, and a second flip transistor is connected.
The input of the flop is connected to the seventh contact. Further A
The first input of the ND circuit is connected to the third contact, the second input is connected to the seventh contact, and the output is used as a test signal for a test circuit of the internal refresh circuit.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a single misfire blade.

In this embodiment, a sense amplifier 1, a memory cell array 2, an I
lo circuit 3, takeout buffer 4, data in buffer 5, X address buffer 6, X decoder 7, Y address buffer 8, Y decoder 9, oscillator 10, timer 11, refresh timing circuit 12, internal refresh address counter 13 , l also include an AS timing circuit 14, a CAS timing circuit 15, a write timing circuit 16, and a test timing circuit 20.

Among the above circuits, the circuits other than the test timing circuit 20 are composed of circuits having substantially the same functions as those commonly used in ordinary pseudo-static and memory circuits.

Details A (11) of the test timing circuit 20 are shown in FIG.

This circuit 20 includes a first one-shot pulse generator O81 whose input is connected to an external control terminal FSH, whose output is connected to a first contact N1, and whose input is connected to a first contact N1. , the output is connected to the second contact N2, the drain is connected to the external row address strobe terminal As, the gate is connected to the first contact N1, and the source is connected to the third A first transistor Q1 having a first polarity is connected to the contact N3 of the transistor Q1, with its drain connected to the row address strobe terminal ILAS, its gate connected to the second contact N2, and its source connected to the third contact N3.
a second transistor Q2 with a second polarity connected to the third contact N3, a first flip 70 tube F/F1 connected to the third contact N3, and one transistor As for the row address strobe; A second inverter I2 has an output connected to a fourth contact N4, an input is connected to a sense amplifier enable signal SE which is an internal signal of this pseudo-static memory circuit, and an output is connected to a fifth contact -N5. a second one-shot pulse generator O82 which is connected to wh, a third inverter (3) whose input is connected to the fifth contact N5, whose output is connected to the sixth contact N6, and whose drain is connected to the fourth contact N4. A third transistor Q3 having the first polarity has its gate connected to the fifth contact N5, its source connected to the seventh contact N7, its drain connected to the fourth terminal point N4, and its gate connected to the fourth contact N4. A fourth transistor Q4 with a second polarity, whose source is connected to the sixth contact N6 and whose source is connected to the seventh contact N7, is connected to the seventh contact N7. 7 lip-flop F/F2, the third
An AND gate A whose one input is connected to the contact N3 of the test timing circuit 20, the other input is connected to the seventh contact N7, and whose output is connected to the output terminal φT of the test timing circuit 20.
1 The drain is connected to the contact N3, and the gate is connected to the timer 1.
1, a fifth transistor Q5 having a first polarity whose source is connected to the ground ( )ND, and a drain connected to the seventh contact N7. In this case, the gate is connected to the riff 1/Tsushi 1 song request signal kL F Q, and the source is connected to the ground GND.
A sixth transistor Q6 having a second polarity is connected to each of the transistors Q6.

Internal refresh and circuit operation checks in this embodiment are performed as follows.

The test timing circuit 20 shown in FIG. 2 has a refresh control terminal ILFS, which is an external terminal, as its input.
It includes a signal from I() and a signal from the row address strobe terminal As, which is also an external terminal, but these two external terminals are connected to the No. 48 waveform, which is a combination that is prohibited in the operation of The two clocks each having a period Illt will be referred to as terminals, and their specific gravitational waveforms will be described later).

As a result, the operation of the circuit 20, which will be described in detail later, causes a test signal pulse (hereinafter referred to as pulse φT and pjl, ibu) having a male φTK period Tt to be issued. In normal operation, it is prohibited to add such a combination of signals to the terminal P S 1-I and the terminal RAS, so the occurrence of this pulse φ↑ may disturb the normal operation. There isn't.

Now, this pulse φT is generated by the RAS timing circuit 14,
It is supplied to the CAS timing circuit 15 and the refresh timing circuit 12, and performs the following 101 dimming.

That is, when the pulse φT appears when the signal applied to the external j-input designation h-j terminal νVE is ink-in designation, the data applied to the data input terminal DIN is transferred to the data buffers 5 and 10. The data is controlled to be stored in the memory cell array 2 through the data storage 3. When the pulse φT appears, the RAS timing circuit 14, the CAS timing circuit 15, and the refresh timing circuit 12 add the contents of the internal refresh address counter 13 at that time to the 1X decoder 7 via the Specify the X address (row address) of the memory cell array 2 to be loaded, and at the same time, the address counter 130 and the Y decoder 9 via the Y address buffer 8 with the same contents, and the @YX address of the memory cell array 2 to be loaded. column address). Furthermore, the sense enable signal SE is generated and the sense amplifier [
and enable it to perform convolution on the specified address of the data. Next, the internal refresh address counter 13 is set 1) and controlled as shown in FIG.

Therefore, - CXi 4, da (- data to be input to terminal DIN
In addition, if the terminal VVlfl is specified to include il' and pulses φT are generated one after another, all addresses such as X address - X address in the memory cell array 2 will be filled with data one after the other. can.

Furthermore, if the terminal WE is designated for reading and the pulse φT is generated one after another, almost all the operations at the address where X address = Y address in the memory cell array 2 are performed in almost the same manner as described above. The data is output one after another through the data out buffer 4 to the data terminal D OUT.
can be read out.

Therefore, for example, first, a pulse φT is generated one after another with the terminal Dna "1" and the terminal WE designated as write, and all addresses in the memory cell array 2 that are X address - X address are written as "1". Write.

Next, by normal read operation, the X address -X is read from the outside.
Adding an address designation signal such as an address, the contents of all addresses in the memory cell array 2 where X address = Y address are read one after another, and ``1'''' is written to all of them. Check.

Next, set the terminal DIN to 0'', and set the terminal W to 1 again.
As the write designation, pulses φT are generated one after another, and the previously written 1'' of all addresses where X address=Y address in the memory cell array 2 is changed to tt On.

Next, by applying a normal read operation again, an address designation signal where X address = Y address is applied externally, and the contents of all addresses where X address = Y address in memory cell array 2 are read. Read them one after another and check that they have all been changed to '0'.

The above-mentioned writing to the memory cell array 2 using pulse φ7 was performed using various circuits for internal refreshing, and as a result of the above-mentioned check, no error was detected. If this does not occur, it is proof that the circuits required to perform internal refresh are operating normally.

Moreover, it has the advantage that it takes only a few milliseconds even in the case of a 64-bit memory.

Next, the internal refresh period can be checked as follows.

As described above, it is possible to easily check whether the seat is occupied by using the pulse φT, but as will be described later, these 24 pulses are connected to the refresh control terminal ItFSH of the test timing circuit 20 and the row address strobe terminal As.
If the period Tt of the above-mentioned external clock added to Since the resetting within the external clock is not performed correctly every cycle of the external clock, the convolution operation for the above-mentioned X address-Y address cannot be performed normally.

If the period Tt of the external clock is longer than the period 1r of the internal refresh, the above-mentioned 1-in operation is performed normally.

Therefore, by successively changing the period l1lt of the external clock and performing the above write/read test, the internal refresh period can be measured from the boundary value between the period in which the one write/read test fails and the period in which it succeeds.

Measuring the internal refresh period using this method is as follows:
It has the advantage that it can be easily automated, and even if the above-mentioned written bladder evacuation test is searched 20 times at different intervals, it can be completed in 100 to 2007J18eC.

Next, the operation of the test timing circuit 20 for generating the above-mentioned pulse φT will be explained with reference to FIGS. 2 and 3.

FIG. 3 is a timing chart for explaining the operation of the circuit 20.

The two external refresh control terminals RFSH and the draw address strobe terminal RAS, which are two external clocks, have a mutual relationship as shown in FIG.
Add S H and clock RAS, respectively. The time interval from the falling leading edge of clock RF8H to the falling leading edge of clock RAS is approximately 100 ns @ 1 degree. In normal use, the interval between the two is approximately 10 μs.
Therefore, in normal use, the following noise φT will not occur and cause a malfunction to a normal operation.

Now, in FIG. 2, clock 1(, Psi() is It
When the voltage changes from 11+ to II OII, a one-shot pulse is generated at the contact N1 by the one-shot pulse generator O81 (Nl in FIG. 3). This is in1<' -ta1
1 and generates a one-shot pulse at contact N2 as well.

While the one-shot pulse is output to the contacts Ni and N2, the transistors Ql and Q2 are turned on, and the clock RAS becomes '1'.
(At this point, the clock l (, As is P1) is taken into the contact N3 and the Noritsu flop F/F1 is set to 1.
(N3 in Figure 3).

Next, when the sense enable signal SE becomes 1" (1g signal SE is an internal signal generated approximately 50 ns later than the falling front of the clock RAS), the output pulse generator 082 connects to contact N5. A one-shot pulse is generated (N5 in FIG. 3).This is inverted by the inverter 3 and a one-shot pulse is also generated at the contact N6.

Contact N5. While the one-shot pulse is output to N6, transistor Q3. Q4 turns on, takes in the inverted signal of the clock RAS of 1" (at this point, the clock RAS is II O" and the inverted signal becomes 1") into the contact N7, and sets the flip-flop F/F 2 to 1". Set (3rd
Figure N7).

When the contact N3 and the contact N7 both become 1'', the output terminal φT of the AND gate A becomes II 17+ (φT in FIG. 3).

Next, when the internal refresh signal RFQ from the timer 11 appears, the flip-flop F/F1 and the Noritsu-flop F/F2 are reset to "0", and therefore the output terminal 4φT returns to "0", thus causing the above-mentioned pulse φT is generated.

As mentioned above, the external refresh control terminal 1LF8H
By adding two clocks RFSH and RAS, each having a period Tt and a mutual relationship as shown in FIG. be able to.

As is clear from the above explanation, with respect to the period Tr of the internal refresh request signal RFQ generated by the timer 11, if Tt is less than Tr, there is an interval in which no reset is performed within the period T. occurs, and a pulse φT with a normal period
will no longer be generated.

Utilizing this, the internal refresh period Trffi can be measured as described above.

Note that the flip-flops F/F1 and F/F2 used here are for preventing floating of the contacts N3 and N7, respectively, and the flip-flop circuit shown in FIG. 41 can be used.

In FIG. 4, transistors Q7 and Q9 have the same P-type polarity, and transistors Q8 and QIO have the opposite N-type polarity. The commonly connected drains of transistors Q7 and Q8 are connected to the commonly connected gates of transistors Q9 and QIO, and the commonly connected drains of transistors Q9 and QIO are connected to the commonly connected gates of transistors Q7 and Q8. This contact is connected to the gate connected to the input contact N3'! of this flip-flop circuit. or used as N7. For example, when this contact is used as contact N3 in FIG. 2, the operating current of transistors Q9 and QIO is selected to be about 1/10 of the operating current of transistors Ql, Q2, Q5, etc., as described above. Can be used to prevent floating.

Note that the configuration shown in FIG. 1 merely shows one embodiment of the present invention, and the present invention is not limited thereto in any way.

In addition, the operation check of the internal refresh circuit mentioned above is performed by φ
Although the write operation using ゛T is used, this is only an example; for example, the soft write operation using φT can also be performed using OU.

As described above, by using the present invention, it is possible to check the operation of the internal refresh circuit in a chamber C crystal within a short period of time (1), and a pseudo A static memory circuit can be provided.

This makes it possible to improve the reliability of the pseudo-static memory circuit and improve production efficiency.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a circuit diagram showing details of the test timing circuit used in this embodiment, and Fig. 3 is a block diagram showing the details of the test timing circuit used in this embodiment. The timing chart and FIG. 4 are circuit diagrams showing details of the flip-flop used in the timing circuit. In the figure, 1...Sense amplifier, 2...Memory cell array, 3...I10 circuit, 4...
Data out buffer, 5...Data inbound buffer, 6...X address buffer, 7...
...X decoder, 8...Y address buffer,
9...X decoder, 10...Oscillator, 11...Timer, 12...Refresh timing circuit, 13...Internal refresh address counter , 14...1LA8 timing circuit, 15...CA8 timing circuit,
16...Write timing circuit, 20...
...Test timing circuit, (JSI. 082...One-shot pulse generator, ll,
■2゜I3...Inverter, F/F11F/■
゛2...Flip 70 knobs, Q1~QIO...
...transistor, A...and gate.・-1). 1 - Attorney Patent Attorney, 1. ．． 1N5 Figure 2 695

Claims (1)

[Claims] (1) In the pseudo-static memory, the input of the first one-slot pulse generator is connected to the 10th input clock of the pseudo-static memory, and the output is connected to the first contact. The input of the inverter is connected to the first contact, the second input flock signal of the static memory is connected, the gate is connected to the first contact, and the source is connected to the third contact, and has a second polarity. A second transistor has a drain connected to the second input clock signal, a gate connected to the second contact, and a source connected to the third contact, and an input of the first clip-flop connected to the third input clock signal. Connect to the contacts. Further, the input of the second inverter is connected to the second input clock signal, the output is connected to the fourth contact, and the input of the second one-shot pulse generator is connected to the internal clock signal of the pseudo stubic memory. , the output of the third inverter is connected to the fifth contact, the input of the third inverter is connected to the fifth contact, the output is connected to the sixth contact, and the drain of the third transistor having the first polarity is connected to the third inverter. to the fourth contact, and the gate to the fifth contact.
Connect the source to the 70th contact point, respectively, and connect the source to the 70th contact point.
The drain of a fourth transistor having a polarity of
The gate is connected to the sixth contact, the source is connected to the seventh contact, and the input of the second 7-lip-flop is connected to the seventh contact. Further, the first input of the AND circuit is connected to the third contact, 8iI! A pseudo-static memory circuit, characterized in that 20 inputs are connected to the seventh contact, and the output is used as a test signal for a test circuit of an internal refresh circuit. The drain of a fifth transistor having a polarity is connected to the third contact, the gate is connected to a refresh request signal which is an output of a timer, and the source is connected to GND, and the drain of a sixth transistor having a first polarity is connected to the third contact. is connected to the seventh contact, the gate is connected to the refresher, the source is connected to GND, and the test circuit is connected to the timer.