JPS60168261A - Control system of merging computer system - Google Patents

Abstract

PURPOSE:To attain a control system of a merging computer system where plural different kinds of computer or operating system exist together and are operated in the constituting method of a computer system. CONSTITUTION:The computer system consists of a host computer HM20, a merging control program 31 which manages the computer HM20, one or more lower computers LM22, and operating systems 34 which manage individual computers LM22. The merging control program 31 operated by the computer HM20 is provided with a processing command interface 28 and selects and excites computers LM22 which should execute individual processings constituting a processing command string 29. The computer LM22 excited by the computer HM20 receives processing names to be executed and processed from the computer HM20 and executes application programs 26 for processing names.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention particularly relates to integrated computer system control that performs suitable control for continuously executing processes that operate independently on computers with different operating specifications on the same computer system. Regarding the method.

[Background of the invention]

Conventional computer systems have adopted the system configurations shown in FIGS. 1 to 4.

FIG. 1 generally shows S P (Single-P r
This is the most common method for configuring computer systems and is used in a wide range of applications from personal computers to large-scale computers. In the SP method, one computer 4 is operated by one operating system.
08) 203, in which the user specifies the program name of the application program (AP) 202 to be executed through the processing command sequence interface 205. The name of the program specified here is generally called a command or a command, and a processing command sequence or command sequence that combines each command is called a command procedure.

Figures 2 and 3 show MP (Multi-Process
This method is called the sor) method, and is a method of configuring one computer system using a plurality of computers in order to compensate for the lack of computer processing power in the SP method. Depending on the configuration, the MP system uses a tightly coupled multiprocessor (T
tightly coupled multi-proc
essor: TCMP) method and the loosely coupled multiprocessor (Loosely Coupled Mul
There are two types of ti-Processor: LCMP) methods.

In the TCMP method shown in FIG. 2, a group of computers 208 that share main memory are connected to one operating system.
It is managed by the system 209. Therefore, the application program (AP) 210 specified by the user in the processing command sequence 211 can be executed on any computer that constitutes the computer system without the user being aware of it.

In the LCMP method shown in Fig. 3, an inter-channel coupling device (Ch
(Annel To Channel Adapter)
A separate operating system (O8) 214 manages a plurality of computers connected by 212. Therefore, by installing an operating system (O8) 214 with different specifications on each computer 216,
Application programs (AP) 215 of different OS interfaces 213 can be executed within one computer system.

Figure 4 shows a virtual computer system (VirtualMac
This is a computer system configuration method called Hine System+i (VMS). A virtual computer system (VMS) is a real computer (base machine: B
a5e Machine) 217 as a per-channel machine monitor (Virtual Machine Mo
It is managed by a special control program called n1tor (VMM) 218, and allows multiple operating systems (O5) 220 to operate under one computer 217. By using the VMS method, a user can synchronously execute different application programs (AP) 221 of the OS interface 219 on one computer.

The four types of commonly used computer system configuration methods have been described above, but the above configuration methods have the following problems.

(1) SP method shown in Figure 1, T method shown in Figure 2
With the CMP method, application programs with different OS interfaces cannot be executed.

(2) By using the LCMP method shown in Fig. 3 and the VMS method shown in Fig. 4, it is possible to simultaneously execute application programs with different OS interfaces. is only an application with the same type of OS interface.
It is limited to the combination of processing instructions (commands) that start up the remote control program (AP).

(3) In the MP system shown in Figures 2 and 3 and the VMS system shown in Figure 4, the types of computers and operating systems (OS) that make up the computer system are limited to the same type or system. be done.

[Purpose of the invention]

The main purpose of the present invention is to provide a converged computer system control method that allows a plurality of different types of computers or different types of operating systems to coexist and operate in a computer system configuration method in order to solve the above problems. It's about doing.

Another object of the present invention is to combine instructions (commands) for starting application programs that run only under each operating system into one processing command sequence (commands) in a computer system in which multiple operating systems coexist.・Procedures)

[Summary of the invention]

In order to achieve the above object, the present invention provides computers with different operating specifications or operating systems with different operating specifications.
A computer system is configured by combining multiple systems, and a high-level computer that exclusively controls the operations of multiple computers, a fusion control program that operates under the high-level computer, and input/output requests for each computer It is characterized by being equipped with a processor selection control device that centrally manages the process, and registering application programs that run separately on computers with different specifications into one processing command sequence (command procedure) and causing them to be executed continuously. . That is, each information record constituting each command is provided with a processor identifier, and the fusion control program selects the corresponding low-level computer based on this processor identifier, and then instructs the operation of the low-level computer. As a result, application programs running on separate computers and operating systems become a collection of command information records, and can execute a single function.

Also, when a low-level computer finishes processing a certain command and requests the next command, the high-level computer recognizes this request, retrieves the information record that has already been prepared, and again uses the processor identifier to A control means is provided for sending the command and input/output operation completion report signal to the computer.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 5 is a conceptual diagram showing the configuration of a computer system to which the present invention is applied. The computer system is a high-level computer (Hyp
A fusion control program (Fusion Control, rol Program) that manages the ervisor Machine (HM) 20 and the high-level computer (HM) 20.
21, and at least one low-level computer (Lo
An operating system (OS) that manages the calMachine (LM) 22 and each low-level computer (LM) 22
) Consists of 23.

High-level computer (HM) 20 and multiple low-level computers (LM) 2
2 are connected by a communication line 24 for exchanging data. Application program
ion Program: AP) 26.

Low-level computer with compatible OS Tonturface 27 (
LM) 22. A fused control program (FCP) 31 that operates on a high-level computer (HM) 20 is equipped with a processing command sequence interface 28, and each process (command) that constitutes a processing command sequence (command procedure) 29.
The low-level computer (LM) 22 to be executed is selected and activated.

The low-level computer (LM) 22 started by the high-level computer (HM) 20 sends the name of the process to be executed to the high-level computer (HM) 20.
) 20 and executes the application program (AP) 26 corresponding to the process name. This is an example of the operation of the integrated computer system which is the basic concept of the present invention.

FIG. 6 is a diagram showing an example of a system configuration in which the integrated computer system of FIG. 5 is implemented using a microprocessor.

The processor 31 corresponds to the high-level computer (HM) 20 in FIG. 5, and the processor group 33 corresponds to the low-level computer (HM) in FIG.
LM) corresponds to 22. The processor 30 and the processor group 33 each include a memory (not shown), the processor 30 stores a fused control program (FCP) 31, and the processor group 33 stores various operating systems (O8n) 34. ing. Data exchange between processor 30 and processor group 33 is performed via system bus 3.
6, and various input/output devices such as a keyboard 37, a display 38 . File 39 is also system
Processor 30 and processor group 33 via bus 36
shared between

A fusion control program (FCP) running on the processor 30
) 31 is an interrupt control unit 347. Processing control unit 348, command table initialization unit 349, keyboard input unit 3
50. It has seven components: a file input section 351, a command/table management section 352, and a processor ID/command name output section 353.

35 is a processor selection control device that exclusively controls the operations of the plurality of processors IT\33. The processor selection control device i35 has a processor group 33 as an input signal line.
The input/output request signal line (IO, ~IO,) 45. Input signal line (RD, ~RD,) 46° mode signal line (MD, -M
D7) 47, weight signal line (WT, -WT7) 54 and processor selection signal line (P, T) 44 of processor 3°
, bus selection signal line (B, 5) 52 is connected. Further, as an output signal line of the processor selection control device 35,
Input/output completion signal line (CI-Ct) to processor group 33
48 is connected to the processor 30, and an input/output interrupt line (Ilo INT) 43 is connected to the system bus 36.
D) 50 and a mode signal line (MD) 51 are connected.

Next, the fusion control program (
An example of the processing method of FCP) 31 will be described.

FIG. 7 shows a processing command sequence (command procedure) 29. Reference numeral 55 denotes a command procedure file for storing processing command sequences, and is given a file name, for example, rFORTcGJ.

56 is a record of a processing command sequence. The record 56 stores a process name (command name) 62 and a processor identifier (PID) 60 indicating the processor that should execute the program specified by the process name.

For example, in the first record, the processor identifier (PID) 60 is "02" and the process name (command name) 6
2 is rEDITJ.

Command procedure file 55 in Figures 8 and 7
This is an example of a program corresponding to command name 62 stored in . Each is an executable load module file, and the file name is a command name (for example, rll
! DI Ding J, rFORT77J.

) is attached.

FIG. 9 shows each record 56 constituting the command procedure stored in the command procedure file 55.
The specification format is shown below. The head of the record begins with a processor identifier (PID) 60, followed by a delimiter 61, followed by a command name 62 and an operand string 63 for the command. The processor identifier (PID) may be set to 1, for example, 1 in order to select one of the processor groups 33 in FIG.
Specify one number from 7 to 7.

Note that the number of processor identifiers (PIDs) 60 is not particularly limited, and can be logically considered to be infinite.

Thereby, commands for starting application programs can be mixed in one processing command sequence (command procedure).

FIG. 1θ is a table related diagram of a portion related to the present invention among a group of tables managed by the fusion control program (FCP) 31. 64 is a command control table (OCT) that manages command tables, and 65 is a command table (CT) that stores command names. A command table (CT) 65 is created for each command name that constitutes the command procedure file 55 and is chained with a pointer 66. Only one command control table (OCT) 64 exists, and a start pointer (CCTFP) indicating the beginning of the command table (CT) 65 exists.
) 67, an end pointer (CCTLP) 68 indicating the end of the command table (CT) 65, and a command table (,
Current pointer (CCTCP) for CT) 65
I have 69.

FIG. 11 shows the structure of the command control table (OCT) 64. Three types of pointers (CCTFP 67.

CCTLP6B and CCTCP69) each have a 4-byte area length consisting of a segment number part 69 and an offset part 70.

FIG. 12 shows the structure of the command table (CT) 65, including a 1-byte processor ID area (CTPID).
71.1 byte data length area (CTTL) 72.4 byte pointer area (CTSEG and CTNP) 7
3, and a data area (CTDATA) 74 for storing command names and operand strings.

FIG. 13 is a flowchart showing the processing procedure of the fusion control program (FCP) 31. Fusion control program (
First, in step 75, the FCP) 31 enters a state in which there is an input/output request interrupt from the processor selection control device 35 (
The processor selection control device 35 in the wait state) performs integrated control in response to command input requests input via the input/output request line (10) 49 from the operating system (O8) 34 operating on all processor groups 33. An input/output interrupt is applied to the processor 30 running the program (FCP) 31 via the input/output interrupt line (Ilo INT) 43.

Fusion control program (FCP) 3 for input/output interrupts
1 is a command table (CT) 65 having a command sequence waiting to be transferred to the processor group 33 in step 76;
Check if exists. The specific checking method is
CCTCP 6 of Command Control Table (OCT) 64
When 9 is zero, it is determined that there is no command sequence waiting to be transferred. If there is no command sequence waiting to be transferred, in step 77 an input request is issued to the keyboard 37,
It waits for the user to input a command/procedure name from the keyboard 37. When the user inputs the command procedure name from the keyboard 37, the fusion control program (FCP
) 31 inputs a command string from the command procedure file 55 waiting for a command procedure name in step 78 and expands it into a command table (CT) 65. At this point, the Command Control Table (OCT)
64 current pointer (CCTCP) 69 is CT
It points to the beginning of the chain. Next, in step 79, the fusion control program (FCP) 31 sets the current pointer (
CCTCP) 69 points to the processor number in the command table (CT) as the processor identifier (PI
After outputting the data to the data bus 36 as D60), the processor selection control device 35 is activated. After that, the fusion control program (FCP) 31 executes the command name 6 existing in CTDATA 74 in the current CT in step 80.
2 and the operand string 63, one character at a time, is sequentially output to the data bus 36. At this time, the processor selection control device 35 sends an input/output completion signal line (C, to C7) 4 to the outputting processor every time one character is output.
8, outputs a signal indicating input/output operation completion report. The fusion control program (FCP) 31 is CTDA1'A 74
When all the character strings in the CT
After replacing the address with address 66, the process returns to step 75 and waits until the next command input request from the processor group 33. On the other hand, in step 76, if there is a command sequence waiting to be transferred, steps 77 and 78 are bypassed, and the commands in the current CT are transferred to the processor group 33.
Transfer to. The above is the processing procedure of the fusion control program.

Next, using FIGS. 14 and 15, the processor selection control device ii (Procegsor S el
Ection Control Unit: PSCU
) The structure and operation example of 35 will be explained. FIG. 14 is a control circuit diagram of the processor selection control unit (PSCU) 35. The processor selection control unit (PSCU) 35 can be roughly divided into an input completion signal generation section 82 (FIG. 14(a)) and an input/output request signal generation section 83 (FIG. 14(b)).

In FIG. 14(a), the input completion signal generation section 82
It is composed of a processor ID (PID) storage register 84, a decoder 85, a gate circuit 96, and AND circuits 87 and 88. The input signal line of the AND circuit 87 is connected to the processor 30 by a processor selection signal line (PT) 44, and is also connected to the bus selection signal line (BS) 52 of the processor 30.
is connected to. The system bus 36 and the output signal line of the AND circuit 87 are connected to the gate circuit 86 .

The input signal lines of the AND circuit 88 are a signal line 91 obtained by distributing the bus selection signal line (BS) 52 of the processor 30 inside the input completion signal generating section 82 and eight signal lines 106 decoded by the decoder 85. The output signal line of the AN, D circuit 88 is connected to the input/output completion signal line (C8 to C,) 48 in a one-to-l ratio to the processor group 33.

In FIG. 14(b), the input/output request signal generation section 83 is composed of three gate circuits 93, 94.95, three OR circuits 96, 97.98, and two AND circuits 99, 100. ing. The input/output request signal lines (IOI to IO?) 45 of the processor group 33 are connected to the OR circuit 96, and the input request signal lines (RD, to RD7) are connected to the OR circuit 97.
) 46 is connected, and the OR circuit 98 is connected to the mode signal line (M
D, to MD, ) 47 are connected. AND circuit 99
is the VA engineering T signal line (WT, ~WT) of the processor group 33.
, )54 are connected. OR circuit 96.97.98 and A
The output signal line of the ND circuit 99 becomes the input signal of the AND circuit 100, and the output signal line of the AND circuit 100 is connected to the input/output interrupt signal line (Ilo INT) 43 of the i-processor 30.The input signal line of the gate circuit 93 AND
The output signal line of the circuit 100, the output signal line of the OR circuit 96,
The output signal line of the AND circuit 99 is input, and the gate circuit 9
The output signal line 3 is connected to the system bus 36 as an input/output request line (10) 49. The input signal line of the gate circuit 94 includes the output signal line of the OR circuit 97 and the AND circuit 10.
The output signal line of the gate circuit 94 is connected to the system bus 36 as an input request signal line (RD) 50.

Further, the input signal line of the gate circuit 95 is connected to the OR circuit 11!
98 output signal line, AND circuit 100 output signal line.

The output signal line of the AND circuit 99 is connected, and the gate circuit 9
The output signal line 5 is connected to the system bus 36 as a mode signal all (MD) 51.

Next, an example of the operation of the circuit shown in FIG. 14 will be shown.

First, an example of the operation of the input/output request signal generating section 83 will be explained.

In the system configuration example of the integrated computer system shown in FIG.
(os, ~O8,) 34 operates, and all processors 33 wait for command input from the keyboard 37.

In this state, the input/output request signal line (10) 45, input signal line (RD) 46, mode signal line (MD) 47, and wait signal line (WT) 54 are all in the logic 1'1'' state. Therefore, the output signals of the OR circuit 96, 97, 98 (7) of the input/output request signal generating section 83 and the output signal of the AND circuit 99 are all logic "'1". As a result, the output signal of the AND circuit 100 It also becomes 1.

An input/output interrupt signal is generated to processor 30.

On the other hand, a gate circuit 93 connected to the system bus 36,
Since the output signal of the AND circuit 100 is in the "1" state, the output signal of 94.95 is inverted and becomes the "0" state, and the gate circuits 93, 94.95 are closed and the output signal is "0". It remains at 0".

By the above operations, the keyboard 3 of the processor group 33
7 is guarded, and the fusion control program switches to an activation request for the processor 30 in the wait state. On the other hand, the input/output request signal line (10) 45, input signal line (RD) 46, mode signal line (MD) 47, and wait signal line (WT) 54 are all in a state other than "1", that is, input other than command input output request, or
When any one of the processors in the processor group 33 is executing processing, the output signal to the processor 30 is always 0'', the gate circuit 93°94.95 is open, and the input to the processor group 33 is Output request line (10)
49, input request signal line (RD) 50, mode signal line (M
D) 51 onto the system bus 36.

Next, an example of the operation of the input completion signal generating section 82 will be explained. In response to a command input request from the processor group 33, the processor 30 first places a processor ID (PiD) 60 indicating the processor that should execute the command on the system bus 36, and connects it to the processor selection signal lines (P, T) 44 and path selection. Each signal is issued to the signal line (B, 5) 52. The input/output completion signal generation section 82 connects the processor selection signal lines (P, T) 44
When the bus selection signal line (B, 5) 52 becomes l'', the gate circuit 86 opens and the processor ID on the path 36 is opened.
(PAD) 60 is stored in the PID register 84. Thereafter, the contents of the PID register 84 are decoded by a decode 85 and the processor ID is entered in an AND circuit 88.
Input completion signal (C1 to C,
) 48 becomes "1". for example,
Assuming that the processor ID (PID) 60 is "01", C3 becomes "1" state and O3 of the processor group 33
The command input request for ゜ is completed.

FIG. 15 is a timing chart showing the above operation example. Data 111 on data bus 36 has period T107
Switch with . The contents 108 of the PID register 84 are
Switching occurs when the signal 112 and PT signal 113 are issued. The decode signal 109 is ``'1'' when the processor ID (PID) 60 is stored in the PID register 84.
” state. Completion signal 11 for command input request
0 is generated in synchronization with the B and S signals 112 each time the command name is output one character at a time on the data 11''1 of the data bus 36.

As explained above, there are calculators with different specifications.

Alternatively, one computer system can be configured by combining multiple operating systems with different specifications.

〔Effect of the invention〕

According to the present invention, computers or computers with different specifications.

Since a computer system can be constructed by combining operating systems with different specifications, multiple application programs running on different types of computers do not need to be unified to the specifications of one computer.

Moreover, it has the advantage that it can be used by incorporating it into one processing command sequence.

[Brief explanation of the drawing]

Figure 1 is a conceptual diagram of the conventional SP method, Figure 2 is the conventional TC
A conceptual diagram of the MP system, Figure 3 is a conceptual diagram of the conventional LCMP system, Figure 4 is a conceptual diagram of the conventional VMS system, and Figure 5 is a conceptual diagram of a computer system using the fused control system of the present invention. FIG. 6 is a system configuration diagram showing an example of an integrated control computer system, FIG. 7 is a diagram showing an example of a command procedure stored in a command procedure file, and FIG. 8 is a diagram showing a load procedure corresponding to FIG. FIG. 9 is a diagram showing the format of a processing sequence record; FIG. 10 is a diagram showing the relationship between the command control table and the command table;
Figure 11 is a diagram showing the structure of the cloak control table.
Figure 2 is a diagram showing the structure of the command table, Figure 13 is a flowchart showing the processing procedure of the fusion control program,
FIG. 14 is a circuit diagram of the processor selection control device, and FIG. 15 is a timing diagram showing an example of the operation of the processor selection control device.
It is a chart. 20... High level computer (HM), 21... Fusion control program (FCP), 22... Low level computer (LM)
, 23...Operating system (O8), 2
4...Communication line, 25...OS interface, 2
6...Application program (AP). 2F... Processing command string interface, 29... Processing command string, 35... Processor selection control device, 43.
... Input/output interrupt line (Ilo INT), 44... Processor selection signal line (PT), 45... Input/output request signal line (10), 46... Input signal line (RD), 47...
...Mode signal line (MD), 52...Bus selection signal line (BS), 54...Wait signal line (WT), 60 lines 1 Figure fJ 2 Figure? i3Fig. 212 14 Fig. 5 Fig. 6 n Ne\J7Fig. 0 Invention Author Tsutomu Ito 1-28 Higashi Koigakubo, Kokubunji City Hitachi, Ltd. Central Research Laboratory

Claims (1)

[Claims] 1. A first computer that selects a computer that executes the process specified in the record that makes up the processing command sequence, a plurality of second computers that execute the specified process, and a bus that connects these computers. In the computer system configured, means for selecting one of the second computers that is not running, which corresponds to the second computer identifier held on the record, and the selected second computer. 1. A converged computer system control system comprising: means for transmitting the record to the selected second computer; and means for importing the transmitted record into the selected second computer.