JPS60164849A - Program debugging system - Google Patents

Abstract

PURPOSE:To debug programs by providing an interrupt generating means which interrupts a processor and preparing a debugging program in the processor. CONSTITUTION:A stop command is sritten from a host computer into a start/ stop register 15 in an interrupt controller 8 through a communication controller 2. Then, a microprocessor 6 is stopped through an OR gate 13 by interrupt, and the address of an instruction step to be traced in set to a memory 7, and the address of an instruction to be executed is set to a register 11. Thereafter, when a start interrupt is transmitted to the processor 6, an address is put on a bus 10 for the purpose of fetching an instruction into the memory 7 after execution of one instruction, and coincidence between this address and the address in the register 11 is detected by a comparator 12 and is sent as an interrupt signal to the processor 6 through an AND gate 14 and the OR gate 13, and the processor 6 is stopped to trace every one instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] Mizumoto Meisha, relates to a program debugging method for a processor memory in a microprocessor application device (controller) that communicates with a host computer via a communication control device.

In recent years, as microprocessors and their peripheral devices have become more sophisticated and their prices have fallen, microprocessors and their software are incorporated into various devices as simple components (called firmware or software that replaces hardware) and are used as controllers. This is becoming more and more common. When using this method, unlike the conventional 1 = collector table and 4 cases, the microprocessor does not usually have a console device, so it is necessary to debug programs using the console device. is the finished table.

In addition, recent control technology is dominated by distributed control.
In many cases, a control device (controller) is connected to a host computer by a transmission line called a four-calway or a dataway. In this field, communication control devices (
It is common to use subprocessors.

The present invention relates to a program depacking method for a processor memory in a controller or the like that communicates with a host computer via a communication control device.

[Prior art and its problems]

FIG. 1 is a block diagram showing an example of a distributed control system to which the present invention is applied. In the figure, 1 is a host computer, 2 is a communication control device, 6 is a controller, and 4
is a controlled process, 5 is a transmission line, D is a display, and K is a keyboard.

The communication control device 2 uses a relatively low-function microprocessor (subprocessor), and the controller 6 uses a high-performance microprocessor.

In this example, an example in which a microprocessor is used in the communication control device 2 is explained, but it goes without saying that there is no need to use a processor as long as the device satisfies the communication functions described below. Furthermore, in the case where the communication function is separated from the communication control device 2, since the device 2 only repeatedly performs extremely simple control, it is easy to create the software even if a processor is used.

Now, in FIG. 1, each controller 3 includes, first, a host computer 1, a communication control device 2, a transmission line 5,
Data and programs for control are initially stored via the communication control device 2 and the like, and later, the controller 6 starts operating in response to a start instruction from the host computer 1. Data obtained as a result of the controller 3 controlling the target process 4 is also sent from the controller 3 to the host computer 1 via the communication control device 2 .

Now, conventionally, programmatic debugging during firmware or software development using this type of control is as follows:
This has been accomplished either by using external debugging tools developed specifically for the controller's microprocessor, or by using a microprocessor simulator implemented by software on the host computer. For this reason, development of these tools has conventionally taken a lot of time and money.

Furthermore, in order to debug the memory that stores the 'fq program to be debugged using an external debugger (debug tool), remove the microprocessor chip from the card that makes up the processor, and then install the debugger. Therefore, the controller as a product had to be provided with a socket for mounting the debugger, which caused problems in terms of reliability and price due to the nature of the socket.

Furthermore, in the case of simulation using software on a host computer, procedures for the hardware part, preparation of setting data, etc. are required, which inevitably makes debugging extremely inefficient. Ta.

A common problem with lag tools is that a tool or table must be created for each microprocessor to be debugged, resulting in inefficiency and high cost.

[Purpose of the invention]

The present invention has been made in order to eliminate the drawbacks and problems of the prior art as described above, and an object of the present invention is to eliminate the need for a special tool and to provide a socket for mounting a debugger. It is an object of the present invention to provide a program depacking method for a processor that does not require any additional processing and can be implemented efficiently and at low cost. [Summary of the Invention] □ The main point of the present invention is that in a program debugging method for a processor memory in a microprocessor application device that communicates with a host computer via a communication control device, the communication control device is discarded and the original host computer is Interrupt generation means is provided for interrupting the processor in response to a command from the processor, and the interrupt generates an operation for moving the contents of the processor to the memory to be stored therein or returning the contents of the memory to the processor. After preparing a debugging program to be realized in the processor and writing the control program to be debugged from the host computer to the processor memory via the communication control device, the processor is started by generating an interrupt by the interrupt generating means. , the debugging program is executed, and the program is debugged by reading the memory from the host computer via the communication control device.

[Embodiments of the invention]

The present invention will now be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an example of the internal configuration within the controller 3 necessary for implementing the present invention. In the same figure, the first
Components that are the same as those in the figure are designated by the same reference numerals. In addition, numeral 6 is a microprocessor, 7 is a memory for storing the Goodaram to be debugged, 8 is an interrupt controller capable of issuing an interrupt to the processor 6, 9 is a process interface, and 10 is a bus.

The communication control device 2 is capable of reading/writing the microprocessor 60 and the memory 7 upon receiving instructions from the host computer, and is also capable of reading/writing the microprocessor 60 and the memory 7.
It is possible to issue an interrupt to the microprocessor 6 and reset the microprocessor 6 via the communication control device.In other words, it is necessary for the communication control device to have such a communication function.

The basic functions necessary and sufficient for debugging the processor program stored in the memory 7 are as follows.

(1) It is possible to read/write the contents of the memory 7, (2) It is possible to save the contents of the memory 7 to an external medium or vice versa, and (3) it is possible to start/write the contents of the microprocessor B. stop/
(4) It is possible to read/change the contents of the microprocessor 6 (memory contents in the internal four registers); (5) There is a trace function for instruction steps executed by the microprocessor 6. , (6) Event trigger function (a function that allows interrupts to be sent from the outside to the microprocessor 6 if necessary) In other words, any device that can realize the functions (1) to (6) above can be used as a debugger. It can be said that this is usually sufficient.

Therefore, the present invention realizes each of the above functions by commands from a host computer without adding a special external device as a debugger. The explanation will be given below. - (1) Reading/writing the memory 7 This can be achieved by issuing a command from the host computer 1 to the communication control device 2 and having the communication control device 2 execute the command. As mentioned above, this is one of the basic functions that the line communication control device 2 should have. - (2) Transfer/save the contents of the memory 7 to an external medium using the function (1) above to transfer the contents of the memory 7 to the memory of the host computer key via the communication control device 2. The data is read and saved on an external medium such as a disk or MT (magnetic tape). Conversely, this can be realized by loading external data into the memory of the host computer-F and then writing it into the memory 7 via the communication control device 2.

(3) Start/stop/start microprocessor 6
Reset This is done by preparing a register in the interrupt controller 8 shown in Figure 2, and by having the communication control device 2 write special data into the register according to a command from the host computer, and then transmitting the data to the microprocessor via the controller 8. 6, an interrupt occurs.

This type of interrupt can be implemented very easily by using the non-maskable interrupt terminal of the processor 6, and the microprocessor 6 only needs to perform start and stop processing upon receiving this interrupt. This function is also generally provided in this type of device. A reset function can also be realized in the same way.

(4) Register/change the contents (internal register) of the microprocessor 6 This function is explained in (3) above. Upon receiving the signal, microprocessor 6 saves all its register contents in memory 7. This is also possible because the microprocessor 6 has an extremely simple program that restores the contents of the memory 7 to its own registers when receiving the start signal.

After issuing a stop command to the communication control device 2, the host computer 1 confirms that the microprocessor 6 has stopped.
This can be accomplished by reading the contents of the microprocessor 6 saved in the memory 7 via the communication control device 2, or by staying up late. Therefore, the program specially prepared for the processor 6Fc in order to implement the present invention is only the above-mentioned simple program, which is extremely simple and poses no problem.

(5) Trace function of mycoup processor instruction step This can be realized, for example, by configuring the interrupt controller 8 shown in FIG. 2 as shown in FIG.

This will be explained below with reference to FIG. In the figure, 8 is an interrupt controller, 10 is a bus, 11 is a register, 12 is a comparator, 13 is an OR gate, 14 is an AND gate, 15 is a start/stop register, Tl is an event trigger input terminal, and T2 is a condition signal. It is an input terminal.

In FIG. 3, start/stop information is transmitted from the host computer 1 via the communication control device 2 to the interrupt controller 8.
A stop command is written in the register (hereinafter referred to as SS register) 15, which interrupts the microprocessor 6 via the OR gate 13 to stop the microprocessor 6, and stores the address of the instruction step to be traced in the memory. PC in 7 (program counter)
, and then set the address of the next instruction (trace instruction) in the register 11. Then, the communication control device 2, the SS register 15 in the interrupt controller 8, and the OR gate are sent to the microphone processor 6. If a start interrupt is sent via 13, the microprocessor 6 will
After executing one instruction, the processor 6 sends the address and register 11 to the memory 7 via the bus 10 for fetching the instruction.
A match with the address set in is detected in the comparator 12, and the match output is sent to the microprocessor 6 as an interrupt signal from the OR gate 13 via the AND gate 14, which is open at that time. 6 stops.

Next, the host computer 1 saves the P stored in the memory 7 again.
The contents of C (pointing to the next instruction, 11) are transferred to register 11.
By setting this, tracing for each instruction becomes possible.

(6) Event trigger function This function outputs a signal that generates a state change from another hardware (not shown) and interrupts the microprocessor 6 from the 4 event trigger input terminals 4 and 7. When the microprocessor 6
This can be easily achieved by receiving the signal via the R gate 13 and performing the stop processing.

That is, as explained in detail above, extremely simple hardware is added and an extremely simple program (for start/stop processing) is installed in the microprocessor 6.
All debugging of the program for processors can be done just by preparing the program.

In such an example, the host computer 1 uses high-speed i/
Normally, the I10 devices are prepared from the beginning, and utilities for using these I10 devices are also prepared.

Programs for debugging can be created using host computing, and output to the 110 device in a format that is easy for the operator to understand can be done by simply converting data into code, and using a high-level language (for example, ForTry, etc.).
It's extremely easy because you can process it with .

By using a transmission line, the transmission time between the computer and the target (the message to be debugged) will be 14-14mm, but this is normally only a few tens of meters at most, so it is sufficient for the operator to You won't feel any waiting time. Also, recently, TSS (time sharing system) as shown in Fig. 4 has been increasingly used in microprocessor software development, but the debugging method according to the present invention basically requires only data exchange. The configuration is convenient for applying TSS because one host computer can be used in common.

In the table and FIG. 4, the controller 3 includes a target (memory that stores a program to be debugged), and the reference numeral 20 indicates a time sharing system (TS).
S) Indicates the terminal.

〔Effect of the invention〕

According to the present invention, it is possible to debug a microprocessor program by preparing an extremely simple circuit and a small number of programs, and there is an advantage that it does not depend on the type of the target processor program.

With conventional technology that uses dedicated debugging, debugging is not possible unless the processor is removed, or
There has been a problem that a debugger cannot be used because the processor is installed on-site and cannot be removed, but the present invention solves this problem.

According to the present invention, the host computer has abundant i/.

It is also excellent from the point of view of ease of use, as it can be used as is. Furthermore, in cases where cross-development of software (assembling, (compilation), loader) can be performed on the host computer, symbolic debugging of the program in the microprocessor becomes possible using symbols on the source list. Furthermore, if the TSS function is used, multiple operators can perform multiple debugging operations using one computer, making it even more economical.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a distributed control system to which the present invention is applied, FIG. 4 is a block diagram showing details of the interrupt controller 8 in FIG. 2, and FIG. 4 is a block diagram showing a time sharing system (TSS) suitable for application of the present invention. Code explanation 1...Host computer, 2...Communication control device,
3... Controller, 4... Control 1 object 7't-cess, 5... Transmission line, 6... Microphone I:l 7' Processor, 7... ...Memory, 8. Hit/interrupt controller, 9. Song/pro kx interface, 10... Pass, 11. Song/register, 12. Song/comparator, 13...-OR gate,
14... Song AND gate, 15. 4. Start/stop register, 20... TSS terminal representative Mizuhito Patent attorney Akio Namiki Patent attorney Kiyoshi Matsuzaki Figure 4

Claims (1)

[Scope of Claims] 1) In a program debugging method for a processor memory in a processor application device that communicates with a host computer via a communication control device, according to a command from the host computer via the communication control device. A debugging program is provided that provides an interrupt generating means for interrupting the processor, and also realizes an operation tube for moving the contents of the processor to the memory and storing it in response to the interrupt, and returning the contents of the memory to the processor. After preparing a four-gram program in a processor and writing a control program to be debugged from a host computer to the processor memory via a communication control device, an interrupt is generated by the interrupt generating means to start the processor; 1. A program debugging method characterized in that: 1- debugging a program is performed by stopping the debugging program, executing the debugging program, and reading the memory from a host computer via a communication control device;