JPS601677A - Eror detecting method - Google Patents

Abstract

PURPOSE:To detect assuredly an error of a data word by considering all words as errors only in case no correct data word consists in a data block containing data words which are simultaneously detected as erroneous by error detection codes of plural different series. CONSTITUTION:A data block formed with a prescribed number of words D1, D2-, error check bit codes P and Q of P and Q series different from the blocks of said data words, a cyclic redundancy check code C of the same series as said data words, etc. Then flags F1-F4 for codes P and Q of words which are simultaneously decided erroneous by the code P and Q are all set at ''1''. Other words of this block are also processed in the same way. If >=1 correct words are not included with a flag of ''0'' in the words D1, F2-, the words D1, D2- of the block are all considered as errors. It is prevented that all words including correct ones are regarded as errors. In such a way, a word error can be detected assuredly.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is used in so-called digital recording internal generation devices.
This invention relates to a preferred error detection method.

BACKGROUND TECHNOLOGY AND PROBLEMS For example, it has been proposed to digitally record and reproduce audio signals by AD converting them. In this case, error correction is performed by so-called cross interleaving. A data word is formed at the node, and a predetermined number of successive data words are used as a data block, for example, CR according to a series within this data block.
A C check code is provided, and a parity check code, for example, is provided in consecutive data blocks in a sequence different from that in the data block.

For example, in FIG. 1, the data data to be transmitted (transmitted) in the B record 111 is provided with an address data after the synchronization data S, followed by 16-bit data words D1 and D, respectively.
2, D3, and D4 are provided, and each is provided with a 16-bit variation code P1QS-CRC check code C to form a "ζl data block. This data block is transmitted sequentially. Here, the CRC check code Code errors are formed for data words D1 to D4 and parity check codes P and Q in the same data block. Parity check codes P and Q are also generated when data blocks are arranged sequentially as shown in FIG. , for example, is formed for the series shown by solid lines and broken lines.In this case, parity check code Q is formed for data that also includes code P, so parity check code P is formed first, and then parity check code Q is formed. is formed,
A CRC check code C is then formed.

By jo in this way, the inner 74E, (f, [t
lt+]), in a sequence of any parity check code P or Q, if the error detected by the CRC check code among the data words included in the sequence is one word, then the parity check code P or Correction can be performed using Q, and the correction ability can be improved by repeating error correction using two sequences invariably.

However, in such an apparatus, for example, when a recording medium that has been used once is reused for recording, the data signal from before ζ may be reproduced due to unerased data. In this case, the data signal due to the erased portion is correct in that part, so the CRC check code cannot detect an error.

Further, depending on the content of the error, detection using the CRC check code may not be performed with probability.

Therefore, if such an erroneous data signal is overlooked and reproduced, an abnormal sound will be generated in the reproduced signal and the sound quality will be extremely degraded.

Alternatively, in the sequence of parity check codes P or Q described above, if an error data word detected by the CRC check code and an error data word not detected are present at the same time, the detected error data word is erroneously corrected. is carried out, and this affects the next series, resulting in wide erroneous corrections.
Put away 4. 'There is that.

OBJECTS OF THE INVENTION The present invention takes this into account and ensures that erroneous data words are detected.

SUMMARY OF THE INVENTION The present invention forms a data lead at a predetermined bit of a digital signal, uses a predetermined number of successive data words as a data block, and is provided with an error check code according to the sequence within the data block. - In demodulating the data signal ζ in which a plurality of other error check codes with a plurality of sequences different from the sequences in the data block are provided for the series of data blocks described above, a plurality of errors in the above distribution are detected. At least two of the other data words included in the data block containing the data word simultaneously detected as erroneous by all of the check codes are detected by the other plurality of error check codes. This is an error detection method in which all of the data words contained in the data block are considered to be errors when there is no data word. Can be detected reliably.

Embodiment In FIG. 3, a flag F (1 bit) for an error pointer is provided in each word L of the random access memory into which 71 of the ζ and data 1]-words are written together with data of 16 h-nodes. Here, the overall configuration of the random access memory is the same as that shown in Fig. 2.It is further extended left and right, and a number of "addresses" corresponding to the data blocks related to - times of error correction are provided. It is something that

For such a random access memory, first set the flag F to all "ζ"1.

Next, write the data signals D1 to IJ4 of the data block that has been printed 11J1 and check codes P and Q to the address corresponding to the address signal to confirm that there is no CRC check code error. Flag F of each word is “
Set it to 0''.

Furthermore, a check is performed using the parity check code P series,
At this time, if there is no data word whose flag F is '1' and the parity check determines that it is an error, the flag F of all data words included in that series is set to '1'. Do this for blocks.

Furthermore, a check is performed using the parity check code Q series,
Similarly to the above, there is no data word with flag F "l",
If the parity check is determined to be an error, the flag F of all data words F included in that series is set to "1".
``.With this, in cases other than ``-statement, the flag F
Error correction is performed when the data word with "l" is l +Ril. This is done for all data blocks.

Thereafter, as in the past, errors d1 are corrected by the series of parity check codes P and Q alternately to increase the correction 11 ability +l]i
Melt.

Error detection and correction is performed in this way.

According to this method, the above-mentioned error caused by missing the CRC check code is prevented, and there is also no possibility that the influence of the error will spread due to erroneous correction.

In other words, in FIG. 4, for example, if a CRC check code error is not detected and only the central data block a is in error, if a check is performed using the parity check code P series, the data surrounded by the solid line will be The word is determined to be in error, and the flag F is set to 1''.A check is then made with a series of parity check codes Q, and at this time the data source L
Since the data word "D1 to D4, P" of J Tsuk a is ]-, the flag is set to "l", so the series containing this data word is checked]. The data word marked with "E" that is not surrounded by a line is determined to be an error, and the correction is omitted from now on. This is an error that would be detected if a series check was performed first.

However, if the above method determines an error in the parity check, tEl , even data words that are incorrect are considered to be errors, resulting in an extremely large number of incorrect data words. In this case, in particular, the barity check sequence -1/-P is often matched with the ΔD/DA input/output sequence before cross-interleaving, so this directly affects the sound quality and causes error data in this sequence. If there are many words, the sound quality will deteriorate significantly.

Furthermore, if all data words in the parity check code (Fl) or Q sequence are found to be errors, it is extremely difficult to correct them in the other sequence, and the sound quality deteriorates due to a lot of interpolation. There will be more risks.

Therefore, in Figure 94%5, each word of the random access memory into which a data word is written is filled with 16 bits of data and a 4-bit flag F□ for an error pointer.
, F2, F3, and F4 are provided.

The flags Fl and F2 are for the parity check code P series, and the flags F3 and F4 are for the Q series, and they are set as (0, 0) for those whose parity check results are not error.
, if there is an error due to the CRC check code of one data word or more and the parity check is impossible, (0,1),
For those determined to be incorrect by parity check (l, 0)
, a flag of (1, ■) is formed for those determined to be errors by the CRC check code 111i.

In accordance with this, the judgment w1 using the parity check code P and Q sequences is performed for all data blocks.

That is, all flags F1 to F4 of the random access memory are set to "1".

Next, data borrowing I) t~D4, parity check code I), and Q of the data block judged to have no CRC check code error are inserted into the address corresponding to the address signal c'j, W'. Flag F1 for each word inserted
~ Set F4 to (0, ■, 0, ■).

Furthermore, a check is performed using the parity check code P series,
If there is no data word determined to be a CRC check code error in the series and no error is detected by the parity check, the flags Fl and F2 of all data words in the series are set to (0, 0) and the error is detected. is detected, the flag F+-F2 is set to (l, 0) and the CRC check code C
'l'l 1lji is an error and the data word is 1.
If there are two, leave them as they are. This is done for all data blocks.

Further, in the series of parity check codes Q, a check similar to that described above is performed, and flags F3 and F4 are written and recalled as necessary. This is done for all data blocks.

In this result, flags F1 to F are (Fl,
F), F3, F4) - (1,0,110)...
(1) -(1,0,0,■)...(2) -(0,■,1.0)...(3) The data word F is judged to be incorrect in both series. If r + J Notake of a Wu is (tsume'(t'u), there is a possibility of an error if one is Wu and the other is untestable, so these data words are treated as errors. .

On the other hand, since data other than the series is not considered to be an error in one series, the other series determines that other data words in the series are in error, and converts them into error-free data words. −.

In other words, in Fig. 6, there is an error in ζ and CRC check code C.
"The part of (C) that was cut off, the above formula txt, (2),
(3) was judged to be incorrect (11, (2), (3)
The part ζ is determined to be an error, and in the above example, the part (0) that was determined to be an error is reduced.

In addition, in FIG. 7, under the same conditions as in FIG. 4 above, only the erroneous data block a surrounded by a solid line and the portion Q that is not judged by the parity check code P sequence are considered to be errors, and the correct data word Therefore, the number of parts that are judged to be incorrect will be reduced.

Therefore, the possibility of deterioration of sound quality is reduced.

Furthermore, in FIG. 8, if there are error data blocks b and c that are determined by CRC check code C along with error data block a, the states of flags F1 to F4 of each data word will be as shown in the figure. It becomes like this. Here, the result of the parity check code P series is written on the upper side, and the result of the Q series is written on the -1 side with a code. Of the codes, E is (10), U is (O21), C is (1, ,1
．． 1), Mujiro throws (Olo). In this case, the data nodes determined to be errors are all contained in data blocks b and c that are not detected by the CRC check code C surrounded by solid lines, and data nodes IJi and P of data block a.

Also, the 9th item 1 has no error due to the CRC check code C,
In the case where two data blocks a1 and a2 are consecutive and have a 'C error', the data word that is determined to be an error in this case is
is the part surrounded by a solid line.

Further, FIG. 10 shows a case where there is an erroneous data block b due to the CRC check code C in the vicinity of the erroneous data block a, and the data word determined to be erroneous in this case is surrounded by a solid line.

However, in this method, the parity check code P
, Q, if there is one or more data words that are erroneous due to the CRC check code C, it becomes impossible to detect that data word. Data words I) 2 to D4, Q within a
detection becomes impossible, and errors may be overlooked.

Also, as mentioned above, the sequence of parity check code P has Q
In the case of non-feedback cross-interleaving that does not contain a sequence of
If the data word is missed, it becomes impossible to check, and the missed data word may lead to erroneous corrections, which may lead to further erroneous corrections.

By the way, as mentioned above, for a data block which is not detected by the CRC check code C and which is erroneous, there is an extremely high probability that all C of the data block are erroneous.

Therefore, after the above-mentioned detection is performed, the flags F1 to F4 are set to (1, ■, 1, ■) by using all the data words of the data block containing at least one erroneous data word as entertainment. All data words surrounded by broken lines in FIGS. 7 to 1.theta. are treated as errors.

This makes it possible to extremely reduce the chance of missing an erroneous data word.

However, in this case, if the number of data blocks determined to be erroneous by the CRC check code C is large, the invalid data words are determined to be erroneous by the parity check11j.
There is a risk that the data word may be unnecessarily erroneous. Furthermore, if an erroneous data block that is not detected by the CRC check code C exists in close proximity, a correct data word will be determined to be erroneous by both parity codes P and Q, and this will cause the data word' The entire data block containing the data may be erroneous.

Therefore, in the above-mentioned detection, the data hood that is determined to be insufficient, that is, (4), (5),
The portion indicated by (6) is detected, and only when there is no correct data word at least in the data block, all the data words included in the data block are printed every 6 times.

For example, if there is even one correct data word F, all data words of that data block are considered correct. As a result, ζ, in Figures 7 to 10,
Each of the data blocks except for data blocks a1b, C, a1, and a2 contains some correct data blocks, and by considering these as false data blocks, it is possible to almost completely identify the erroneous data blocks.

Note that there is a probability that some data words in an incorrect data block may be determined to be correct by chance, so we need to detect the number of correct data words in the data block. It is determined that it is difficult to stop when the number is more than a predetermined number, and furthermore, the flags F1 to F4 shown in (4) are (
0, 0, 0, 0) may be weighted to determine the correct number of data reads.

In addition, in the above example, all the data hoods that were determined to be 1vf as being incorrectly set the flags F1 to F4 (1, 1, ■, l).
, and from now on, it will be treated as if it were determined to be an error based on the CRC check code C.

Effects of the Invention According to the present invention, erroneous data words can be detected in real time.

[Brief explanation of the drawing]

2131 and 2 are diagrams for explaining conventional error detection and correction, and FIGS. 3 to 1O are diagrams for explaining the present invention. 1) 1 to D4 are data feeds, P and Q are parity check codes, and F and F to F4 are flags for error pointers.

Claims (1)

[Claims] forming a data word with predetermined bits of the digital signal;
A predetermined number of consecutive data words are set as a data block, and an error check code of - &-1 is set according to the sequence within this data block, and the sequence within the above data block is different from the sequence within the above data block. In demodulating a data signal in which a plurality of other error checking codes according to a plurality of sequences are set, two data words that are simultaneously detected as being in error by all of the plurality of error checking codes in the distribution are included. "When none of the other data words included in the data block is detected by at least the plurality of error check codes distributed above," the data word included in the first data block is An error detection method that considers all errors.