JPH0563862B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an error detection method suitable for use in a so-called digital recording/reproducing device.

BACKGROUND TECHNOLOGY AND PROBLEMS For example, it has been proposed to perform AD conversion of audio signals and record and reproduce them as digital signals. In this case, error correction by so-called cross interleaving is performed. That is, a data word is formed using predetermined bits of a digital signal, a predetermined number of successive data words are used as a data block, and a CRC check code, for example, is provided according to a sequence within this data block, and the above-mentioned method is applied to the continuation of the data block. For example, a parity check code is provided, which has a different sequence than that in the data block.

For example, in FIG. 1, the data signal to be recorded/reproduced (transmitted) follows the synchronization signal S and then the address signal A.
are provided, followed by 16-bit data words D ₁ , D ₂ , D ₃ , D ₄ , respectively, and 16-bit parity check codes P, Q, D 4 , respectively.
A CRC check code C is provided to form one data block. This data block is transmitted sequentially. Here, a CRC check code C is formed for data words D ₁ to D ₄ and parity check codes P and Q in the same data block. Furthermore, parity check codes P and Q are formed, for example, for the series shown by solid lines and broken lines when data blocks are arranged sequentially as shown in FIG. In this case, the parity check code Q is created for data that also includes the code P, so the parity check code Q is created after the parity check code P is created, and then the parity check code Q is created.
A CRC check code C is formed.

By doing this, during reproduction (demodulation), in a sequence of any parity check code P or Q, only one error among the data words included in the sequence is detected by the CRC check code. In this case, correction can be performed using parity check code P or Q, and the correction ability can be improved by alternately repeating error correction using the two sequences.

However, in such an apparatus, when recording is performed by reusing a recording medium that has been used once, the previous data signal may be reproduced due to unerased data. In this case, the data signal due to the erased residue is correct if only that part is looked at, so errors cannot be detected by the CRC check code.

Further, depending on the content of the error, detection using the CRC check code may not be performed with probability.

Therefore, if such an erroneous data signal is overlooked and reproduced, an abnormal sound will be generated in the reproduced signal and the sound quality will be extremely degraded.

Alternatively, in the series of parity check codes P or Q mentioned above, if an error data word detected by the CRC check code and an error data word that was not detected occur at the same time, the detected error data word is incorrectly corrected. This may affect the next series and cause the erroneous correction to spread.

OBJECTS OF THE INVENTION The present invention has been designed to ensure that erroneous data words are detected in consideration of these points.

SUMMARY OF THE INVENTION The present invention comprises forming a data word using predetermined bits of a digital signal, using a predetermined number of successive data words as a data block, and providing an error check code according to a series within the data block. When demodulating a data signal in which a plurality of other error check codes with a plurality of sequences different from the sequences in the data block are provided for a series of data blocks, one of the other plurality of error check codes is used. An error in which only the above-mentioned data words in which an error is detected by at least one check code and which are not detected as correct or correct by all of the remaining error check codes in which no error is detected are considered to be errors. A detection method according to which erroneous data words can be reliably detected.

Embodiment In FIG. 3, each word of the random access memory into which a data word is written is filled with 16 bits of data as well as an error pointer flag F(1).
bit) is provided. Here, the overall configuration of the random access memory is the same as that shown in Fig. 2, and is further extended left and right to provide a number of addresses corresponding to the data blocks related to one error correction. be.

For such random access memory,
First, all flags F are set to "1".

Next, the data signals D ₁ to _{D 4} and parity check codes P and Q of the data block determined to be free of errors by the CRC check code C are written to the address corresponding to the address signal A, and the flag of each written word is written. Set F to “0”.

Furthermore, a check is performed on the series of parity check code P, and if there is no data word with flag F set to "1" and the parity check is determined to be an error, the flags of all data words included in the series are checked. Set F to “1”. This is done for all data blocks.

Furthermore, a check is performed on the series of parity check code Q, and if there is no data word with flag F set to "1" and the parity check is determined to be an error, then all data included in that series are checked. Set word flag F to "1". At the same time, in cases other than the above, error correction is performed when there is only one data word in which the flag F is "1". This is done for all data blocks.

From then on, parity check code P,
Error correction is performed alternately using Q sequences to improve the correction ability.

Error detection and correction is performed in this way.
According to this method, the occurrence of an error due to the above-mentioned missed CRC check code is prevented, and furthermore, there is no possibility that the influence of the error will spread due to erroneous correction.

In other words, in Fig. 4, for example, if an error is not detected by the CRC check code C and only the data block a in the center is an error, if a check is performed using the parity check code P, the result will be as shown in the solid line. The data word is determined to be an error, and flag F is set to "1". Next, parity check code Q
At this time, since the flags of data words D ₁ to D ₄ and P of data block a have already been set to "1", the series including this data word is not checked, and the data words The data word enclosed by the dashed line containing Q is determined to be erroneous and henceforth is corrected. Note that E in the figure indicates an error. Data words marked with an E that are not surrounded by lines are errors that would be detected if the parity check code Q sequence was first checked.

However, in the above method, if the parity check determines an error, all data words in the series are considered to be errors even though only one data word in the series is incorrect. The number of erroneous data words becomes extremely large. In this case, the parity check code P sequence in particular is often matched with the AD/DA input/output sequence before cross-interleaving, so this will directly affect the sound quality, and if there are many erroneous data words in this sequence, it will directly affect the sound quality. Sound quality deteriorates significantly.

Furthermore, if all the data words in the parity check code P or Q series are found to be errors, it is extremely difficult to correct them in the other series, and there is a risk that a lot of interpolation will be involved and the sound quality will deteriorate. There will be more.

Therefore, in FIG. 5, each word of the random access memory into which a data word is written has 16
Along with the bit data, 4-bit flags F ₁ , F ₂ , F ₃ , and F ₄ for error pointers are provided. Here, flags F ₁ and F ₂ are for the parity check code P series, and flags F ₃ and F ₄ are for the Q series. If there is an error due to one or more data words and the parity check cannot be performed (0, 1), if the parity check determines an error (1, 0), if the error is determined by the CRC check code (1, 0). A flag of (1, 1) is formed for the determined one.

Accordingly, judgments based on the parity check code P and Q sequences are made for all data blocks.

i.e. random access memory flag F ₁
~Set all _F4 to “1”.

Next, the data signals D ₁ to _{D 4} and parity check codes P and Q of the data block determined to be free of errors by the CRC check code C are written to the address corresponding to the address signal A, and the flag of each written word is written. Set F ₁ to _{F 4} to (0, 1, 0, 1).

Further, the series of parity check code P is checked, and if there is no data word judged as an error by CRC check code C in that series, and no error is detected by parity check, all the data words of that series are checked. Set the flags F ₁ and F ₂ to (0, 0),
When an error is detected, flags F ₁ and F ₂ are set to (1,
0), and if there is one or more data words determined to be erroneous by CRC check code C, leave it as is. This is done for all data blocks.

Furthermore, in the series of parity check codes Q, a check similar to that described above is performed, and flags F ₃ and F ₄ are rewritten as necessary. This is done for all data blocks.

In this result, the flags F ₁ to _{F 4} are (F ₁ , F ₂ , F ₃ , F ₄ )=(1, 0, 1, 0)...(1)=(1, 0, 0, 1)... (2) = (0, 1, 1, 0) ... (3) The data word is either judged to be erroneous in both sequences and has a very high probability of being erroneous, or it is judged to be erroneous in one sequence and untestable in the other. In this case, the possibility of error remains, so these data words are considered to be erroneous.

On the other hand, since the items other than those mentioned above are not considered errors in one series, it is determined that other data words in the series are erroneous in the other series, and these are treated as error-free data words. to be regarded as such.

In other words, in FIG. 6, the part of C that is determined to be an error in the CRC check code C, the above equations (1), (2), and (3)
The parts 1, 2, and 3 that were determined to be incorrect in In the case of the condition, the error data block a surrounded by a solid line
Only the part of Q that is not determined by the series of parity check codes P is determined to be an error, and the number of correct data words that are determined to be errors is reduced.
Therefore, the possibility of deterioration of sound quality is also reduced.

Furthermore, in FIG. 8, if there are error data blocks b and c determined by the CRC check code C along with error data block a, the states of flags F ₁ to _{F 4} of each data word are not shown in the figure. become that way. Here, the results from the parity check code P series are written on the top, and the results from the Q series are shown on the bottom, respectively.E in the code is (1, 0),
U indicates (0, 1), C indicates (1, 1, 1, 1), and no mark indicates (0, 0). In this case, the data words judged to be errors are all contained in data blocks b and c detected by the CRC check code C surrounded by solid lines, and only data words D ₁ and P of data block a.

Furthermore, Fig. 9 shows a case where there is no error due to CRC check code C, but two data blocks a ₁ and a ₂ are erroneous consecutively, and the data word judged to be erroneous in this case is the part surrounded by a solid line. It is.

Further, FIG. 10 shows a case where there is an erroneous data block b due to the CRC check code C in the vicinity of the erroneous data block a, and the data word determined to be erroneous in this case is the part surrounded by a solid line.

However, in the case of this method, if one or more erroneous data words due to the CRC check code C are present in both the parity check code sequences P and Q, it becomes impossible to detect the data word. That is, it becomes impossible to detect data words D ₂ to _{D 4} and Q within data block a in FIG.
Errors may be overlooked.

Furthermore, as mentioned above, in the case of non-feedback type cross interleaving in which the parity check code P sequence does not include the Q sequence, an error caused by the CRC check code C is added to the Q sequence containing the erroneous parity check code Q. The presence of just one data word makes it impossible to test, and the missed data word may lead to false corrections, which could lead to further false corrections.

By the way, as mentioned above, there is an extremely high probability that all of the data blocks that are not detected by the CRC check code C and are erroneous are erroneous.

Therefore, after performing the above-mentioned detection, flags F ₁ to _{F 4} are set to (1,
1, 1, 1). That is, all data words surrounded by broken lines in FIGS. 7 to 10 are treated as errors.

This makes it possible to extremely reduce the chance of missing an erroneous data word.

However, in this case, if there are a large number of data blocks that are determined to be erroneous by the CRC check code C, correct data words will be determined to be erroneous by the parity check, and data words will be unnecessarily erroneous. There is a risk that this may occur. Also
If an erroneous data block that is not detected by the CRC check code C exists in close proximity, a correct data word will be judged as erroneous by both parity check code sequences P and Q, thereby causing the data word's content to be incorrect. In some cases, the entire block of data that is written may be erroneous.

Therefore, in the above-mentioned detection, the data words that are determined to be correct, that is, the portions indicated by 4, 5, and 6 in FIG. All included data words are judged to be incorrect.

For example, if at least one data word is correct, all data words in that data block are considered correct. As a result, in FIGS. 7 to 10, data blocks other than data blocks a, b, c, a ₁ and a ₂ contain correct data words, and by considering these as correct,
Erroneous data blocks can be almost completely identified.

Note that there is a probability that some data words in an erroneous data block may be determined to be correct by chance, so the number of correct data words in the data block is detected and The correct number of data words may be determined by determining that the number of data words is correct sometimes, or by weighting the times when the flags F ₁ to F ₄ indicated by 4 are (0, 0, 0, 0).

In the above example, all data words determined to be incorrect have flags F ₁ to _{F 4} set to (1, 1, 1,
1), and henceforth shall be treated as if it were determined to be an error by CRC check code C.

Effects of the Invention According to the present invention, it has become possible to reliably detect erroneous data words.

[Brief explanation of the drawing]

FIGS. 1 and 2 are diagrams for explaining conventional error detection and correction, and FIGS. 3 to 10 are diagrams for explaining the present invention. _D1 to _D4 are data words, P and Q are parity check codes, and F and _F1 to _F4 are flags for error pointers.

Claims (1)

[Claims] 1 A data word is formed from predetermined bits of a digital signal, a predetermined number of successive data words are used as a data block, and one error check code is provided according to the sequence within this data block.
When demodulating a data signal in which a plurality of other error check codes having a plurality of sequences different from those in the data block are provided for the series of data blocks, Only those data words for which an error is detected by at least one of the error check codes, and which are not detected as correct by all of the remaining error check codes, are considered to be errors. error detection method.