JPS6016758B2 - Gallium nitride light emitting device and its manufacturing method - Google Patents
Gallium nitride light emitting device and its manufacturing methodInfo
- Publication number
- JPS6016758B2 JPS6016758B2 JP54135641A JP13564179A JPS6016758B2 JP S6016758 B2 JPS6016758 B2 JP S6016758B2 JP 54135641 A JP54135641 A JP 54135641A JP 13564179 A JP13564179 A JP 13564179A JP S6016758 B2 JPS6016758 B2 JP S6016758B2
- Authority
- JP
- Japan
- Prior art keywords
- gallium nitride
- nitride layer
- semi
- light emitting
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910002601 GaN Inorganic materials 0.000 title claims description 44
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 26
- 239000013078 crystal Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 230000001747 exhibiting effect Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 229910052594 sapphire Inorganic materials 0.000 description 9
- 239000010980 sapphire Substances 0.000 description 9
- 235000005811 Viola adunca Nutrition 0.000 description 3
- 240000009038 Viola odorata Species 0.000 description 3
- 235000013487 Viola odorata Nutrition 0.000 description 3
- 235000002254 Viola papilionacea Nutrition 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
- H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Description
【発明の詳細な説明】
本発明は窒化ガリウム発光素子の新規な構造及びその製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel structure of a gallium nitride light emitting device and a method for manufacturing the same.
従来窒化ガリウム発光素子は主に材料特性の険討が行な
われているだけであり、実際の素子に組み立てる技術は
殆んど開発されていない。Conventional gallium nitride light emitting devices have only been subject to extensive research into material properties, and almost no technology for assembling them into actual devices has been developed.
通常知られている窒化ガリウム発光素子は、例えば第１
図に示すようにサファイア基板１上にｎ型窒化ガリウム
層２およびｐ型ないし半絶縁性窒化ガリウム層３（以下
ｉ層という）を形成し、ｉ層３表面に蒸着などで金属電
極４を、また側面のｎ型肩２の露出した部分にｎ型オー
ミック電極５を形成し、図のように金属電極４をステム
６にダィボンドし、ｎ型オーミック電極５をポスト７に
紬線９で縞線し、適当なしンズ８をかぶせて形成されて
いる。この素子の形を通常Ｍ−１−Ｎ形と呼び、金属ス
テムと金属ポストの間に適当な電圧を印加することによ
り発光する。このような素子では、細い金属線９による
結線をするために断線を生じたり、また取付ける発光ダ
イオードチップの個数、取付けるべきステムの形状や材
料、かぶせるレンズの材質などによって工程の煩雑さや
信頼性の低下が問題となる。A commonly known gallium nitride light emitting device is, for example, a first
As shown in the figure, an n-type gallium nitride layer 2 and a p-type or semi-insulating gallium nitride layer 3 (hereinafter referred to as i-layer) are formed on a sapphire substrate 1, and a metal electrode 4 is formed on the surface of the i-layer 3 by vapor deposition or the like. In addition, an n-type ohmic electrode 5 is formed on the exposed part of the n-type shoulder 2 on the side surface, and the metal electrode 4 is die-bonded to the stem 6 as shown in the figure, and the n-type ohmic electrode 5 is attached to the post 7 with a striped line using a pongee wire 9. It is formed by covering it with a suitable lens 8. The shape of this element is usually called the M-1-N type, and it emits light by applying an appropriate voltage between the metal stem and the metal post. In such devices, wire breaks may occur due to the thin metal wires 9 being used for connection, and the process may be complicated and reliability may be compromised due to factors such as the number of light emitting diode chips to be attached, the shape and material of the stem to be attached, and the material of the lens to be covered. Decrease becomes a problem.
特にｎ型オーミック電極を小さな発光ダイオードチップ
の側面からとることは、金属電極の形成、ワイヤによる
ポストとの結線が困難であり、量産性に乏しい欠点があ
った。本発明は上記欠点を解消し、ステムないし金属ポ
ストと発光ダイオード上の金属電極とを金属ワイヤで結
線する必要がなく、信頼性・量産性におし、て優れた窒
化ガリウム発光素子及びその製造方法を提供するもので
ある。In particular, when the n-type ohmic electrode is taken from the side surface of a small light emitting diode chip, it is difficult to form a metal electrode and connect it to a post with a wire, which has the drawback of poor mass production. The present invention eliminates the above drawbacks, eliminates the need to connect the stem or metal post and the metal electrode on the light emitting diode with a metal wire, and provides an excellent gallium nitride light emitting device with excellent reliability and mass productivity. The present invention provides a method.
以下図面を用いて本発明の一実施例における発光素子を
詳細に説明する。第２図は本発明の一実施例を示したも
ので、ａは発光ダイオードのチップ斜視図、ｂはａに示
した発光ダイオードチップをステムに取り付けた場合の
断面図を示す。第２図ａにおいて、１ １はサファイア
などの基板であり、その一部に切り溝等の凹凸部９１が
ストライプ状に設けてある。２１はｎ型窒化ガリウム層
、３１は半絶縁性窒化ガリウム層であり、凹凸部９１に
対応する部分の半絶縁性窒化ガリウム層にはｎ型の強い
導電性を示すビットを含んだ領域９２を形成し、この領
域９２はｎ型窒化ガリウム層２１と連続して接続されて
いる。DESCRIPTION OF THE PREFERRED EMBODIMENTS A light emitting device according to an embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 2 shows an embodiment of the present invention, in which a is a perspective view of a light emitting diode chip, and b is a sectional view of the light emitting diode chip shown in a attached to a stem. In FIG. 2a, reference numeral 11 is a substrate made of sapphire or the like, and a part thereof is provided with uneven parts 91 such as grooves in a striped shape. 21 is an n-type gallium nitride layer, 31 is a semi-insulating gallium nitride layer, and the semi-insulating gallium nitride layer in the portion corresponding to the uneven portion 91 has a region 92 containing bits exhibiting strong n-type conductivity. This region 92 is continuously connected to the n-type gallium nitride layer 21 .
上誌凹凸部９１の形成には、基板表面を荒らしておけば
良く、例えば超音波加工やサンドブラストなどを用いれ
ば良い。上記強いｎ型導電性領域９２の少なくとも一部
に接するごとくｎ型オーミック電極４１が、強いｎ型導
電性領域９２には接しないように、半絶縁性窒化ガリウ
ム層３１上に他方の金属電極（以下ｉ層電極と記す。）
５１が形成される。第２図ｂにおいて、６７はステムで
、ステム電極６１及び７１から構成されており、ステム
電極６１と７１は絶縁体９０で絶縁され、かつ一体化さ
れている。To form the above-mentioned uneven portions 91, it is sufficient to roughen the surface of the substrate, and for example, ultrasonic processing, sandblasting, etc. may be used. The other metal electrode ( (hereinafter referred to as i-layer electrode)
51 is formed. In FIG. 2b, a stem 67 is composed of stem electrodes 61 and 71, and the stem electrodes 61 and 71 are insulated by an insulator 90 and integrated.
同図ａに示した発光ダイオードチップを、ｎ型オーミッ
ク電極４１がステムの電極７１に、ｉ層電極５１がステ
ムの電極７１に接続するようにダイボンドし、レンズ８
１をかぶせて本発明の発光素子を完成する。この発光素
子のステムの電極に適当な電圧を印加することにより素
子からの発光が得られる。本発明の発光ダイオードの場
合、ｎ型窒化ガリウム層２１からの電極取り出しを、強
いｎ型導軍性領域を介して基板表面で行なっているため
、ワイヤ結線が不要となり、従って断線による歩留りの
低下を防止できる。The light emitting diode chip shown in FIG.
1 to complete the light emitting device of the present invention. By applying an appropriate voltage to the electrode of the stem of this light emitting element, light emission from the element can be obtained. In the case of the light emitting diode of the present invention, since the electrode is taken out from the n-type gallium nitride layer 21 on the substrate surface through the strong n-type conductivity region, wire connection is not required, and therefore the yield is reduced due to wire breakage. can be prevented.
また強いｎ型導電性領域の形成は、サファイア基板１１
に、スクラィバ等により凹凸領域を形成すれば良く、従
釆に比して簡単に形成でき、電極の取り出しが容易にな
る利点がある。In addition, the formation of a strong n-type conductive region is possible on the sapphire substrate 11.
In addition, it is sufficient to form the uneven region using a scriber or the like, which has the advantage that it can be formed more easily than in the case of a follower, and that the electrode can be easily taken out.
上記の説明では凹凸部９１をストライプ状に設けた例を
掲げたが、凹凸部９１の形状がこれに限定されるもので
ないことはもちろんであり、必要ならば円形にすること
もできる。In the above description, an example is given in which the uneven portions 91 are provided in a striped shape, but it goes without saying that the shape of the uneven portions 91 is not limited to this, and may be circular if necessary.
次に第３図によって、第２図ａに示した本発明の発光ダ
イオードチップの製造方法を説明する。Next, a method for manufacturing the light emitting diode chip of the present invention shown in FIG. 2a will be explained with reference to FIG.
まず１に示すようにサファイア等の基板１２を用意し、
ローこ示すように基板１２の表面にスクラィバないしダ
ィサ等の加工装置を用いて必要なピッチで切り溝ないし
スクラッチ９３を形成する。この基板に例えば気相成長
法などでｍに示すようにまずｎ型窒化ガリウム層２２を
形成し、さらにＷに示すように亜鉛等をドープして半絶
縁性にした窒化ガリウム層３２を形成する。このとき切
り溝の上に相当する部分は、半絶縁性とならずに、ｎ型
の高い導電性を示すビットを含んだ結晶９４となってい
る。次にＶに示すように、マスク蒸着ないしフオトェツ
チ工程等半導体工業でよく知られた工程により、上記ビ
ットを含んだｎ型領域９４の少なくとも一部に接するご
とくｎ型オーミック電極４２を、上記ｎ型領域９４を含
まない領域にｉ層電極５２を形成する。このウェハをダ
ィサ等でチップに切断すれば第２図ａに示した発光ダイ
オードチップとなる。以下本発明を実施例にもとずいて
説明する。First, as shown in 1, a substrate 12 such as sapphire is prepared,
As shown in the figure, grooves or scratches 93 are formed on the surface of the substrate 12 at a required pitch using a processing device such as a scriber or a dicer. On this substrate, an n-type gallium nitride layer 22 is first formed as shown in m by, for example, a vapor phase growth method, and then a gallium nitride layer 32 doped with zinc or the like to make it semi-insulating is formed as shown in W. . At this time, the portion corresponding to the top of the groove is not semi-insulating, but is a crystal 94 containing bits exhibiting high n-type conductivity. Next, as shown in V, the n-type ohmic electrode 42 is attached to the n-type ohmic electrode 42 in contact with at least a portion of the n-type region 94 containing the bit, using a process well known in the semiconductor industry such as mask deposition or photo-tetch process. The i-layer electrode 52 is formed in a region that does not include the region 94. If this wafer is cut into chips using a dicer or the like, the light emitting diode chips shown in FIG. 2a will be obtained. The present invention will be explained below based on examples.
＜実施例 １＞第２図において基板１１をサファイア基
板で形成し、凹凸部９１としてスクラィバによるきずを
つけた。<Example 1> In FIG. 2, the substrate 11 was formed of a sapphire substrate, and scratches were made as uneven portions 91 using a scriber.
ｎ型半導体層２１はｎ２１び７〜１び９仇‐８の姿化ガ
リウム層を気相成長法により厚さ１０〜１００ムｍで形
成した。半絶縁層３１はｐ型不純物として、例えば亜鉛
を添加した室化ガリウムを２０山以下の厚さに気相成長
法で成長させて形成した。金属電極４１，５１は葵着マ
スクを用いて金属を真空蒸着により付着させて形成した
。この素子をステムの上にマウントする方法は、熱圧着
法あるいは半田によった。以上に示した本実施例の発光
素子は、緑〜青紫の領域の発光を示した。The n-type semiconductor layer 21 is formed by forming gallium layers of n21, 7 to 1, and 9 to 8 to a thickness of 10 to 100 mm by vapor phase epitaxy. The semi-insulating layer 31 is formed by growing gallium nitride doped with zinc as a p-type impurity to a thickness of 20 peaks or less by vapor phase growth. The metal electrodes 41 and 51 were formed by depositing metal by vacuum evaporation using an Aoi mask. This element was mounted on the stem by thermocompression bonding or soldering. The light-emitting element of this example shown above emitted light in the green to bluish-violet range.
〈実施例 ２＞
基板１１としてスピネル単結晶および六方晶系炭化シリ
コン単結晶を用いて実施例１と同じ条件で素子を形成し
たところ同機に緑〜青紫の発光をする素子が得られた。<Example 2> When a device was formed under the same conditions as in Example 1 using a spinel single crystal and a hexagonal silicon carbide single crystal as the substrate 11, a device emitting green to blue-violet light was obtained.
＜実施例 ３＞実施例１において、スクライバの代りに
ダイサ−を用いて中約１００ムｍの切り溝を入れたとこ
ろ、その幅に等しい領域に帯状をなして導電性のビット
を多数含む領域が得られた。<Example 3> In Example 1, when a dicer was used instead of the scriber to cut a groove with a diameter of about 100 mm, an area equal to the width of the groove formed in a band shape and containing many conductive bits. was gotten.
これを用いて同機に緑に青紫の発光をする素子が得られ
た。＜実施例 ４＞実施例１において、スクライバの加
重を大きくし約５一の深さに至る切り溝を格子状に入れ
たサファイア基板１１を用いて、窒化ガリウム結晶を成
長させたところ、切り溝の上部に導電性のビットを含む
領域が形成されると同時に切り溝に沿ってサファイア基
板内にクラツクが発生した。Using this, an element that emits green to blue-violet light was obtained on the same machine. <Example 4> In Example 1, when a gallium nitride crystal was grown using the sapphire substrate 11 in which the scriber load was increased and the kerfs to a depth of approximately 5 mm were formed in a lattice pattern, the kerfs were A crack was generated in the sapphire substrate along the kerf at the same time as a region containing conductive bits was formed on top of the sapphire substrate.
このクラックに沿って割ることにより、第４図に示すよ
うな発光ダイオードチップを容易に得ることができた。
すなわち、基板１３に格子状に深い溝９６を入れておく
と、ダイオードチップの周辺部をとりかこむように導電
性にビットを含む領域９５が表面に達するまで形成され
る。この導電・性の領域９５にかかるようにｎ型電極４
３、かからないようにｉ層電極５３を形成した後、ロー
ラーで軽く圧することにより図に示す様なチップが容易
に得られ、このようにして作られた素子により緑〜青紫
の発光が得られた。なお図で３３は半絶縁性窒化ガリウ
ム層、２３はＮ型窒化ガリウム層である。＜実施例 ５
＞
本発明の方法を数字表示に用いた例を第５図を用いて述
べる。By breaking along this crack, a light emitting diode chip as shown in FIG. 4 could be easily obtained.
That is, if deep grooves 96 are formed in the substrate 13 in a lattice pattern, a conductive bit-containing region 95 is formed surrounding the peripheral portion of the diode chip until it reaches the surface. The n-type electrode 4 is placed over this conductive/sexual region 95.
3. After forming the i-layer electrode 53 so that it does not overlap, a chip as shown in the figure can be easily obtained by pressing lightly with a roller, and the device made in this way can emit green to blue-violet light. . In the figure, 33 is a semi-insulating gallium nitride layer, and 23 is an N-type gallium nitride layer. <Example 5
> An example of using the method of the present invention for numerical display will be described using FIG.
同図ａはサファイア基板上の１数字分を示してあり、そ
の一部に超音波加工によって表面を荒らした領域５５を
設けてある。このような処理をした基板上に実施例１と
同様な方法によりｎ型および半絶縁性のＧａＮ結晶を成
長させたところ、基板上の加工をした領域５５に相当す
る部分の表面は高い導電率をもつｎ型であり、その他の
表面は高抵抗層５９であった。このような結晶に同図ｂ
に示すように数字表示素子を形成した。ここで５６は、
基板の５５で示した領域に形成したｎ側金属電極であり
、“日”の字型の金属電極５７と小数点の金属電極５８
は、結晶の半絶縁層５９上に形成した。ｎ側電極を負に
、“日”の字型及び小数点の電極を正になるように電圧
を印加したところ音色の発光が得られた。ｎ側電極５６
と小数点電極５８の大きさないし形を変えておくことに
より識別を容易にすることも可能である。Figure a shows one digit on the sapphire substrate, and a region 55 whose surface has been roughened by ultrasonic processing is provided in a part thereof. When an n-type and semi-insulating GaN crystal was grown on the substrate treated in this manner in the same manner as in Example 1, the surface of the portion corresponding to the processed region 55 on the substrate had high conductivity. The other surface was a high resistance layer 59. In such a crystal, the same figure b
A numeric display element was formed as shown in FIG. Here, 56 is
This is the n-side metal electrode formed in the area indicated by 55 on the substrate, and includes a “Japanese”-shaped metal electrode 57 and a decimal point metal electrode 58.
was formed on the crystalline semi-insulating layer 59. When a voltage was applied so that the n-side electrode was negative and the "day"-shaped and decimal point electrodes were positive, tonal light emission was obtained. n-side electrode 56
It is also possible to make identification easier by changing the size or shape of the decimal point electrode 58.
数字パターンのかわりにドットマトリックスとすること
によって文字表示とすることも可能である。以上述べて
きたように、本発明は、単結晶基板、その上に形成され
た導電性窒化ガリウム層、さらにその上に形成された半
絶縁性窒化ガリウム層を有してなる発光素子及びその製
造方法において、上記単結晶基板の一部に凹凸領域を設
け、この凹凸領域に対応し、導電性及び半絶縁性窒化ガ
リウム層を貫通して表面に達する、導電性窒化ガリウム
層と導電型が同じで高い導電率を示す高導電性領域を形
成し、高導電性領域と半絶縁性窒化ガリウム層とから電
極を取り出すようにしたもので、この電極を直接ステム
に接続することが可能となり、結線用の金属ワイヤが必
要でなくなり、信頼性・量産性に優れる。It is also possible to display characters by using a dot matrix instead of a numerical pattern. As described above, the present invention relates to a light-emitting device having a single crystal substrate, a conductive gallium nitride layer formed thereon, and a semi-insulating gallium nitride layer formed thereon, and its manufacture. In the method, an uneven region is provided in a part of the single crystal substrate, and the conductive gallium nitride layer corresponding to the uneven region penetrates the conductive and semi-insulating gallium nitride layer to reach the surface, and has the same conductivity type as the conductive gallium nitride layer. A highly conductive region exhibiting high conductivity is formed in the wafer, and an electrode is taken out from the highly conductive region and the semi-insulating gallium nitride layer, making it possible to connect this electrode directly to the stem, making it possible to connect There is no need for additional metal wires, resulting in excellent reliability and mass production.
またｎ型窒化ガリウム層からの電極の取り出しが容易と
なり、工程の簡略化がはかれる利点もある。Further, there is an advantage that the electrode can be easily taken out from the n-type gallium nitride layer, and the process can be simplified.
第１図は従来の窒化ガリウム発光素子をステムに取りつ
けた状態の断面図、第２図ａは本発明の窒化ガリウム発
光素子の斜視図、同ｂはａに示した素子をステムに取り
つけた状態を示す断面図、第３図１〜Ｖは本発明の窒化
ガリウム発光素子の製造工程を順に示す図、第４図ａは
本発明の他の実施例の斜視図、同ｂは同断面図、第５図
ａ，ｂは本発明の素子を数字表示に応用した例を示す平
面図である。
１，１１・・・・・・基板、２，２１・・・…ｎ型窒化
ガリウム層、３，３１・・・・・・半絶縁性窒化ガリウ
ム層、４１……ｎ型オーミツク電極、５１……ｉ層電極
、９１・・・・・・凹凸領域、９２・・・・・・ｎ型高
導電性領域、６７……ステム。
第１図
第２図
（ＯＪ
（も）
第３図
（１）
ｍ’
‘血
‘村，
【Ｖ１
第４図
「〇，
‘ｂー
第５図
（は）
（ｂーFIG. 1 is a cross-sectional view of a conventional gallium nitride light emitting device attached to a stem, FIG. 3. 1 to 3 V are diagrams sequentially showing the manufacturing process of the gallium nitride light emitting device of the present invention, FIG. 4 a is a perspective view of another embodiment of the present invention, and FIG. FIGS. 5a and 5b are plan views showing an example in which the device of the present invention is applied to a numerical display. 1, 11... Substrate, 2, 21... N-type gallium nitride layer, 3, 31... Semi-insulating gallium nitride layer, 41... N-type ohmic electrode, 51... ...i-layer electrode, 91 ... uneven region, 92 ... n-type highly conductive region, 67 ... stem. Figure 1 Figure 2 (OJ (also) Figure 3 (1) m''Blood' Village, [V1 Figure 4 '〇, 'b-Figure 5 (ha) (b-
Claims (1)
ガリウム層および半絶縁性窒化ガリウム層を形成してな
り、前記単結晶基板表面の一部に設けられた凹凸領域と
、この凹凸領域に対応し導電性及び半絶縁性窒化ガリウ
ム層を貫通して表面に達する、導電性窒化ガリウム層と
同導電型で高導電率を示す高導電性領域とを有し、前記
半絶縁性窒化ガリウム層と高導電性領域に電極を設けた
ことを特徴とする窒化ガリウム発光素子。 ２ 半導体または絶縁体の単結晶基板表面上の一部に、
スクライバまたはダイサ等により浅い切り溝またはひつ
かき傷等の凹凸領域を形成する工程と、前記凹凸領域を
含む基板全面に一導電性の窒化ガリウム層を形成する工
程と、その上に反対導電型不純物を添加した半絶縁性窒
化ガリウム層を形成する工程と、前記一導電性の窒化ガ
リウム層および半絶縁性窒化ガリウム層を形成する工程
により前記凹凸領域上に表面にまで達するよう形成され
た高導電性領域上と半絶縁性窒化ガリウム層上に電極を
形成する工程とを含むことを特徴とする窒化ガリウム発
光素子の製造方法。[Claims] 1. A conductive gallium nitride layer and a semi-insulating gallium nitride layer are formed on a single crystal substrate of a semiconductor or an insulator, and an uneven region is provided on a part of the surface of the single crystal substrate. and a highly conductive region having the same conductivity type as the conductive gallium nitride layer and exhibiting high conductivity, which corresponds to the uneven region and reaches the surface by penetrating the conductive and semi-insulating gallium nitride layer, A gallium nitride light emitting device comprising a semi-insulating gallium nitride layer and an electrode provided in a highly conductive region. 2. On a part of the surface of a semiconductor or insulator single crystal substrate,
A step of forming an uneven region such as a shallow cut groove or scratch using a scriber or a dicer, a step of forming a gallium nitride layer of one conductivity on the entire surface of the substrate including the uneven region, and an impurity of the opposite conductivity type is formed on the gallium nitride layer of one conductivity. A highly conductive layer formed on the uneven region so as to reach the surface by the step of forming a semi-insulating gallium nitride layer doped with , and the step of forming the mono-conductive gallium nitride layer and the semi-insulating gallium nitride layer. 1. A method of manufacturing a gallium nitride light emitting device, the method comprising the step of forming an electrode on a semi-insulating gallium nitride layer and a semi-insulating gallium nitride layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54135641A JPS6016758B2 (en) | 1979-10-19 | 1979-10-19 | Gallium nitride light emitting device and its manufacturing method |
| US06/199,097 US4396929A (en) | 1979-10-19 | 1980-10-20 | Gallium nitride light-emitting element and method of manufacturing the same |
| US06/480,794 US4476620A (en) | 1979-10-19 | 1983-03-31 | Method of making a gallium nitride light-emitting diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54135641A JPS6016758B2 (en) | 1979-10-19 | 1979-10-19 | Gallium nitride light emitting device and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5660076A JPS5660076A (en) | 1981-05-23 |
| JPS6016758B2 true JPS6016758B2 (en) | 1985-04-27 |
Family
ID=15156550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54135641A Expired JPS6016758B2 (en) | 1979-10-19 | 1979-10-19 | Gallium nitride light emitting device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6016758B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH072290Y2 (en) * | 1987-09-15 | 1995-01-25 | アイシン精機株式会社 | Power seat equipment |
| CA2037198C (en) | 1990-02-28 | 1996-04-23 | Katsuhide Manabe | Light-emitting semiconductor device using gallium nitride group compound |
| JP3679720B2 (en) | 2001-02-27 | 2005-08-03 | 三洋電機株式会社 | Nitride semiconductor device and method for forming nitride semiconductor |
-
1979
- 1979-10-19 JP JP54135641A patent/JPS6016758B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5660076A (en) | 1981-05-23 |
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