JP2987111B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device using a sapphire substrate, and more particularly to a semiconductor device using a sapphire substrate, such as a light emitting diode element or an integrated circuit, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, GaN, In _x Ga ₁ -xN, Ga
such _x Al _1-x N, gallium nitride (GaN) based III
-Group V compound semiconductors are drawing attention as materials for blue LEDs and blue laser diodes (LDs). This G
By using an aN-based compound semiconductor, it has become possible to obtain a blue device having a certain luminous intensity. These blue light-emitting devices using a GaN-based compound semiconductor use a sapphire substrate as a substrate.
Some proposals have been made in, for example, JP-A-320280. FIG. 6 shows an example of the basic structure of such a conventional LED. That is, the blue light emitting element 2 includes the n-type GaN semiconductor layer 202 and the p-type GaN semiconductor layer 203 that are stacked on the sapphire substrate 100 via the buffer layer 201. These n-type GaN semiconductor layers 202 and p-type G
Light emission can be performed by injecting carriers into a pn junction region between the aN semiconductor layers 203.

[0003] In order to manufacture such a blue light emitting device,
A predetermined sapphire substrate 100 is prepared, the sapphire substrate 100 is set in a reaction chamber (growth chamber) such as an MO-CVD method, and the GaN semiconductor layers 201, 202, and 203 are stacked on the sapphire substrate 100. To go. Thereafter, the laminated substrate is taken out of the reaction chamber, cut into an appropriate size, and separated into individual chips. Finally, the chip is connected to a wire frame, and necessary wiring and molding are performed to produce a product.

On the other hand, there is a remarkable increase in the degree of integration in recent semiconductor integrated circuits, particularly in dynamic random access memory (DRAM) technology which has entered the gigabit era. However, with the progress of integration, DRA
The memory cell area of M tends to decrease more and more, and it is difficult to secure a cell capacity for preventing loss of stored contents caused by alpha rays existing in nature, that is, a so-called soft error. Therefore, a semiconductor element is formed on a single crystal silicon film on a sapphire substrate as shown in FIG. This is because the crystal lattice spacing of silicon can be matched with the lattice spacing of sapphire, and a high-quality silicon film can be obtained. A so-called SOS (Silicon-On-Sapph) shown in FIG.
The ire) element can be easily miniaturized and can operate at high speed, and is promising as a high-performance element. That is, since the SOS element has a structure in which a single crystal Si layer formed on a sapphire substrate is used as an active region, elements such as a transistor in the active region are completely separated, and furthermore, an integrated circuit or the like is formed. This is because, in the case where is formed, advantages such as a small coupling capacitance with the substrate and suppression of latch-up in CMOS are expected. At the same time, S
The OS element generates electron-hole pairs generated by alpha rays,
The soft error resistance in a DRAM cell or the like is greatly improved because it can be limited to a thin single crystal silicon film on a sapphire substrate. FIG. 7 shows a DRAM having an SOS structure.
FIG. 2 is a diagram showing a cell, in which a data line (bit line) 409 is formed via a contact electrode 408 above an n ⁺ source region 306 formed in a silicon film 303 epitaxially grown on a sapphire substrate 100. .
Further, a storage electrode 405, a capacitor insulating film 406, and a counter electrode 407 are formed above the n ⁺ drain region 306 via a contact electrode 410. Also, n ⁺ source region 3
A gate electrode 305 of polysilicon or the like is formed via a gate oxide film 304 on the channel region between the channel region 06 and the n ⁺ drain region 306 and the upper portion of the silicon film 303. Function.

[0005]

In a semiconductor device such as an LED or an SOS-DRAM using such a conventional sapphire substrate, the hardness of the sapphire substrate is considerably large, so that the cut in a state in which the semiconductor layers are laminated cannot be performed. It was very difficult. Usually, the sapphire substrate is cut with a diamond cutter. However, the sapphire substrate has to be polished in advance so as to be very thin, for example, 250 μm or less at most and about 100 μm in some cases. However, it is very difficult to polish to such a thinness in terms of mechanical strength and the like, and there is a concern that a light emitting layer of a light emitting element or a growth layer which becomes a channel region of a switching transistor of a DRAM may be strained. Polishing a harder substrate thinly has a practical problem that a considerable processing time is required. Therefore, the production cost increases,
This has been an obstacle to mass production.

In view of the above problems, an object of the present invention is to provide a semiconductor device using a sapphire substrate that is easy to manufacture and a method of manufacturing the same.

Another object of the present invention is to provide a high yield LE.
An object of the present invention is to provide an integrated circuit such as a light emitting element such as D or an SOS-DRAM and a method of manufacturing the same.

Still another object of the present invention is to provide a semiconductor device such as a light emitting element or an SOS integrated circuit suitable for mass production and a method of manufacturing the same.

[0009]

In order to achieve the above-mentioned object, the present invention relates to a semiconductor device such as an LED or an SOS-DRAM formed on a sapphire substrate, wherein the surface roughness of the sapphire substrate is reduced to a predetermined value. It is characterized in that it is finished to a degree of flatness, that is, a level of flatness of 30 nm or less when measured by a probe method. The probe method means, for example, a diameter of 0.6 to 1
This method refers to a method of measuring unevenness on the surface of a sample using a tungsten needle (probe) having a diameter of μm as a stylus.

That is, as shown in FIGS. 1 and 5, a semiconductor device according to the present invention has a first conductivity type semiconductor single crystal layer 101, 102, 1 formed on a sapphire substrate 100.
03 or 303 and the second conductivity type semiconductor regions 105 and 106 formed above the semiconductor single crystal layer or the second conductivity type semiconductor region 306 formed inside the semiconductor single crystal layer. A semiconductor device having at least a structure, wherein the surface roughness of the sapphire substrate 100 is the flatness described above.

For more specific description, a blue light emitting diode shown in FIG. 1 will be described as an example. That is, a blue light-emitting diode as an example of the present invention includes a first cladding layer made of a gallium nitride (GaN) -based semiconductor having a first conductivity type and a substantially intrinsic GaN.
An active layer made of a base semiconductor and a second layer opposite to the first conductivity type.
A second cladding layer made of a conductive GaN-based semiconductor,
Double heterostructure (DH) laminated on a sapphire substrate
Structure), the surface roughness of the sapphire substrate is:
It is characterized by being 30 nm or less by a probe method. The first conductivity type refers to, for example, n-type, and the second conductivity type refers to p-type opposite to n-type. However, the n-type and p-type may be reversed.

The method of manufacturing a semiconductor device according to the present invention will be described by taking a light emitting diode as an example. A buffer layer made of a first conductivity type gallium nitride based semiconductor and a first conductivity type gallium nitride based semiconductor made of a first conductivity type gallium nitride based semiconductor will be described. A first cladding layer, an active layer substantially composed of a true gallium nitride based semiconductor, and a second cladding layer composed of a second conductivity type gallium nitride based semiconductor opposite to the first conductivity type. The sapphire substrate is continuously laminated on the sapphire substrate, and the sapphire substrate is polished to a predetermined thickness so as to have a smooth surface. Specifically, it is polished until its transmittance becomes 60% or more, and then cut into a plurality of chips for manufacture. This polishing may be completed with a thickness of about 260 μm to 400 μm, and does not need to be made too thin.

With the above configuration, the semiconductor device of the present invention can be easily separated even if the sapphire substrate is thick. Therefore, polishing of the sapphire substrate is greatly simplified. Further, no strain is applied to the active layer and the channel region.

Therefore, the yield of the semiconductor device as a product is greatly improved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a gallium nitride (GaN) -based compound semiconductor blue light emitting diode according to a first embodiment of the present invention. In the GaN-based compound semiconductor blue light emitting diode 1 of the present invention, a buffer layer 101 made of a GaN-based semiconductor and an n-type contact layer 102 made of an n-type GaN-based semiconductor are formed on a sapphire substrate 100. First of n-type GaN-based semiconductor
Active layer 1 made of GaN-based semiconductor
04, a second clad layer 105 made of a p-type GaN-based semiconductor, an n-type electrode 108 connected to a p-type contact layer 106 made of a p-type GaN-based semiconductor, and an n-type semiconductor contact layer 102, and a second clad layer P connected to 105
The side electrode 107 is formed. The n-side electrode 108 is formed on the bottom of a groove formed by etching the p-type contact layer 106, the second clad layer (p-type clad layer) 105, the active layer 104, and the second clad layer (n-type clad layer) 103. Is formed.

In the present invention, In as a GaN-based semiconductor, In
_x Al _x Ga _1-xy N compound semiconductor was used. this is,
By adjusting the compositions x and y, a wide range of blue light emission can be realized. Hereinafter, examples of specific compositions will be described. Here, the composition x, y is 0 ≦ x ≦ 1, 0 ≦ y ≦ 1
And x + y = 1. The buffer layer 101 made of a GaN-based semiconductor reduces the mismatch between the lattice of the n-type contact layer 102 made of the n-type GaN-based semiconductor and the sapphire substrate 100. In _x Al _y G
The value of each parameter of a _1-xy N is, for example, 0 ≦ x ≦
1, 0 ≦ y ≦ 1, preferably 0 ≦ x ≦ 0.5, 0 ≦ y
≦ 0.5. n-type semiconductor contact layer 102
Is for providing a contact surface to the n-side electrode 108. In the case of the n-type contact layer 102, the value of each parameter of In _x Al _y Ga _1-xy N is, for example, 0 ≦ x
≦ 1, 0 ≦ y ≦ 1, preferably 0 ≦ x ≦ 0.3, 0 ≦ y
≤ 0.3. Again, impurities such as silicon (Si) and selenium (Se) are added in order to obtain the n-type, and the impurity density is 6 × 10 ¹⁸ cm ⁻³ . The n-type cladding layer (first cladding layer) 103 forms the n-side of the pin junction forming the light emitting region. The value of each parameter of In _x Al _y Ga _1-xy N of the n-type cladding layer 103 is appropriately adjusted depending on the wavelength to be emitted. For example, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, preferably 0 ≤
x ≦ 0.3 and 0.1 ≦ y ≦ 1 are selected. Also,
Impurities such as Si and Se are added in order to obtain the n-type, and the impurity density is 3 × 10 ¹⁸ cm ⁻³ .

The active layer 104 made of a GaN-based semiconductor is
This is a substantially intrinsic semiconductor layer that forms a central region of the light emitting region. In _x Al _y Ga of the active layer 104
The value of each parameter of _1-xy N is appropriately adjusted depending on the wavelength to emit light. For example, 0 ≦ x ≦ 1, 0 ≦ y ≦
1 Preferably, 0 ≦ x ≦ 0.5 and 0 ≦ y ≦ 0.6 are selected. A second cladding layer (p-type cladding layer) 105 made of a p-type GaN-based semiconductor is used to form a pi for forming a light emitting region.
Constructs the p-side of the n-junction. In of the p-type cladding layer 105
Values of the parameters _x Al _y Ga _1-xy N, in relation to the n-type cladding layer 103 and the active layer 104, is adjusted appropriately by wavelength to emit light, for example, 0 ≦ x ≦
0, 0 ≦ y ≦ 1, preferably 0 ≦ x ≦ 0.3, 0.1 ≦
It is selected so that y ≦ 1.0. In order to obtain a p-type, magnesium (Mg), beryllium (Be), zinc (Z
n) is added. The impurity density is
It is 3 × 10 ¹⁸ cm ⁻³ . The p-type contact layer 106 made of a p-type GaN-based semiconductor is for providing a contact surface to the electrode 107. p-type contact layer 10
The value of each parameter of In _x Al _y Ga _1-xy N of _No. 6 is:
For example, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, preferably 0 ≦ x ≦
0.3, 0 ≦ y ≦ 0.3. In addition, impurities such as Mg, Be, and Zn are added to obtain a p-type. The impurity density is 6 × 10 ¹⁸ cm ⁻³ .

The p-side electrode 107 is a transparent electrode for emitting light from the active layer 104 made of a GaN-based semiconductor. Specifically, it is formed from a compound of a metal and oxygen such as ITO (indium tin oxide).
Metals such as l and Ni may be formed sufficiently thin. The n-side electrode 108 is the other electrode, but need not be particularly transparent. For example, it may be formed of a metal such as Ti, Au, and Ni.

In the above setting, In _x Al _y Ga _1-xy
The value of each composition x and y of N is determined by the n-type cladding layer 103 and p
The band gap of the mold cladding layer 105 is
Is determined to be larger than the band gap. By doing so, the amount of carriers injected into the active layer 104 made of a GaN-based semiconductor is increased,
The emission intensity can be further improved.

Next, the method of manufacturing the blue LED is described in 2 (a) to
This will be described with reference to FIG.

(A) First, a sapphire substrate 1 having a predetermined thickness
00 on using the MOCVD method or the like as shown in FIG. _{2 (a) n-In x} Al y Ga 1-xy N buffer layer 101, n
_{-In x Al y Ga 1-xy} N contact layer 102, n-
_{In x Al y Ga 1-xy} N cladding layer 103, an undoped _{In x Al y Ga 1-xy} N active layer 104, p-In _x
Al _y Ga _1-xy N cladding layer 105, p-In _x Al
_{The y} Ga _1-xy N contact layer 106 is continuously laminated. In the case of growing by the normal pressure MO-CVD method, for example, Ga (CH ₃ ) ₃ , In (CH ₃ ) ₃ , A
It may be introduced using l (CH ₃ ) ₃ and NH ₃ together with a carrier gas composed of hydrogen or nitrogen. The growth pressure is naturally 1 atmosphere (about 100 kP) in the atmospheric pressure MOCVD method.
a). Of course, the growth may be performed by the low pressure MOCVD method. Thus, the GaN-based semiconductor is continuously grown from the buffer layer 101 to the contact layer 106.
In that case, the composition ratio of each layer may be adjusted by switching the respective component ratios of the reaction gas. In addition, in order to add impurities, SiH ₄ , CP ₂ Mg, or the like may be appropriately introduced.

(B) Next, a buffer layer 101 is formed on the
-The sapphire substrate 100 on which the contact layer 106 is continuously deposited is taken out of the CVD furnace, and preparation for U-groove etching is performed. _{That, p-In x Al y Ga} 1-xy N top to the sputtering method or CVD contact layer 106
Oxide film (Si) used as an etching mask
O ₂ film). Then, a photoresist pattern is formed on the oxide film by a predetermined photolithography technique, and the oxide film is selectively etched.

(C) The photoresist used for etching the oxide film is left, and the p-type contact layer 10 is formed using an etching mask composed of the photoresist and the SiO ₂ film.
6, p-type cladding layer 105, non-doped active layer 104,
The n-type cladding layer 103 is etched to form a U-shaped groove 118 as shown in FIG. 2B, and the n-type contact layer 102 is exposed at the bottom of the U-shaped groove 118. n-type contact layer 1
02 may be further etched.

(D) After removing the etching mask material, the substrate is washed, and a predetermined slight etching or the like is performed.
A p-type electrode 107 made of a transparent electrode material such as a TO film is formed on the p-type contact layer. As the p-side electrode 107, an ITO film or the like is formed by using a so-called lift-off method as shown in FIG.
Is patterned as shown in FIG. The ITO film may be deposited by sputtering or CVD.

(E) Next, the substrate is washed, and a metal material for the n-side electrode 108 such as Ti, Al, or Ni is deposited on the entire surface by a sputtering method or a vacuum evaporation method. Then, the U-groove 11 is formed by using a photolithography method or a lift-off method.
As shown in FIG. 2B, patterning of the p-side electrode 108 is performed on the bottom of the electrode 8. In the case of the lift-off method, of course, a photoresist pattern is formed before depositing a metal thin film.

(F) Next, the sapphire substrate 100 is attached to a predetermined polishing jig 13 as shown in FIGS. Polishing is performed until the surface of the substrate 100 reaches a predetermined smoothness. The polishing of the sapphire substrate will be described later.

(G) After the basic structure of the blue light emitting device is completed in this way, a large number of chips are obtained by cutting the blue light emitting device into an appropriate size with a diamond cutter. Then, these chips are mounted on a predetermined stem, and are molded after wire bonding, whereby the blue LED of the present invention is completed.

The polishing of the sapphire substrate 100 will be described below. In the present invention, polishing of the sapphire substrate 100 is completed when its thickness is 260 μm or more, for example, from 280 μm to about 400 μm. It is well known to those skilled in the art that, as it is in the prior art, it is not possible to cut well using a diamond cutter, but the inventor has performed a predetermined surface treatment of the present invention after trial and error. Thick sapphire substrate 1
Even if it was 00, the condition for easily cutting was determined. In other words, by making the surface optically very smooth, it becomes easy to cut even a thick sapphire substrate.

FIGS. 2 (c) and 2 (d) and FIG.
This will be described with reference to FIG. First, as shown in FIG. 3, a cloth 12 is laid on a glass substrate 11, and water is poured on the cloth 12 to put an abrasive. The abrasive has a particle size of about 2000 to 4000. On the other hand, as shown in FIGS.
The sapphire substrate 100 is fixed to the rotatable holder 13 with the surface on which the stacked body of the system semiconductor is formed facing upward. Then, the lower surface of the sapphire substrate 100 on the holder 13 is pressed against the abrasive while rotating, and polishing is performed.

Such polishing is performed until the surface roughness becomes equal to or less than 30 nm, preferably equal to or less than 10 nm as measured by a probe method. The probe method is a means for measuring surface unevenness using a stylus (probe), and for example, an apparatus such as “Alpha Step” or “Tari Step” may be used. Actually, even without using the probe method, the smoothness of this surface can be determined by the transmittance of the substrate. That is, the present inventors have found that there is a certain relationship between the smoothness of the surface and the light transmittance, and use this fact. Specifically, when the transmittance of the substrate after polishing is smaller than 60%, it is used that the surface roughness is too large, the chips are not separated well, and the yield is reduced. That is, polishing may be performed so that the transmittance after polishing is 60% or more. FIG. 4 shows the relationship between the substrate transmittance and the chip yield. As can be seen from FIG. 4, in the present invention, in order to improve the yield of the chip forming process, it is preferable to perform polishing until the transmittance becomes 60% or more, preferably 70% or more. The fact shown in FIG. 4 indicates that if fine cracks and the like on the surface of the sapphire substrate are removed and the surface is sufficiently smooth, cutting with a diamond cutter can achieve a high yield even if the sapphire substrate is thick. It is.

As described above, the GaN according to the present invention
The polishing of the blue light-emitting device based on a compound semiconductor requires only a short time, so that the manufacturing process is greatly simplified. In particular, if the sapphire substrate is optically smoothed while keeping a certain thickness without being thinned, it becomes easy to cut the sapphire substrate into predetermined chips, which is suitable for mass production. Therefore, according to the manufacturing method of the present invention, the yield of the GaN-based blue light emitting device as a product is greatly improved.

Although the blue light emitting diode has been described above, the present invention is applicable to any semiconductor device using a sapphire substrate, and may be a red, yellow, or infrared light emitting diode or a semiconductor laser. Further, the present invention can be applied to a photodetector such as a pin photodiode using a sapphire substrate.

FIG. 5 is a block diagram of a second embodiment of the present invention.
FIG. 2 is a schematic sectional view of an OS-DRAM. That is, the present invention is not limited to the light emitting element shown in the first embodiment, but may be used for an SOS integrated circuit such as a DRAM as shown in FIG. The SOS-DRAM of the present invention shown in FIG.
An n ⁺ source region 306 and an n ⁺ drain region 306 constituting a switching transistor are formed in a silicon thin film 303 having a thickness of 0.5 to 3 μm epitaxially grown on a sapphire substrate of μm to 400 μm. A data line (bit line) 409 is formed above the n ⁺ source region 306 via a contact electrode (plug) 408. Further, a storage electrode 405, an insulating film 406, and a counter electrode (plate electrode) 407 are formed above the n ⁺ drain region 306 via a contact electrode 410. A portion between the n ⁺ source region 306 and the n ⁺ drain region 306 is a silicon film 303 serving as a channel region of the switching transistor. A gate electrode 30 of a switching transistor such as polysilicon is formed above the channel region 303 via a gate oxide film 304.
5 are formed. The gate electrode 305 is simultaneously DRA
It functions as the M word line. If the (1012) plane is selected as the sapphire substrate, a silicon (100) plane having good crystallinity grows on the sapphire substrate 100. The SOS-DRAM shown in FIG.
Since the surface roughness of No. 00 was measured by a probe method and smoothed so as to correspond to irregularities of 30 nm or less, the yield of cutting chips by a diamond cutter thereafter was extremely high. Therefore, the SOS-DRAM shown in FIG.
Has high latch-up resistance, small stray capacitance, high speed,
Low power consumption operation is possible. It is suitable for mass production because the yield of chip cutting is high. Further, there is no distortion to the channel region 303 due to the thin sapphire substrate, a low leak current, and excellent retention characteristics.

[0034]

As described above, in the semiconductor device according to the present invention, the polishing process of the sapphire substrate can be performed in a short time, so that the manufacturing process is greatly simplified and the production cost is reduced.

Since the sapphire substrate does not need to be particularly thin, it is mechanically stable, and there is no need to worry about the influence of stress, strain and the like. For this reason, the yield of the assembling process is high, and the sapphire substrate can be easily separated. Therefore, high performance such as high luminous efficiency and low leak current is guaranteed as a product, and the manufacturing yield is greatly improved.

[Brief description of the drawings]

FIG. 1 shows a gallium nitride (GaN) compound semiconductor blue light emitting diode (LE) according to a first embodiment of the present invention.
FIG. 4D is a cross-sectional view illustrating a layer structure of the semiconductor chip.

FIG. 2 is an explanatory diagram showing a method for manufacturing a blue LED according to the first embodiment of the present invention.

FIG. 3 is a blue LLED according to the first embodiment of the present invention.
It is a figure explaining the grinding method of.

FIG. 4 is a diagram showing a relationship between the yield of the blue LED and the transmittance of the sapphire substrate according to the first embodiment of the present invention.

FIG. 5 shows an SOS-DR according to a second embodiment of the present invention.
It is sectional drawing of AM.

FIG. 6 is a sectional view showing a layer structure of a semiconductor chip of a conventional blue LED.

FIG. 7 is a sectional view of a conventional SOS-DRAM.

[Explanation of symbols]

1, 2 semiconductor chip of gallium nitride (GaN) based compound semiconductor blue light emitting diode 11 glass substrate 12 cloth 13 polishing jig 14 wax 100 sapphire substrate 101 GaN-based n-type semiconductor buffer layer 102 GaN-based n-type semiconductor contact layer 103 GaN-based n-type semiconductor layer 104 GaN-based n-type semiconductor active layer 105 GaN-based p-type semiconductor layer 106 GaN-based p-type semiconductor contact layer 107, 108, 204, 205 electrode 303 channel region 304 gate oxide film 305 word line 306 n ⁺ source / Drain region 405 Storage electrode 406 Insulating film 407 Counter electrode (plate electrode) 408 Contact electrode (plug) 409 Data line (bit line)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification code FI H01L 27/108 (58) Fields investigated (Int.Cl. ⁶ , DB name) H01L 33/00 H01L 21/304

Claims (16)

(57) [Claims] 1. A sapphire substrate, a first conductivity type semiconductor single crystal layer formed on the sapphire substrate, and a second conductivity type provided on or inside the first conductivity type semiconductor single crystal layer. At least a semiconductor region of a mold type, and the surface roughness of the sapphire substrate is 10 nm by a probe method.
A semiconductor device having a surface roughness corresponding to the following irregularities. 2. The semiconductor device according to claim 1, wherein there are a plurality of semiconductor regions of the second conductivity type. 3. The semiconductor region of the second conductivity type is a source region and a drain region of a MOS transistor, and the first semiconductor single crystal layer between the source region and the drain region is a channel region of the MOS transistor. 3. The semiconductor device according to claim 2, wherein: 4. The sapphire substrate has a thickness of 260 μm to 4 μm.
2. The semiconductor device according to claim 1, wherein the thickness is 00 μm. 5. A sapphire substrate, a first cladding layer made of a first conductivity type compound semiconductor formed on the sapphire substrate, and a substantially intrinsic compound semiconductor formed on the cladding layer. At least a second cladding layer formed on the active layer and made of a compound semiconductor of a second conductivity type opposite to the first conductivity type, the surface of the sapphire substrate being roughened. The semiconductor device has a surface roughness corresponding to unevenness of 10 nm or less measured by a probe method. 6. The sapphire substrate has a thickness of 260 μm.
6. The semiconductor device according to claim 5, wherein: 7. The semiconductor device according to claim 5, further comprising a buffer layer made of a first conductivity type compound semiconductor between said sapphire substrate and said first conductivity type cladding layer. 8. The semiconductor device according to claim 5, wherein said sapphire substrate has a transmittance of 60% or more. 9. The semiconductor device according to claim 5, wherein each of the compound semiconductors constituting the first cladding layer, the active layer, and the second cladding layer is a group III-V compound semiconductor. 10. The semiconductor device according to claim 9, wherein the group III-V compound semiconductor is a gallium nitride-based compound semiconductor. 11. The gallium nitride-based compound semiconductor comprises I
n _x Al _y Ga _1-x- semiconductor device according to claim 10, characterized in that the _y N. 12. The value of each composition x and y of In _x Al _y Ga _1-xy N is 0 for the first cladding layer.
≦ X ≦ 0.3, 0.1 ≦ y ≦ 1, for the active layer, 0 ≦ x ≦ 0.6, 0 ≦ y ≦ 0.5, for the second cladding layer, 0 ≦ x ≦ 0.3, 0.1 ≦ y ≦ 1.
12. The semiconductor device according to claim 11, wherein the value is zero. 13. A method for manufacturing a semiconductor device, comprising at least the following steps. (A) a buffer layer made of a first conductivity type gallium nitride based semiconductor, a first cladding layer made of a first conductivity type gallium nitride based semiconductor, and an active layer made of a substantially intrinsic gallium nitride based semiconductor. Laminating a second cladding layer made of a gallium nitride based semiconductor of a second conductivity type opposite to the first conductivity type on a sapphire substrate. (B) The sapphire substrate has a transmittance of 60% or more. (C) a step of cutting the sapphire substrate and cutting it into a plurality of chips 14. The method of manufacturing a semiconductor device according to claim 13, wherein the polishing is performed so that the polished thickness of the sapphire substrate becomes 260 μm or more. 15. The method of manufacturing a semiconductor device according to claim 13, wherein the polishing is performed until the surface roughness of the sapphire substrate becomes equal to or less than 10 nm when measured by a probe method. 16. The gallium nitride-based semiconductor is In _x A
l _y Ga _1-xy N, and the values of the compositions x and y are 0 ≦ X ≦ 0.5 and 0.5 ≦ y ≦
1. For the first cladding layer, 0 ≦ x ≦ 0.
3, 0.1 ≦ y ≦ 1, 0 ≦ x ≦ for the active layer
14. The method according to claim 13, wherein 0.6, 0≤y≤0.5, and 0≤x≤0.3 and 0.1≤y≤1.0 for the second cladding layer. A method for manufacturing a semiconductor device.