JPS6016732A - Receiver - Google Patents
ReceiverInfo
- Publication number
- JPS6016732A JPS6016732A JP59131371A JP13137184A JPS6016732A JP S6016732 A JPS6016732 A JP S6016732A JP 59131371 A JP59131371 A JP 59131371A JP 13137184 A JP13137184 A JP 13137184A JP S6016732 A JPS6016732 A JP S6016732A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- power supply
- control circuit
- current consumption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0225—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal
- H04W52/0245—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal according to signal strength
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Noise Elimination (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はディジタル信号の変復調回路を内蔵した受信機
に関するもので消費電流を少くすることを目的とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiver incorporating a digital signal modulation/demodulation circuit, and an object of the present invention is to reduce current consumption.
従来、この種の装置は例えは第１図に示すような構成が
とられていた。受信信号入力端子１に供給された受信信
号は受信増幅回路２により、増幅および周波数変換され
、復調回路３により、基底帯信号に復調されてディジタ
ル信号復調回路４、雑音増幅回路Ｔに与えられる。ディ
ジタル信号復調回路４は基底化信号から、ティンタル信
シシの原信号を復調し、Ｄ 、−’ Ａ 変換回路５で
音声γｔのアナロク信号に変換し、信は増幅回路６て増
幅した後、受信信号出力端子１０に受信信号を出力する
。また、雑音増幅回路７は基底・１１：以外の広帯域を
増幅し、信号制御回路８に雑音電圧信号などを険波し。Conventionally, this type of device has had a configuration as shown in FIG. 1, for example. The reception signal supplied to the reception signal input terminal 1 is amplified and frequency-converted by the reception amplifier circuit 2, demodulated to a baseband signal by the demodulation circuit 3, and given to the digital signal demodulation circuit 4 and the noise amplifier circuit T. The digital signal demodulation circuit 4 demodulates the original signal of the tintal signal from the basis signal, converts it into an analog signal of audio γt in the D, -'A conversion circuit 5, and amplifies the signal in the amplifier circuit 6 before receiving it. The received signal is output to the signal output terminal 10. Further, the noise amplification circuit 7 amplifies a wide band other than the base and 11:, and sends a noise voltage signal etc. to the signal control circuit 8.
て供給する。信号制御回路８ては信号検出レベルをＦｉ
Ｊ変抵抗器９により設定し、雑音増幅回路７からの雑音
電圧の大きさなどにより、信号増幅回路６の電源などを
制御し、受信信号出力端子１０・Ｘの受信信号を切断す
るなどの回路構成がとられていた。しかしこの回路構成
では受信電界強度の強さに関係なく変復調回路が常時動
作してしまい、待ち受け時の／ｌＩｌ費電流が大きいと
いう欠点があった。supply. The signal control circuit 8 sets the signal detection level to Fi.
A circuit that is set by the J resistor 9, controls the power supply of the signal amplification circuit 6, etc. according to the magnitude of the noise voltage from the noise amplification circuit 7, and disconnects the received signal of the received signal output terminal 10. It was structured. However, this circuit configuration has the disadvantage that the modulation/demodulation circuit is always in operation regardless of the strength of the received electric field, and that the current consumption during standby is large.
本発明はこのような欠点を除去したもので、以下その一
実施例を第２図を用いて詳細に説明する。The present invention eliminates these drawbacks, and one embodiment thereof will be described in detail below with reference to FIG. 2.
第２図の実施例は第１図の回路に電源制御回路１１を新
たに設けたものである。すなわち、電６；（制御回路１
１は信号制御回路８の出力を受けて変復調回路４および
Ｄ／Ａ変換回路５の電源を制頒する。これにより、受信
電界強度がトかったとき受信機は９″ｊ“ち受け状態と
なり、変復調回路４およびＤ／Ａ変挽変格回路６源が断
となるため、回路の消費電流を非常に低く抑えることが
できる。In the embodiment shown in FIG. 2, a power supply control circuit 11 is newly added to the circuit shown in FIG. That is, power 6; (control circuit 1
1 receives the output of the signal control circuit 8 and controls the power supply of the modulation/demodulation circuit 4 and the D/A conversion circuit 5. As a result, when the received electric field strength is high, the receiver enters the 9"j" receiving state, and the modulation/demodulation circuit 4 and D/A variation circuit 6 are cut off, so the current consumption of the circuit can be kept very low. It can be suppressed.
また、変復調回路４やＤ／Ａ変換回路６はＣＭＯＳ な
どの静的消費電流の少ない素子で構成されることが多い
ため、電源制御回路１１の代わりに変復調回路４やＤ／
Ａ変換回路５に供給されるクロック信号を停止させるよ
うな論理回路を設けても同様の効果があることは明らか
である。Furthermore, since the modulation/demodulation circuit 4 and the D/A conversion circuit 6 are often configured with elements such as CMOS that have low static current consumption, the modulation/demodulation circuit 4 and the D/A conversion circuit 6 can be used instead of the power supply control circuit 11.
It is clear that the same effect can be obtained by providing a logic circuit that stops the clock signal supplied to the A conversion circuit 5.
受信電界強度が下がった時、受信信号電流の大きさによ
り、受信信号出力を制御する回路方式においても、前記
と同様の回路構成をとり、消費電流を低く抑えることが
できるのは明らかであるので、その説明は省略する。It is clear that when the received electric field strength decreases, the current consumption can be kept low by using the same circuit configuration as described above even in a circuit system that controls the received signal output depending on the magnitude of the received signal current. , the explanation thereof will be omitted.
以上説明したように、本発明によれは受信電界強度の弱
い待ち受け状態での消費電流を非常に少なく抑えること
ができ、その工業的価値は大てあAs explained above, according to the present invention, the current consumption in the standby state where the receiving field strength is weak can be suppressed to a very low level, and its industrial value is largely
第１図は従来の受信機の回路構成の一例を示すブロック
図、第２図は本発明の一実施例における受信機の回路構
成を示すプロ・ツク図である。
２・・・ 受信増幅回路、３ 復調回路、４ ・ディジ
クル信号復調回路、ｓ −Ｄ ／ Ａ変換回路、６・・
信号増幅回路、７・・ 雑音増幅回路、８・・信号制
御回路、９ 可変抵抗器、１１ 電源制御回路。FIG. 1 is a block diagram showing an example of the circuit configuration of a conventional receiver, and FIG. 2 is a block diagram showing the circuit configuration of a receiver in an embodiment of the present invention. 2... Reception amplifier circuit, 3 Demodulation circuit, 4 - Digital signal demodulation circuit, s-D/A conversion circuit, 6...
Signal amplification circuit, 7... Noise amplification circuit, 8... Signal control circuit, 9 Variable resistor, 11 Power supply control circuit.
Claims (2)
信号電流の大きさを判別し、」二記基底帯信号を処理す
る処理系の電源あるいはクロック信号を制御する手段を
設けた受信機。(1) Receiver equipped with means for determining the magnitude of the baseband signal of the received signal or the received signal current and controlling the power supply or clock signal of the processing system that processes the baseband signal. .
である特許請求の範囲第１項記載の受信機。(2) The receiver according to claim 1, wherein the processing system is a digital signal demodulation circuit and a D/A conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59131371A JPS6016732A (en) | 1984-06-26 | 1984-06-26 | Receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59131371A JPS6016732A (en) | 1984-06-26 | 1984-06-26 | Receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6016732A true JPS6016732A (en) | 1985-01-28 |
Family
ID=15056370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59131371A Pending JPS6016732A (en) | 1984-06-26 | 1984-06-26 | Receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6016732A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0255048A2 (en) * | 1986-07-26 | 1988-02-03 | Nec Corporation | Portable radio telephone having power saver |
| JPS63156433A (en) * | 1986-12-19 | 1988-06-29 | Sanyo Electric Co Ltd | Radio receiver |
| JPS63156432A (en) * | 1986-12-19 | 1988-06-29 | Sanyo Electric Co Ltd | Radio receiver |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS562002A (en) * | 1979-06-18 | 1981-01-10 | Nec Corp | Control circuit |
-
1984
- 1984-06-26 JP JP59131371A patent/JPS6016732A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS562002A (en) * | 1979-06-18 | 1981-01-10 | Nec Corp | Control circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0255048A2 (en) * | 1986-07-26 | 1988-02-03 | Nec Corporation | Portable radio telephone having power saver |
| JPS63156433A (en) * | 1986-12-19 | 1988-06-29 | Sanyo Electric Co Ltd | Radio receiver |
| JPS63156432A (en) * | 1986-12-19 | 1988-06-29 | Sanyo Electric Co Ltd | Radio receiver |
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