JPS60165628A - Power circuit of camera - Google Patents

Abstract

PURPOSE:To save the power consumption of a storage holding power source connected to a semiconductor memory circuit by providing a current cutoff member between the storage holding power source and a control circuit. CONSTITUTION:A main power source 11 supplies electric power to a driving circuit 15 and also supplies electric power to the semiconductor circuit 16 through a diode 13 simultaneously with a power switch 23 on. In this state, the storage holding power source 12 supplies no power to the circuit 16; and a diode 13 cuts off electric power supply from the power source 12 to the circuit 15 and a diode 14 prevents the power source 11 from being consumed through the flow passage of the current source 12. When the switch 23 is open, on the other hand, the circuit 16 is powered on by the power source 12 through the diode 14, but any electric power is not supplied because of the diode 13. The circuit 16 is therefore in operation to hold storage contents.

Description

[Detailed Description of the Invention] Field of Industrial Application] The present invention relates to a power supply circuit for an exposure control circuit of a camera and other electronic control circuits, and more specifically, the present invention relates to a power supply circuit for an exposure control circuit of a camera and other electronic control circuits. Each parameter (for example, shutter speed, aperture value, etc.) that defines the camera control operation is electronically set, and furthermore, such exposure control information is stored in a semiconductor memory circuit that electrically stores information on the camera. Therefore, a method of storing all data in one circuit was adopted. but,
In this method, when the power supply is stopped, the circuit that stores this information no longer operates, and when the power is supplied again, the previously stored information has disappeared, so these There was the hassle of having to reset the information. Also, in consideration of the risk of the power supply to the memory circuit being interrupted (↑11), a configuration in which a special power source is added to the memory circuit can be considered, but it is best to simply add a special power source to the memory circuit ('j In this case, each power supply is consumed simultaneously for all the control circuits in the camera device, which deviates from the original purpose of supplying power to the memory circuit. The purpose of the present invention is to provide a power supply circuit in which both power supplies are large to some extent and the power is consumed only by the memory circuit.

Furthermore, the present invention supplies power from the memory retention power supply only when the power switch is turned off, that is, when power is not supplied to the semiconductor metal circuit from the main power supply, thereby reducing power consumption of the memory retention power supply. The purpose is to provide a power supply circuit that saves money.

[Summary of the Invention] A camera power supply circuit according to the present invention includes a semiconductor memory circuit that electrically stores and holds information necessary for determining exposure control operations of the camera, and a semiconductor memory circuit that reads out the information stored in the semiconductor memory circuit. In a camera equipped with a control circuit that performs an exposure control operation, a main power supply that supplies power to the control circuit and the semiconductor memory circuit when the switch member is open, and a rectifier member that supplies power to the semiconductor memory circuit. In step I), the memory holding power source is connected to the lower conductor memory circuit, and a current blocking member prevents current from flowing from the memory holding power source to the control circuit.

[Description of Embodiments] The present invention will be described below with reference to embodiments shown in the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a power supply circuit according to the present invention. In the following explanation, in order to facilitate understanding, a shutter curtain control circuit of a four-wheel-brain shutter will be explained as an example of an electronic control device of a camera device. The anode (+) of the main power supply 11 is connected to one end of the magnet 1 17 via the power switch 23 , the power supply terminal of the drive circuit 15 of the magnet 17 , and the anode of the diode 13 . The ground G is connected to the cathode (-) of the main power supply 11, the ground terminal G1 of the magnet drive circuit 15, the ground terminal G2 of the semiconductor metal circuit 1G, and the cathode (-) of the memory retention power supply 12.

The anode (G) of the memory storage power supply 12 is connected to the second diode 1.
4, and the cathode of the second diode 14, the cathode of the first diode 13, etc., and the power supply terminal v2 of the semiconductor memory circuit 16 are connected to each other at a connection point 22. The main power supply 11 is for the magnet drive circuit 15, and the memory retention power supply 12 is for the semiconductor memory circuit 16.
For example, a lithium battery is used. The magnet drive circuit 15 and the semiconductor memory circuit 16 transmit and receive signals to and from the phase η via a plurality of data reading signal lines 18 and one data writing signal line 19 (multiple lines may be used if necessary). 4 - Connected to The switch 20 is a normally closed switch that is opened in synchronization with the movement of the front shutter curtain, and the mechanism for opening the switch is well known and will not be described here. The bush switch 21 is used to electrically store information necessary for determining the exposure control operation of the camera device in the semiconductor memory circuit 16 by turning the button switch 0N10FF.

The switch 20 and the bushing switch 21 are connected between the magnet drive circuit 15 and the ground G.

Next, the operation of the first illustrated circuit in relation to camera operation will be briefly explained. When starting to use the camera, the memory circuit 16
It is necessary to store exposure control information (for example, shutter speed information) in the
By flipping the FF, the information is transferred to the memory circuit 16 via the information write signal line 19.The drive circuit 15 reads the data from the semiconductor memory circuit 16 via the read signal line 18, It is possible to know the parameters for determining the exposure control operation of the apparatus, that is, the timing of closing the rear shutter curtain.

When the shutter release operation is reversed, the front shutter runs and the switch 20 becomes open, and the drive circuit 15 responds to this by exciting the -C magnet to engage the rear shutter 11-, as will be described later. Thereafter, the drive circuit 15 de-energizes the magnets j~17 after a period of time determined based on the exposure determination parameters including information stored in the semiconductor memory circuit 16, and causes the rear part to travel.

This completes the exposure to film. Although not particularly shown in FIG. 1, a signal may be sent from the drive circuit 15 to a circuit that indicates the execution or completion of the shutter operation.

Next, we will explain the circuit operation focusing on the use of two power sources.
-ru. The main power supply 11 supplies power to the drive circuit 15 when the power switch 23 is in the open state, and can also supply power to the semiconductor memory circuit 16 via the diode 13 at the same time. The power switch 23 may be closed in synchronization with the movement of the release operating member of the camera device, and the power switch 23 may be closed in synchronization with the movement of the release operating member of the camera device. It may be closed separately by the user or by another member. When the power switch 23 is in an open state, power is supplied to the semiconductor memory circuit 16 from the main power supply 11, and the memory retention power supply 12 does not supply power to the memory circuit 16. Further, the diode 13 blocks power supply from the memory retention power supply 12 to the drive circuit 15.

The diode 14 prevents the main power supply 11 from being consumed by the flow path of the storage power supply 12.

When the Barry switch 23 is open, the semiconductor memory circuit 16 is connected to the diode 14 from the storage power supply 12.
However, since the diode 13 is connected in the opposite direction, no power is supplied to the drive circuit 15. Therefore, even if the power switch 13 is in an open state, only the semiconductor memory circuit 16 remains in an operating state and its memory can be retained.

Since no current flows from the memory holding power supply 12 to the drive circuit 15, the power supply 12 is used exclusively for the semiconductor memory circuit 16, which is very efficient in use. If a CMO8 circuit configuration is used for the semiconductor memory circuit 16, the current consumption can be significantly reduced, and the storage power supply 7-12 can also have a small capacity, allowing a small battery to be used. This is a great advantage for camera devices that are always carried with you.

Once the information necessary for camera exposure control is set and stored in the memory circuit 16, this information will be stored even when the camera's power switch 23 is in the open state to prevent consumption of the main power source 11. Therefore, you will need to set the settings again the next time you shoot.
There is no need to perform memorization work, and the operability of the camera device is improved.

Next, with reference to FIGS. 2 to 4, information necessary to determine the exposure control operation of the camera will be explained using a specific example. FIG. 2 specifically shows the inside of the drive circuit 15 and semiconductor memory circuit 16 in FIG. 1.

In the drive circuit 15, one end of the switch 10 is connected to the positive power supply line via a pull-up resistor 25, and
It is connected to the input of the inversion circuit 31 and the input of the AND circuit 26. Another input of the AND circuit 26 is connected to the output of the oscillator 24. The output of the AND circuit 26 is sent to the inverting circuit 2.
The output terminal Q of the T flip-flop 1:1 is connected to the clock pulse input terminal T of the T flip-flop 70 through the pin 1.
0-flip-flop E1.11.・・・・・・
...FN is connected. Each T flip 70 knobs F
1. F2. ......Each output terminal Q of FN is connected to each AND circuit A provided correspondingly.1. A2.・・・・・・
・Connect to one of the inputs of AN, and connect each logic circuit AI, Δ
2. ...Another input of AN is each output terminal D1 of the decoder 32. D2. ...Connect to each DN. A signal line 18 is connected to the input terminal of the decoder 22 .

Each AND circuit A I, A 2. ......The output terminals of the 8N are all connected to the input of a single AND circuit 28, and the output terminal of the AND circuit 28 is connected to the terminal (S) of the RS flip 70 tube 30. ). The output terminal of the RS laritub flop 30 is connected to the positive power supply line via the magnet 11. Said T flip [] knob F
1. 2. . . . Each reset terminal R of FN and the reset terminal R of the RS flip-flop 30 (Y,
The output terminal of the inverting circuit 31 is connected.

One end of the bushing switch 21 is connected to the write line 19 and also connected to the anode of the power supply via a pull-up resistor 29.

In the semiconductor memory circuit 16, the write signal rA19 is connected to the clock input terminal of the flip-flop F01. terminal 10
Connect to. The output Q of the T-flip 70 block FO2 is connected to the clock input terminal of the T-flip-flop FO3, and thereafter, the required number of flip-flops are connected in series. Each output terminal Q of each flip 70 tube FOI, FO2, FO3 is connected to the input terminal of the decoder 32 of the drive circuit 15 via the read signal line 18. It is assumed that each of the flip 70 knobs FO1, F02, and FO3 responds to a fall in the potential of the clock input terminal.

FIG. 3 shows that the T flip-flop FO of the semiconductor memory circuit 16 is turned on by the 0N10FF operation of the bushing switch 21.
This shows how data is set in 1, FO2, and FO3. FIG. 3 shows the change in the signal from the semiconductor memory circuit 16 due to the movement of the bush switch 21, with time t plotted on the horizontal axis. The top row is the bush switch 21
The following steps show the operation of T-flip 70 tube FOI
, indicates the output Q of FO2 and FO3. mouth, t2, t3,
t4 indicates the time point when the bushing switch 21 is turned on.

When the bush switch 21 is turned ON and OFF sequentially, the potential of the signal @A19 drops to -L, which is applied to the clock input terminal of the T-flip 70 bush FO1. ■Flip-flop F01. F02 and FO3 constitute a binary counter as a whole, and the output of the T flip-flops [01 and 02°FO3 changes according to the number of ON and OFF operations of the bush switch 21.

Next, with reference to FIG. 4, the operation of the drive circuit illustrated in FIG. 2 will be described. The horizontal axis indicates time. The part between 11 and t2 is shortened by omitting a part. These 10, 11, t2 are
It has nothing to do with rO to 1-4 in FIG. 50 represents the output of the oscillator 24, 52 represents the potential change accompanying the operation of the switch 20, 54 represents the output of the inverter 27, and 54, 56, 58 represent the respective T flip-flops F11-1, F2 . . . . "Represents the output of N. 62 represents the Nth output of the decoder 32, 64 represents the output of the AND circuit ΔN, 66 represents the output of the AND circuit 28, and 68 represents the output of the AND circuit 28. Indicates the output Q of the RS flip-flop 30,
70 indicates ON (excitation state) and OFF of magnet 17
(released state). The output of the decoder 32,
For example, in DN62, there is no need to limit the state before t1, and this is indicated by the ITW line in the figure.

In the example shown in the fourth figure, the T flip 70 knobs F01 to FO3
The decoder 32 decodes the data set to
Suppose that the Sth output is selected. This decoding operation is performed to
has been executed before. The switch 20 is opened in synchronization with the start of running of the front curtain of the shutter device (time t1),
As a result, the output of the oscillator 24 is input to the clock input terminal of the T-flip 70 tube F1 via the AND circuit 26 and the inverter 27.

In addition, each T flip 70 knob F1. F2...F
N is such that when the switch 20 is in the open state, a "high" signal is applied to its reset terminal R by the reverse rotation 21.
2- is set and reset. At the same time as the front curtain starts running, a clock signal is applied to the clock input terminal, and the reset is canceled by a "low" signal to each reset terminal, so the T flip-flops Fl, F
2. ...The entire FN starts operating as a counter. Before t1, RS flip-flop 30 [
A "high" signal is also applied to the terminals 1 to 2, and the output of terminal A is low, energizing the magnet 11 and prohibiting the trailing curtain from running. Note that each flip-flop F1. F2
．． ...FN responds to the falling edge of the clock terminal. When the ON output selected by the decoder 32 and the output of the Nth T flip-flop match (time t2),
The AND circuit AN transmits a set signal to the terminal S to the cell 1 of the RS flip-flop 30 via the OR circuit 28. Then, the output terminal Q becomes "high", the magnet 11 becomes de-energized, and the trailing curtain starts running.

A plurality of output lines D1. of the decoder 3. D2.・・・・・・
・You can arbitrarily set the time from the start of running of the leading curtain to the start of running of the trailing curtain depending on which output line of the DN the signal is output to. This means that the 7 lip flops FOI in memory circuit 16
, means that the shutter time can be arbitrarily controlled by the setting data of FO2 and FO3.

Table 1 below is classified into No. 61 to No. 34 according to the presence or absence of the main power source 10 and memory retention power source 12 in FIG.
They are ICs showing the operating states of the semiconductor memory circuit 16 and the drive circuit 15, respectively.

Table 1 No, I No, 2 No, 3 No, 4 Main power supply 11
Right No Yes No holding voltage a12 Yes Yes No Memoryless circuit 16 Operation Operation Operation - Drive circuit 15
Operation - Operation - 1: In the case of non-operation and N001, the memory holding power supply 12 and the main power supply 10 supply power to the memory circuit 16 and the drive circuit 15, respectively, so both circuits can operate. In the case of No. 2, the main power source 10 is exhausted or removed, or the power switch 23 is opened. The memory circuit 16 can operate by receiving power from the storage power supply 12. That is, the memory circuit 16 can retain its contents. In the case of N003, 1, even though there is no memory retention power supply 12, as long as the power switch 23 is in the open state, power is supplied to the memory circuit 16 from the main power supply 11 via the diode 13. ,
Both the drive circuit 15 and the machining circuit 16 are operable, and proper image transfer can be performed. N014 is a case where both power supplies are not available, and it is natural that the circuit does not operate.

In the present invention, even in the case of N013, information for limiting the exposure control operation of the camera can be electrically stored and retained using only the power supply used for the control circuit that performs the main exposure operation of the semiconductor device. Furthermore, by using a power supply for memory retention, the information can be electrically stored regardless of whether the power switch is open or open. Since the memory storage power supply does not supply power to the control circuit, the power supply efficiency is increased and a relatively small capacity battery can be used. Furthermore, since the memory retention power supply supplies power to the memory circuit only when power is not supplied to the memory circuit from the main power supply, the memory retention power supply may have a small capacity in this respect as well. In practice, the warranty period of the camera, for example 10 years or more,
There is no need for replacement.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. Second
The figure shows a specific example of the inside of the drive circuit 15 and semiconductor memory circuit 16 in FIG. 1. Figure 3 shows
By operating the bushico switch 21, the semiconductor memory circuit 1
6 is a diagram illustrating a signal change when data is set to 6. FIG. FIG. 4 shows the drive circuit 15 according to the exposure operation of the camera.
The horizontal axis shows signal changes in each part over time. 11... Main power supply 12... Memory retention power supply 13.
... Diode 14... Diode 15... Drive circuit 16... Semiconductor 16 integrated memory circuit 17... Magnet 18... Read signal line 19... Occupied signal line 20... Switch 2
1...Pushy switch 22...Connection point 32.
... Power switch G... Ground 24... Oscillator 25... Pull-up resistor 26... AND circuit 21... Inverting circuit 28... AND circuit 29...
・Pull-up resistor 30...RS flip-flop
31... Inverting circuit Fl, F2~NF... T flip-flop FOl, FO2, FO3... T flip-flop △1. A2 Heh △N...Logic product circuit patent applicant Asahi Optical T-gyo Co., Ltd.

Claims (1)

[Scope of Claims] (1) A semiconductor memory circuit that electrically stores and holds information necessary for determining exposure control operations of a camera, and a control that reads out the information stored in the semiconductor memory circuit and performs exposure control operations. In a camera equipped with a circuit, a main power supply that supplies power to the control circuit and the semiconductor memory circuit when the switching member is closed, and a rectifier that supplies power to the semiconductor memory circuit through the main power supply that supplies power to the semiconductor memory circuit. A camera power supply circuit characterized by comprising a memory retention power source connected to a memory circuit, and a current blocking member that blocks current from flowing from the memory retention power source to the control circuit. (2) A camera according to claim 1 or 2, characterized in that the semiconductor memory circuit is of 0MO8 type. (4) The control circuit is a shutter drive circuit, and the semiconductor memory circuit holds shutter one-time information.
) A power supply circuit for the camera according to any one of the above items.