JPS60165114A - Noncyclic digital lattice filter - Google Patents

Abstract

PURPOSE:To obtain a sufficient filter characteristic even with a short word length of coefficient by adding the 1st or the 2nd output to a signal giving at least one sample period delay to the 2nd or the 1st output signal of a lattice type circuit block and outputting the result as a filter output signal. CONSTITUTION:Multipliers 251-254 and adders 271, 272 of a lattice type circuit block of the 1st stage generate two signals [K11(1).X1(1)+K21(1).X2(1)] and [K12(1).X1(2)+K22(1).X2(1)] based on signals X1(1) and X2(2). An output signal of the lattice type circuit block 211 of the 1st stage is inputted respectively to input terminals 225, 226 of the lattice type circuit block 212 of the 2nd stage and the output signal is outputted respectively to output terminals 227, 228. The processing is conducted sequentially similarly. This filter characteristic depends on values of coefficients K11(i), K22(i), K12(i) and K21(i) of the multipliers and an excellent characteristic is obtained even when the word length of the coefficients is short.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to an acyclic digital filter that processes a double-encoded digital signal.

(Prior art) The first acyclic digital filter with a conventional direct configuration
As shown in the figure.

In FIG. 1, reference numbers 110-1 to 110-(N-
1) is a delay element that provides a delay of l sample periods. The input signal from the input terminal lot is sent to the delay element 111-1.
The 11th order is transmitted to 15. Input signal and each delay element c
Multipliers 120-0 to 120-1 add coefficients aO""-'aN-1 to the output signals of tio-1-110 (N-1), respectively.
20-(N-1), adder 130-1-1
30-(N-1), a filter output is obtained at the output terminal 102 by sequentially increasing the trough multiplier output r and increasing the trough multiplier output r.

Here, the coefficient Uao''-aN-1 is a constant that determines the filter characteristic sound, and is expressed by a double code with a finite word length. Generally speaking, when the coefficient word length is shortened, the filter % characteristic is lower than the design value. to degrade.

Therefore, it is necessary to express the coefficient ao = as-1k using a relatively long word length (10 to 16 bits), but since the hardware size of the multiplier is proportional to the coefficient word length, this results in a reduction in the filter hardware size. - Conventional circuits have the disadvantage of increasing the size of the circuit.

(Objective of the Invention) The object of the present invention is to provide a filter that eliminates the above-mentioned drawbacks and provides sufficient filter characteristics even with a short coefficient word length. It is about providing.

(Structure of the Invention) The filter of the present invention uses two different input signals Xi(ri and K2(i) (i=1, 2..., P
: P is a positive integer) and the coefficient K 11 (i) and 21
('), and multiply K11(su・Xl(su+) by 21(i
)・Xz(i) as the first output day number Y1(')
as well as the input signal X1 (RI and K
2(ri) multiplies the coefficient by 12(ri and Kzz('J), generates a signal that becomes 22(su・K2(ri), delays this P lattice circuit blocks outputting the output signal Y2 (2) and the j-th (j=i, 2°, . . . , P-1)
The output signals Y1(ri and Y2(s'fr) of the lattice m circuit block in the th stage, the input signals X1(j+1) and K2(j+1) of the lattice type circuit block in the j+xth stage
) and transmitting means for transmitting the filter input signal to the 1!1-straddling second stage of the lattice circuit block in the first stage.
input means for supplying the filter input signal as the input signal of the filter input signal and delaying the filter input signal by at least l sample period and supplying the delayed filter input signal as the second or first input signal of the lattice circuit block of the first stage; Ail description of lattice type circuit block No. 2-1. or a signal obtained by delaying the first output signal by at least l sample period and the first or second output signal of the lattice circuit block in the final stage, and outputs the addition result as a filter output signal. and output means.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows a circuit configuration showing one embodiment of the present invention. A signal input from the input terminal 201 is applied to the second input terminal 222 via the first input terminal 221 of the first stage lattice circuit block 211 and the delay element 241 which provides a delay of l sample periods. It will be done. Each of the first stage lattice circuit blocks 211 has two input terminals 22.
Signal X given to 1 and 222 1(1) and x
2tt+, two signals (Kotl
l・X 1fil 10 to 21t11・X2tt+) and (K12t11・X1t21+ to 22tll・x2+
11) 'e, occurs. The former is the output signal Y 1 fi
The latter is outputted to the first output terminal 223 of the M1th stage lattice circuit block 211 as Y 2 tit, and the latter is output to the second output terminal 224 via the delay element 242 as Y
is output as

The output signals Y 1 fil and Y2fll of the first stage lattice mtg circuit block 211 are input to the second stage lattice type circuit block 212 as input signals X 1 (21 and X 2121 to input terminals 225 and 226, respectively When the input is changed, the output signal Y 1 is obtained by similar processing.
Output terminals 227 and 22 on f21 and Y2+21'
8 respectively. Similarly, the J() = t
r 2 +...

P−1)-th stage block output signal Y1(j) and Yz(j)k j+1th stage block input signal X1(
j+1) and Xz(j+1), and the processing is performed sequentially. Output signal Y 1 (P) obtained at the it output terminal 231 of the final second stage lattice circuit block 213
and the output signal Y2 (P
) and a signal consecutively fired for P sample periods by the delay element 245 in an adder 277, a filter output is obtained at the output terminal 202.

In addition, in Figure 2, the numbers 255, 257゜25
8, 256, 259, 261, 262 and 2
60 are each related (i'1Kix t21 r K12
t211 K211211 K2z121 rKltc
PJ r l<1zcPJ, Kzl(P)oL HiKzz(Pi 71m and the corresponding multiplier, the same numbers 273 to 276 are adders, the same numbers 243 and 24
4 is l'! A delay element t which provides a delay g2 of ll-pulle period is shown, respectively.

In the filter of the present invention, the filter characteristic is the multiplier coefficient Kn
(L) s K22 (suy K12(') and ni 21
It is determined by the value of (i==1.2...,P), and good characteristics can be obtained even when the coefficient length is short.

FIG. 3 is a diagram showing a comparison of loss characteristics between a conventional configuration with a short coefficient word length (l bits for code, 6 bits for mantissa) and the configuration of the present invention.
Design value) 301, whereas the conventional configuration has a characteristic of 302! However, the stopband reduction amount deteriorated by 19 dB. On the other hand, in the configuration of the present invention, as shown in %Note 303, there is no deterioration of 6 dBl.

Therefore, in order to obtain the same filter characteristics, the configuration of the present invention requires a shorter coefficient word length than the conventional configuration.

The hardware scale can be lowered.

Next, the coefficient b K11 of the multiplier used in the present invention (S, ni 2
We will explain the symmetry between 2(S+ and 12(S), K2t(L).

In the conventional configuration, the transfer function H(z) of the filter is expressed by the multiplier coefficient ai (L-0, L, .
ω≦2π (ω is the angular frequency).

In the case of a linear phase acyclic filter in which the group delay time % property has a constant value regardless of the number of filters, in the conventional configuration, the coefficient a
The following symmetry (N or (B)) holds between ;

N-odd or to=odd (N-1)=ON=odd This relationship, in an uninvented configuration, applies to the coefficients 11(i)
.

Between K22(sl K12(') and K21(ri), corresponding to the above (N and (B)), the following (A
') and (B') can be realized by providing symmetry.

Buddha') K11 (su = 22 (su + klz (j) = 2t (i) i = x, z, ..., P (H') K11 (') = 22 (su + K12 (su) =
21(i = 1,2,...,P-1 and Kxt(1)) = K22(p), K12(hull = K22(11)). In a smear Φ Tesmear filter and a filter in which the time characteristic τ (ω) satisfies τ (ω) + τ (π - ω) = -, the coefficient a7 in the conventional configuration has the following relationship: (N is the number).

and' 4 This relationship is expressed by the coefficient Kn(L) in the configuration of the present invention.
+ K22(su+ni12(sr Kzi(tl) can be achieved by having the following symmetry.

K11(S=K22(S1K12(S=Ni21)
i-odd number 1□(su = K22(su+ 12(su=-21(L)) All configuration examples of the lattice type circuit blocks used are shown, and each has the following symmetry.

The same figure (in case of al: R1]
(S=Kb gift of the same figure (b) @-: ni 11 (L+= K22(shun-Ka, ni 12(li-k)
2t(LeeKbSame figure(C1: Kn (i)−ks+z(s=l(a l K12(
S=21(S=Kb) In the case of (d) in the same figure: kn(L)-, l'z2(S=Ka+1(+2(Le-
21 (Lee Kb) In the same figures (a) to (d), reference numerals 4t36, 407, 426°446, 466 and 467 represent the relationship between iKa and the input signal and the t-th power of the ride 4.
The same numbers 427 and 447 are multipliers that multiply the input signal by the coefficient -Ka, and the same numbers 408, 409, 429,
448, 449 and 468 are the input signals for multiplying the coefficient Kb and the input signal, and the same numbers 428 and 469 are the coefficients -
1) and a multiplier that multiplies the input signal by t, the same number 410,
411,430,431゜450.451,470 and 471 are additions, instruments, same numbers 405, 425, 44
5 and 465 are delay elements that delay the input signal sound by one sample period, and the same numbers 401, 402, 421, 42
2,441,442,461 and 426 are input terminals,
Same number 403.404.423.

424, 443, 444, 463 and 464 indicate output terminals, respectively.

(Effects of the Invention) As described above, the present invention has the effect that even when the length of the coefficient is short, it is possible to realize a filter having better characteristics than the conventional configuration, and the hardware scale can be reduced to t1. .

In addition, in the case of a phase acyclic filter or a complementary group delay time filter, it is necessary to have symmetry r between the coefficients.
Realization @ru.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional acyclic digital filter, and Fig. 2 is an embodiment of the present invention. A circuit configuration diagram shown,
Figure 3 is a diagram showing a comparison of loss characteristics, and Figures 4 (a) -
(d) is a diagram showing a complete example of the configuration of a lattice type circuit block in which coefficients have a symmetrical relationship in the present invention. In the figure, 101...filter input i child, 1
02...Filter output terminal, 1to-t~11
0-(N-1)--Delay element, 120-0 to 1
20-(N-1) ・-----Next 1i41 Rm, 1
30-1-130-(N-1)...Adder, 2
01...Filter input terminal, 2o2...
・Filter output terminal, 211-213... Lattice type circuit block, 221, 222, 225, 226, 2
29. 230... Lattice type circuit block input terminal, 22
3゜224.227,228,231,232...
・・Lattice type circuit block output terminal, 241 to 245・・
... Delay element, 251-262... Multiplier, 271-277... Adder, 401, 402
,421,422,441,442,461゜462・
... Lattice type circuit block input terminal, 403°40
4.423,424,443,444,463,464
...... Lattice type circuit block output terminal, 405
, 425 , 445 . 465...Delay element, 406-409, 42
6~429°446~449, 466~469...
...multiplier, 410. 411.430,431,450,451,470,4
71...Adder. , 2 Knee... 4θ5 415 Ward 4

Claims (1)

[Claims] (11) Two different input signals X1(ri and K2(j=t, z, ..., FDP is a positive integer) Ktl(
i). ri and 22(rito) <-1z(su・Xl(su+ni 22(su・Xz(i))), and this (Q
The second output signal Y 2 (P lattice circuit blocks output as l and the jth (j=l, l, ..., P-1 ) output signal Yl (l and YzU) of the lattice circuit block in the
The input signal X1 (
transmitting means for supplying the filter input signal as the first or second input signal of the lattice circuit block of the first stage; input means for supplying the second or first input signal to the first stage of the lattice circuit block with a delay of at least lv one cycle;
A signal obtained by delaying the second or first output signal of the lattice-type circuit block of the final stage by at least l sample period and the second or first output signal of the lattice-type circuit block of the final stage
An acyclic digital lattice filter characterized in that C comprises an output means for adding the second output signal and outputting the addition result as a total filter output signal. (21 said coefficient Kn('l r K22(il, K
12(Ll, Kzt(tl, (a) Klx(i
)=Kzz(sr Klz(tl=Kzx country, (b)
K 11 (S = K22 (i) y K12 (S =
1(zl(ri -(cJ kn(lee-Kzz(sl K
12(su”Kzl(i) E or (dJ
2(S1K12(S=Kzl) The acyclic digital lattice filter according to claim 11, wherein the symmetry of any one of the following is a % characteristic.