JPS60164855A - Cache memory - Google Patents

Abstract

PURPOSE:To make it unnecessary to disconnect a directory circuit and data blocks in a cache memory, by providing a stand-by directory circuit and switching the directory circuit to the stand-by circuit when the copy directory circuit is faulty. CONSTITUTION:When a stand-by directory circuit effective register 2320 is set, corresponding switching circuits 2310, and 2311 are used to switch the comparing circuit output of the copy directory circuit to be switched, which is indicated by a signal line 2320-2, to an output signal line 2319-1 of an OR circuit 2319 by signal lines 2321-1 and 2321-2. If a write indication of the copy directory circuit to be switched is generated in a write circuit 2305 by a signal line 2321-3, write is indicated to a stand-by directory memory 2316 and a flag memory 2317 also by a signal line 2305-3. Thus, when cache coincidence processing communication is indicated by a signal line 153, the stand-by directory circuit is operated as it is substituted for the copy directory circuit indicated by the effective register 2320.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a cache memory, and more particularly to a cache memory used when a plurality of processing devices having cache memo IJ'& share one main memory.

[Prior art]

In the cache memories of multiple data processing devices that share main memory, when another processing device rewrites the contents of the main memory, all cache memories that have copies of the contents rewrite their contents to the main memory. It becomes necessary to match the content. In order to achieve this matching, when the processing unit updates the contents of the main memory, it notifies all other cache memories of which contents have been updated (characteristic matching processing communication), and the cache memory uses this type of communication. When a communication is received, it searches its own directory device, and if corresponding data exists, it updates it or invalidates it. This is called character matching processing.

In order to perform such character matching processing, a directory device is used to search for the presence or absence of corresponding data in the cache memory.

In a normal multiprocessor, the main memory is frequently updated, so it is necessary to reduce the load on the directory device by performing cache matching processing. Therefore, a copy directory device that has copy information of the directory device is used. However, in a copy directory device with such a configuration, not only does the failure rate increase, but when a failure is detected, the consistency of the data in the cache memory and main memory may be affected. To ensure continued safety, disconnect the faulty circuit from the system.

It continued to operate at reduced capacity. Therefore, in such a reduced operation, it is necessary to disconnect not only the failed copy directory device but also the directory device and even the data blocks in the corresponding cache memory, which significantly degrades system performance. This was a contributing factor.

Therefore, it is possible to provide the directory device with a backup circuit by relatively simple reasoning.

Therefore, considering the operation of having this backup circuit, if the regular circuit is switched to the backup circuit, the information on the regular circuit side will be unreliable due to a failure.

Also, since the backup circuit side has just been switched, the contents are uncertain. In order to eliminate this uncertainty, it is sufficient to clear the entire data after switching and restart the process, but in this case, all data already stored in the cache memory is also discarded. Therefore, all subsequent accesses from the processing device must go to the main memory, which temporarily degrades performance◎ [Object of the Invention] Therefore, the first object of the present invention is to (5) In a cache memory, when a copy directory failure occurs in a copy directory device, the directory circuit and characters in the corresponding directory device are removed. - To provide a cache memory that does not require separation of data blocks in the sea memory and operates efficiently. It is in.

A second objective of the present invention is to minimize the amount of data that is discarded when switching from a regular circuit to a backup circuit when a backup circuit is used to achieve the above object. Cage is intended to provide five memory.

[Structure and effects of the invention]

In order to achieve the above-mentioned first object, the cache memory according to the present invention is provided with at least one spare directory 9 circuit, and when a failure occurs in the copy directory circuit in the copy directory device, the □ copy directory By switching the circuit to a spare directory circuit, it is no longer necessary to separate the directory circuit in the corresponding directory device and the data block in the cache memory.

(6) In addition, in order to achieve the second objective, an update flag is provided corresponding to each entry in the preliminary directory circuit to display this when the entry matches an entry in the corresponding directory circuit. By providing the above-mentioned copy directory circuit, it is not necessary to clear the corresponding directory circuit when replacing the copy directory circuit with the backup directory circuit, and by configuring the system so that only necessary entries can be sequentially cleared in response to access to the copy directory device. Sh.

In other words, by preventing unnecessary erasure of data that does not need to be erased at all, it is possible to efficiently replace the copy directory circuit with the backup directory circuit. In the latter case, when the processing unit accesses the main memory, it first indexes the directory device, and if it finds that the data is not in the cache memory, it fetches the data from the main memory and expands it to the cache memory. Since it is registered in both directory circuits at the same time, there is no need to clear anything registered in the directory as described above before character matching processing is specified, and registration in the directory circuit is relatively frequent. It is effective from this point of view as well.

Here, the configuration of the present invention will be described in detail.

included in at least one of a plurality of processing devices that share a main memory, having at least one directory circuit consisting of a plurality of entries, and in response to an access from the processing device, the at least one directory circuit a first directory device configured to search for a processing device; a copy directory circuit having copy information of the directory circuit corresponding to each directory circuit included in the first directory device; Data is exchanged between a second directory device configured to search the copy directory circuit in response to an access from the processing device, and the processing device and the main memory using the search results of the first directory device. In the cache memory having a buffer memory for sending and receiving data, the second directory device is a part of the copy directory circuit.

at least one backup directory circuit that can be used in place of this copy directory circuit and that can be searched in response to access from the other processing device, and corresponding to each entry of the at least one backup directory circuit. A flag that is provided in a flag that can be searched in response to an access from the other processing device, and when the backup directory circuit and the copy directory circuit are replaced, a flag that can be searched with a corresponding entry in the backup directory circuit. 7. a group of update flags indicating whether or not the preliminary directory circuit and the corresponding entry of the first directory device corresponding to the replaced copy directory circuit match; and when there is an access from the other processing device. , the spare directory circuit searched by this access is transferred to the switching circuit (the directory)
When the IJ circuit is replaced with the IJ circuit and the update flag of the entry for the access indicates a mismatch, clear the corresponding entry of the first directory circuit corresponding to the replaced copy directory circuit (9). A cache memory is obtained which is characterized in that it does the following.

〔Example〕

Next, the present invention will be explained in detail by way of embodiments with reference to the drawings.

FIG. 1 is a diagram showing an example of the configuration of a multiprocessor system in which the present invention is implemented. In the system shown in FIG. 1, processing units 10 and 15 having cache memories 20 and 25, respectively, have a main memory 30'f! : A shared multiprocessor system. In this system, signal lines 101 and 151 are connected to processing units 10 and 15.
This is an address signal that supplies a memory address generated by a memory address for accessing an instruction or data to the cache memories 20 and 25, respectively. When the access is for writing data, signal lines 102 and 152 are used to indicate that the access is for writing data. For reading, signal lines 201 and 2
51, data is exchanged.

The signal lines 103 and 153 are signal lines for communication in the cache matching process (10).When each processing device updates the contents of the main memory 30, each processing device updates the cache memory of the other processing device to that effect. is displayed, and the data in the cache memory corresponding to the updated memory address of the main memory 30 is instructed to be invalidated.

Signal lines 202 and 252 are connected to cache memories 20 and 2.
5 supplies a memory address when accessing the main memory 30, and when the access is for writing, it is sent via signal lines 203 and 253, and when the access is for reading data, it is sent via signal lines 301 and 351, respectively. Data is exchanged.

Note that the multiprocessor system configured as described above is merely an example, and it goes without saying that other types of systems may be used.

FIG. 2 is a diagram showing an outline of the configuration of the cache memory that is the object of the present invention in the system of FIG. 1.

This will be explained below with reference to FIG.

The IJ device 21 is a device that receives the address signal 101 from the processing device 10, searches the internal directory circuit, and displays the result on the buffer memory device 22 via the signal line 211.

The buffer memory device 22 accesses the built-in buffer memory or the main memory 30 according to the search results of the first directory device 21 informed by the signal line 211, and writes data to the signal lines 102, 201 or 202, 203, 301. Data is exchanged between the multi-processing device 10 and the main memory 30. In addition, when the buffer memory device 21 loads new data from the main memory 30 into the internal memory during the above-mentioned data transfer, the buffer memory device 21 transfers the data to the first directory device 21 and the first directory device 21 via the signal line 221. The address corresponding to the load position of the data is registered in the directory device 23 of No. 2 to enable subsequent access.

The second directory device 23 is configured as a copy of the first directory device 21 . and signal line 15
3, receives the cashier match signal, searches the internal B-REF) IJ circuit, clears its own entry based on the result, displays the signal line 231 in the first directory circuit 21, and takes action. Entries can be cleared. This completes the general description of the cache memory, and the first and second directory devices will now be described in detail. Note that the configuration and operation of the buffer memory device 22 are not directly related to the present invention, and a description thereof will be omitted to avoid complexity.

FIG. 3 is a diagram showing the details of the configuration of the first directory device (21 in FIG. 2). 1 for this figure 3
This will be explained using the diagram and FIG. 2 together.

The memory address register 2101 holds the memory address given from the processing device 10 to the signal line 101,
A part of the switching circuit 2103 is connected to the signal line 2101-3.
In addition, the other part is connected to the signal line 2101-1.
108, 2109, and the signal line 2101-
2, the address is displayed on the buffer memory device 22 via the signal line 211.

The switching circuit 2103 is connected to the signal line 2101-3.221'-1
Directory memory 210 given by ゜2312-1
6゜21o7 read or write address (
13) Switch and save the output to directory memory 2106゜2
107 is supplied to the signal line 2103-1. Similarly, the switching circuit 2104 also connects the signal line 221-2.2.
Switches the signal applied to the signal line 2104 to the directory memories 2106 and 2107.
-1 supplies write data for the memory. The initial value generation circuit 2102 is a directory memory 2106.21.
The switching circuit 210 generates initial value data to be written when clearing 07, and transfers the data to the signal line 2102-1.
Give to 4. The write circuit 2105 uses the information given through the signal line 221-3 or the signal line 231-1 to instruct the directory memories 2106 and 2107 to write through the signal lines 2105-1 and 2105-2.

The rest of the days below (14) Directory memories 2106 and 2107 are signal lines 21
05-1 or the signal line 2105-2, the data indicated by the signal line 2104-1 is written to the address indicated by the signal line 2103-1, and the data indicated by the signal line 2105-1 or the signal line 2105-1 is written. Line 2105-
If writing is not instructed by 2, the signal line 210
Data corresponding to the address indicated by 3-1 is read out to signal lines 2106-1 and 2107-1. Comparison circuit 2108-1.2108-2 is connected to signal line 2101-1
The contents of the memory address register 2101 given by the above are compared with the contents of the signal lines 2106-1 and 2107-1, and the comparison result is sent to the grapha memory device 22 via the signal line 211 via the signal lines 2108-1 and 2109-1. indicate.

As described above, the first directory device 21 shown in FIG. 3 includes the directory memory 2106 and the comparator 210.
80 sets and directory memory 2107 and comparator 210
It is configured as a directory device with a set associative configuration, having two directory circuits (separated in the figure) consisting of 90 sets.

FIG. 4 is a diagram showing the details of the configuration of the second directory device (copy directory device). This fourth
To explain the diagram using FIGS. 1 to 3 together, the memory address register 2301 corresponds to the memory address 2101 in FIG. 2, and the switching circuit 2303 corresponds to the switching circuit 21.
03, the switching circuit 2304 is connected to the switching circuit 2104, the initial value generation circuit 2302 is connected to the initial value generation circuit 2102, and the directory memory 2306 is connected to the directory memory 2106.
, the directory memory 2307 is connected to the directory memory 2107, the comparator 2308 is connected to the comparator 2108, the comparator 2309 is connected to the comparator 2109, and the write circuit 2305
correspond to the write circuit 2105, and in this range, the memory address register 2301 in FIG. 3 is configured similarly to the memory address register 2101 in FIG. 2. The directory memory 2306 and directory memory 2307 are controlled to store the same information as the directory memo IJ 2106 and directory memory 2107, respectively. In this way, the second directory device 23 includes the directory memory 23o6 and the comparator 23.
08 set and directory memory 2307 and comparator 23
The copy directory device is configured as a set associative structure copy directory device having two copy directory circuits (not differentiated in the figure) consisting of sets of 0.09.

Further, the second directory device 23 has a spare directory circuit composed of a directory memo IJ 2316 and 23180 sets of comparators, and the two copy directory circuits (2306 and 2308, 2307 and 2309). and 2318), it has a peripheral circuit described below.

Directory memory 2316, like other directory memories, has addresses on signal line 2303-1, write data on signal line 2304-1, and signal line 2305-3.
A write instruction is given to each of them, and the read output is sent to the signal line 2316-1. Also, the comparison circuit 231
8 similarly compares the contents of the signal line 2301-1 and the signal line 23161-1, and sends the result to the OR circuit 2319 via the signal line 2318-1.

Flag memory 2317 is the corresponding directory memo! J
When a value is written to 2316, the initial value generation circuit 231
5 is written to the address indicated by the signal line 2303-1, and its read output is sent to the signal line 2317-1.
The signal is transmitted to the OR circuit 2319 via .

Switching circuits 2310 and 2311 are connected to comparators 2308 and 2
The output of 309 and the output of OR circuit 2319 are switched, and the results are stored in registers 2313 and 2314, respectively. The switching circuits 2310 and 2311 are instructed to switch from the spare directory circuit valid register 2320 via the control circuit 2321 to the signal line 2321-1 and the signal line 2321-2, respectively.

Regarding the first directory device 21 and the second directory device 23 configured as described above, the signal line 1
The operation for cache matching processing communication instructed via 53 will be explained.

(18) First, spare builf) IJ circuit valid register 23
20 (simply shown as a valid register in FIG. 4) is not set.

The memory address for cache matching processing communication instructed via the signal line 153 is stored in the memory address register 2301.
A part of the data is stored in the directory memory 2306 and 2307 via the signal line 2301-2 degree switching circuit 2303 and the signal line 2303-1, and the contents are sent to the signal line 2306-1.2307-. At the same time, a part of the address is set in the register 2312. Further, the other part of the memory address register 2301 is connected to the comparators 2308 and 2309 via the signal line 2301-1.
supplied to The comparison results by the comparators 2308 and 2309 are sent to the signal line 2308-1 and the switching circuit 2310. to the register 2313 via signal line 2310-1, and to signal line 2309-1.

Switching circuit 2311. Each is set in the register 2314 via the signal line 2311-1.

At this time, if both registers 2313 and 2314 indicate a mismatch, that is, comparator 2308.

If both 2309 indicate a mismatch in the given data, the process ends. Also, register 2313.2
314 indicates a match, that is, if either one of the comparators 2308 and 2309 indicates a match for the given data, the directory memory corresponding to the comparator that indicates a match is created using the following procedure. Clear the contents of. That is, first, the address in the register 2312 is the signal line 2312-1, the switching circuit 2303. Signal line 23
Directory memory 2306, 230 via 03-1
7 and generated by the initial value generation circuit 2302 is sent to the signal line 2302-1 and the switching circuit 230.
4. Provided via signal line 2304-1. Next, the contents of registers 2313 and 2314 are set to signal line 2313-1.
．． Write circuit 2 via 2314-1.231-1
305, and the write circuit 2305 is connected to the signal line 23.
05-1 or signal line 2305-2 to write to the directory memory corresponding to the comparator that indicates a match.

Next, the spare builf) IJ circuit valid register 2320
The case where is set will be explained. The spare directory circuit valid register 2320 sends a signal indicating the validity of the register to the signal line 2320-1.

A signal indicating which copy directory circuit the spare directory circuit corresponding to the register has been switched to is sent to the control circuit 232 via the signal line 2320-2.
Give to 1. The control circuit 2321 generates the following signals based on these signals. That is, first, the signal line 2321-1
Or the corresponding switching circuit 231 via the signal line 2321-2
0.2311 and the comparison circuit output of the copy directory circuit to be switched indicated by the signal line 2320-2,
Switch to the output signal line 2319-1 of the OR circuit 2319.

In addition, the write circuit 2305 is connected to the signal line 2321-3.
When a write instruction is issued to the copy directory circuit to be switched, the configuration is configured such that when a write instruction is issued to the copy directory circuit to be switched, a write instruction is also issued to the spare directory memory 2316 and the flag memory 2317 via the signal line 2305-3.

As described above, when cache match (21) processing communication is instructed by the signal line 153 and the memory address is stored in the memory address register 2301, the backup directory circuit is converted into a copy directory circuit instructed by the backup directory circuit valid register 2320. It works as if they were swapped.

Similarly, the corresponding directory memory of the first directory device 21 in FIG. 3 is also cleared. That is,
The address in the register 2312 in FIG.
12-1. Switching circuit 2103.

Directory memory 210 via signal line 2103-1
6° 2107 and generated by the initial value generation circuit 2102 is sent to the signal line 2102-1. Switching circuit 2104. Directory memo via signal line 2104-1! 72106 and 2107, and the contents of registers 2313 and 2314 in FIG.
1 and 2314-1 (both are combined as 231-1) to the write circuit 2105. This write circuit 2105 has a signal line 2105-1.
Or the corresponding directory memo via signal line 2105-2! Instruct J2106 or 2107 (22) to write.

As a result of the above, if an entry corresponding to the address of the cache match processing communication given via the signal line 153 exists in the copy directory device 23.

The entry is cleared and the directory device 21
The corresponding entry in is also cleared.

Here, the flag memory 2317 is the directory memory 1J.
Each time a write occurs to 2316, the value generated by the initial value generation circuit 2315 is sent to the corresponding entry on the signal line 2315-
1 to remember that the directory memory 2316 has been updated.

That is, if the limb position is set in the flag memory 2317, this indicates that the same contents are written in the directory memo IJ 2316 and the corresponding directory memory of the first directory device 21.

Furthermore, when the directory memory 2316 is read out, the flag memory 2316 is also read out at the same time, and the signal line 2316 is also read out.
17-1 provides read information to the OR circuit 2319. OR circuit 2319 is a flag memo! If the flag is not set to the above value in the read information of J2317, it is made to appear as if the output of the comparison circuit 2318 indicates a match, and the output is sent to the signal line 2319-1. This flag memo! When an entry in which the J2317 flag is not set to the above value is accessed, the contents of the entry in the directory memory 2316 corresponding to the entry in the flag memory 2317 and the spare directory circuit valid register 232o corresponding to the directory memory 2316 are accessed. Directory memory 21 paired with the indicated directory memory 23o6 or 23o7
The contents of the corresponding entry of o6 or 21o7 are cleared, and at this time the flag memo! The corresponding update flag of J2317 is set.

In addition, in FIGS. 3 and 4, the cache memory 2
0 has been described, but the cache memory 25 may also be configured in a similar manner.

As explained above, the copy directory device includes spare directory circuits (3316 and 2318).

A flag memo with update flags corresponding to each entry in this circuit! J (2317) and a spare directory circuit valid register (2320), the copy directory circuit (2306 and 2308 or 23
07 and 2309) to the above-mentioned backup directory circuit, the switching can be performed efficiently by clearing only the necessary entries.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a multiprocessor system in which the present invention is implemented, and FIG. 2 is a diagram showing an overview of the configuration of a cache memory according to the present invention. Figure 3 shows in detail the configuration of the first directory device used in the cache memory in Figure 2.
FIG. 4 is a diagram showing the configuration of the second (copy) directory device in detail. Explanation of symbols: 10 and 15 are processing units, 20 is a cache memory, and 21 is a first directory device. 22 is a buffer memory device, 23 is a second delay device (25
25 is a cache memory, 30 is a main memory, 2101 is a memory address register, and 2102 is an initial value generation circuit. 2103 and 2104 are switching circuits, 2105 is a writing circuit, 2106 and 2107 are directory memories, 2108
and 2109 is a comparator, a combination of 2106 and 2108,
and the combination of 2107 and 2109 is a directory circuit,
2'3o1 is a memory address register, 2302. is an initial value generation circuit, 2303 and 230.4 are switching circuits,
2305 is a write circuit. 2306 and 2307 are copy directory memories. 2308 and 2309 are comparators, the combination of 2306 and 2308 and the combination of 2307 and 2309 are copy directory circuits, 2310 and 2311 are switching circuits, 2312 to 2314 are registers, 2315 is an initial value generation circuit, 2316 is a spare directory memo, and , 2317 is a flag memory (update flag memory), 2318 is a comparator,
The combination of 2316 and 2318 is a backup directory circuit,
2319 is an OR circuit, 2320 is a backup directory circuit, 26) is a register, and 2321 is a control circuit. (27) Figure 2

Claims (1)

[Claims] 1. Included in at least one of a plurality of processing devices that share a main memory, having at least one directory circuit consisting of a plurality of entries, and responsive to access from the processing device. a first directory device configured to search the at least one directory circuit; and a copy directory circuit having copy information of the directory circuit corresponding to each directory circuit included in the first directory device. , a second directory device configured to search the copy directory circuit in response to an access from another processing device other than the processing device; and a second directory device configured to search the copy directory circuit in response to an access from a processing device other than the processing device; In the cache memory having a buffer memory for exchanging data with the main memory, the second
The directory device includes, in addition to the IJ circuit, at least one spare directory circuit that can be used in place of the copy directory circuit and that can be searched in response to access from the other processing device. , a flag provided corresponding to each entry of the at least one backup directory circuit and capable of being searched in response to an access from the other processing device, wherein the backup directory circuit and the copy directory circuit are replaced. 7, the corresponding entry of the spare directory circuit and the first copy directory circuit corresponding to the copy directory circuit replaced with the spare directory circuit.
and a group of update flags that indicate whether or not the corresponding entry in the directory device matches. When there is an access from the other processing device, the spare directory circuit searched by this access is replaced by the directory circuit by the switching circuit, and the update flag of the entry for the access does not match. When it shows. A cache memory characterized in that a corresponding entry in the first directory circuit corresponding to the replaced copy directory circuit is cleared.