JPS6016460A - Manufacture of semiconductor image pickup device - Google Patents

Manufacture of semiconductor image pickup device

Info

Publication number
JPS6016460A
JPS6016460A JP58124989A JP12498983A JPS6016460A JP S6016460 A JPS6016460 A JP S6016460A JP 58124989 A JP58124989 A JP 58124989A JP 12498983 A JP12498983 A JP 12498983A JP S6016460 A JPS6016460 A JP S6016460A
Authority
JP
Japan
Prior art keywords
region
diffusion
substrate
layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58124989A
Other languages
Japanese (ja)
Other versions
JPH0527268B2 (en
Inventor
Junichi Nishizawa
潤一 西澤
Naoshige Tamamushi
玉蟲 尚茂
Akimasa Tanaka
章雅 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hamamatsu Photonics KK
Original Assignee
Hamamatsu Photonics KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hamamatsu Photonics KK filed Critical Hamamatsu Photonics KK
Priority to JP58124989A priority Critical patent/JPS6016460A/en
Publication of JPS6016460A publication Critical patent/JPS6016460A/en
Publication of JPH0527268B2 publication Critical patent/JPH0527268B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14679Junction field effect transistor [JFET] imagers; static induction transistor [SIT] imagers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To obtain the titled device easily manufactured at high yield and low cost by providing a photosensor array composed of SIT. CONSTITUTION:The surface of a high resistant Si substrate 21 at 50OMEGAcm or more is covered with an SiO2 film of about 1mum, an n<+> layer 22 being formed by As diffusion from the back surface, and the film 20 being then removed. An n<+> layer 25 is formed by As ion implantation from the side of the substrate 21, thus compensating the terminal part 23 of the previously formed layer 22 for diffusion sag and impurity concentration and then accurately controlling the thickness b of a channel region 24. Next, after crystal defects are annealed, the region is covered with an SiO2 film 26 about 1mum long, and with the film 26 as a mask a control gate region 26, a p<+> type shielding gate 27, and a p<+> drain 28 are formed by successive diffusion. Thereafter, when wiring is carried out by providing an electrode window, the image pickup element is completed. The n<-> channel layer can be formed with accurate uniformity by the use of the high resistant n<-> substrate and diffusion and ion implantation in such a manner, and then fine working at a high cost in SIT manufacture becomes unnecessitated, resulting in obtaining the titled device consisting of excellent SIT picture element cells at a low cost.

Description

【発明の詳細な説明】 (発明の技術分野) 本発明は、静電誘導トランジスタを光検出およびスイッ
チング素子として1つの画素セルを構成し、これを多数
配列して成る半導体撮像装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for manufacturing a semiconductor imaging device in which one pixel cell is constructed using electrostatic induction transistors as photodetection and switching elements, and a large number of these are arranged. .

(従来技術と問題点) 光検出をダイオードで行う半導体撮像装置が知られてい
る。
(Prior Art and Problems) Semiconductor imaging devices that perform light detection using diodes are known.

これに対し、光検出に光感度の大きい静電誘導トランジ
スタを用いてゲート領域に光信号をM積し、このゲニト
領域のポテンシャルに応じて、ツース・ドレイン間の電
流を制御して映像信号を取り出すことによって高い信号
出力の得られる半導体撮像装置(特願昭56−2046
56号、特願昭57−157693号)が提案されてい
る。
In contrast, an electrostatic induction transistor with high photosensitivity is used for photodetection, and an optical signal is multiplied in the gate region, and the current between the teeth and the drain is controlled according to the potential of this gate region to generate a video signal. Semiconductor imaging device that can obtain high signal output by taking out
No. 56, Japanese Patent Application No. 57-157693) has been proposed.

前記静電誘導トランジスタを用いた半導体撮像装置の製
造方法として、高抵抗半導体からなる厚みがおおよそ2
μm〜1(lcrmで表面と平行で、極めて平坦なチャ
ンネル領域を形成するのに、高品位高抵抗エビクキシャ
ル成長工程が導入されていた。しかしこの高品位、高抵
抗エピタキシャル成長工程は、エピタキシャル成長装置
の管理、また形成された層の高抵抗値の再現性に問題が
あった。通常、高品位、高抵抗エピタキシャル成長によ
って期待できる抵抗値としては、おおよそ数百Ωcmが
限界であり、また、抵抗値が1ooΩCm以上になると
、各基板に成長させた高抵抗領域の抵抗値が、各基板で
著しいバラツキを生じる。
As a method for manufacturing a semiconductor imaging device using the electrostatic induction transistor, the thickness of the high-resistance semiconductor is approximately 2.
A high-quality, high-resistance epitaxial growth process has been introduced to form an extremely flat channel region parallel to the surface (μm ~ 1 (lcrm). In addition, there was a problem in the reproducibility of the high resistance value of the formed layer.Usually, the limit of the resistance value that can be expected from high-quality, high-resistance epitaxial growth is approximately several hundred Ωcm, and the resistance value is 1ooΩCm. In this case, the resistance values of the high resistance regions grown on each substrate vary significantly from one substrate to another.

したがって、半導体撮像装置の高歩留りが期待できず、
静電誘導トランジスタを用いた半導体撮像装置の製造コ
スI・高の一因となっていた。
Therefore, high yields of semiconductor imaging devices cannot be expected;
This is a contributing factor to the high manufacturing cost of semiconductor imaging devices using electrostatic induction transistors.

(発明の目的) 本発明の目的は、静電誘導トランジスタからなる光セン
γアレイを構成し、製造が容易で、高歩留り、低コスト
な半導体撮像の装置の製造方法を提供することである。
(Objective of the Invention) An object of the present invention is to provide a method for manufacturing a semiconductor imaging device that is easy to manufacture, has a high yield, and is low in cost, by configuring a photosensor gamma array made of electrostatic induction transistors.

(発明の構成) 前記目的を達成するために本発明による半導体撮像の装
置の製造方法は、高抵抗半導体から形成されたチャンネ
ル領域を介して対向する一導電型の一生電極領域および
他生電極領域を前記両生電極領域間に流れる電流を制御
するために、前記チャンネル領域に接して設けられた他
導電型のコントロールゲート領域とからなる静電誘導ト
ランジスタを含み、光励起によって生じた電子正孔対の
一方がコントロールゲート領域に蓄積され、これによっ
て前記両生電極間の電流を制御し得るように形成された
画素セルを複数個配列して成る半導体撮像装置の製造方
法において、半導体基板の光入射側面となる方の第1の
面と反対側の第2の面からのみ、半導体基板と同一導電
型不純物を拡散する工程と、次に第1の面から前記半導
体基板と同一導電型不純物を、その深い部分が、前記第
2の面より拡散して形成した拡散層と重なり、その浅い
部分が前記第2の面より拡散した不純物が拡散していな
い基板にあるようにイオン注入する工程と、コントロー
ルゲート領域、シールディングゲート領域を形成するた
めの第1の拡散工程と、ドレイン領域を形成するための
第2の拡散工程とから構成されている。
(Structure of the Invention) In order to achieve the above object, a method for manufacturing a semiconductor imaging device according to the present invention provides a method for manufacturing a semiconductor imaging device in which a living electrode region and a different living electrode region of one conductivity type face each other across a channel region formed of a high-resistance semiconductor. and a control gate region of a different conductivity type provided in contact with the channel region in order to control the current flowing between the amphibodielectrode regions. In a method for manufacturing a semiconductor imaging device comprising a plurality of pixel cells arranged in such a manner that one of the pixel cells is accumulated in a control gate region, thereby controlling the current between the two electrodes, the light incident side surface of the semiconductor substrate and a step of diffusing an impurity of the same conductivity type as the semiconductor substrate only from a second surface opposite to the first surface of the semiconductor substrate; a step of implanting ions so that a portion thereof overlaps with a diffusion layer formed by diffusion from the second surface, and a shallow portion thereof is in a substrate where impurities diffused from the second surface are not diffused; and a control gate. The method includes a first diffusion step for forming a region and a shielding gate region, and a second diffusion step for forming a drain region.

(発明の実施例) 以下、図面等を参照して本発明をさらに詳しく説明する
(Embodiments of the Invention) The present invention will be described in more detail below with reference to the drawings and the like.

第1図は、本発明の製造方法により製造される半導体撮
像装置の画素セルの素子断面図である。同図において、
■はStのn+基板、2は高抵抗なn一層(ないしは真
性半導体層)である。
FIG. 1 is a cross-sectional view of a pixel cell of a semiconductor imaging device manufactured by the manufacturing method of the present invention. In the same figure,
2 is an n+ substrate of St, and 2 is a high-resistance n-layer (or an intrinsic semiconductor layer).

一方の主電極(ドレイン)3は高不純物密度なn+領領
域ら形成されている。 第 1のゲート(コントロールゲート)4は高不純物密度な
p+領領域ら形成され、第2のゲート(シールディング
ゲート)5も高不純物密度なp+領領域ら形成されてい
る。
One main electrode (drain) 3 is formed from an n+ region with high impurity density. The first gate (control gate) 4 is formed from a p+ region with high impurity density, and the second gate (shielding gate) 5 is also formed from a p+ region with high impurity density.

コントロールゲート電極6はS n O2膜、8はドレ
イン電極、9は5i0215ii、10はソース電極で
ある。
The control gate electrode 6 is a SnO2 film, 8 is a drain electrode, 9 is 5i0215ii, and 10 is a source electrode.

第2図を参照して、第1図に示した静電誘導トランジス
タ撮像装置の製造方法の実施例を説明する。
Referring to FIG. 2, an embodiment of a method for manufacturing the static induction transistor imaging device shown in FIG. 1 will be described.

おおよそ、50Ωc、m以上の高抵抗半導体基板21 
(通常厚みは200〜500μm)の表面に厚さ1μm
程度の熱酸化膜(Si02膜)20を形成する。
High resistance semiconductor substrate 21 of approximately 50 Ωc, m or more
(usually thickness is 200 to 500 μm)
A thermally oxidized film (Si02 film) 20 of approximately 100% is formed.

次に前記半導体21の裏面から砒素またはリンの拡散工
程により、不純物濃度I Q 18c m’以上のn+
領域22を形成する(第2図a)。
Next, by a step of diffusing arsenic or phosphorus from the back surface of the semiconductor 21, an impurity concentration of n +
A region 22 is formed (FIG. 2a).

その後、前記熱酸化膜20を除去する。After that, the thermal oxide film 20 is removed.

次に、拡散工程が施された表面とは反対側の表面から拡
散工程によって砒素またはリンのイオン注入工程により
不純物濃度1018cm−3以上のれ+領域25を形成
する(第2図b)。
Next, an arsenic or phosphorus ion implantation process is performed from the surface opposite to the surface on which the diffusion process has been performed to form a lag region 25 having an impurity concentration of 1018 cm-3 or more (FIG. 2b).

これより、さきに形成された領域22の終端部分23の
拡散ダレおよび不純物濃度補償、またチャンネル領域2
4の厚みβを正確に制御する。
From this, diffusion sagging and impurity concentration compensation of the termination portion 23 of the region 22 formed earlier, as well as channel region 2
4. Accurately control the thickness β.

次にイオン注入領域の結晶欠陥をアニールした後、熱酸
化法により熱酸化膜(Si02膜)を厚さおおよそ1μ
m程度にしたフィールド酸化膜26を形成する(第2図
C)。
Next, after annealing the crystal defects in the ion-implanted region, a thermal oxide film (Si02 film) is formed to a thickness of approximately 1 μm using a thermal oxidation method.
A field oxide film 26 having a thickness of about m is formed (FIG. 2C).

次に、このフィールド酸化膜26をマスクして、コント
ロールゲート領域、シールディング領域を形成するため
の第1の拡散工程、次に、ドレイン領域を形成するため
の第2の拡散工程を行う(第2図d)。
Next, by masking this field oxide film 26, a first diffusion process is performed to form a control gate region and a shielding region, and then a second diffusion process is performed to form a drain region. Figure 2 d).

なお図において、21はStO高抵抗n−基板、24は
チャンネル領域、26はコントロールゲート、27はシ
ールディングゲート、28はドレインである。
In the figure, 21 is a StO high resistance n-substrate, 24 is a channel region, 26 is a control gate, 27 is a shielding gate, and 28 is a drain.

この後、コンタクト窓、電極配線を設ければ、半導体撮
像素子が完成する(図示せず)。
Thereafter, contact windows and electrode wiring are provided to complete the semiconductor image sensor (not shown).

なお、前述した裏面からの拡散工程に代わり、イオン注
入工程を用いることも考えられるが、前記半導体基板の
厚みを考慮すると相当大きなエネルギーをもつイオン注
入装置が必要となり、イオン注入に伴う結晶欠陥、製造
コストの増大などの欠点を有している。
Note that an ion implantation process may be used instead of the above-mentioned diffusion process from the back side, but considering the thickness of the semiconductor substrate, an ion implantation device with considerably high energy is required, and crystal defects and It has disadvantages such as increased manufacturing cost.

また、高抵抗n一層からなるチャンネル領域24の厚み
βはおおよそ2μm〜10μm程度である。
Further, the thickness β of the channel region 24 made of a single high-resistance n layer is approximately 2 μm to 10 μm.

(発明の効果) 以上説明したように、本発明によれば、ドレインないし
はソース領域とコントロールゲートおよびシールディン
グゲートからなる静電誘導トランジスタで各画素セルを
構成した半導体撮像装置の製造方法において、高抵抗n
−基板を用い、かつ拡散工程とイオン注入工程を使用す
ることにより、従来制御が難しく、コスト高な高品位、
高抵抗エピタキシャル成長工程により形成していた高抵
抗n一層からなるチャンネル領域を正確、均一に形成で
きる。
(Effects of the Invention) As explained above, according to the present invention, in the method of manufacturing a semiconductor imaging device in which each pixel cell is composed of a static induction transistor consisting of a drain or source region, a control gate, and a shielding gate, resistance n
-By using a substrate and using a diffusion process and an ion implantation process, high quality, which was previously difficult to control and expensive,
A channel region made of a single high-resistance n layer, which was formed by a high-resistance epitaxial growth process, can be formed accurately and uniformly.

さらに高抵抗n−基板を使用することから、エピタキシ
ャル成長工程では得られない、高抵抗値、おおよそ10
0cm程度のものが得られる。
Furthermore, since a high resistance n-substrate is used, a high resistance value of approximately 10
One with a diameter of about 0 cm can be obtained.

このことにより、静電誘導トランジスタ製造の上で、高
度な、また高価な微細加工工程が必要でなくなり、製造
歩留り、製造コストに多大な利益をもたらす。
This eliminates the need for sophisticated and expensive microfabrication processes in the manufacture of static induction transistors, resulting in significant benefits in terms of manufacturing yield and manufacturing costs.

したがって、本発明方法によれば高歩留り、低コストで
優れた静電誘導トランジスタ画素セルからなる半導体撮
像装置が製造できる。
Therefore, according to the method of the present invention, a semiconductor imaging device comprising an excellent electrostatic induction transistor pixel cell can be manufactured at high yield and at low cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の画素セルの素子断面図である。 第2図(a)(b)(c)および(d)は、本発明方法
の実施例を示す製造工程を示す断面図である。 1・・・Stのn+基板 2・・・高抵抗エピタキシャル成長工程からなるn″′
層 3・・・ドレイン 4・・・コントロールケ−+−5・
・・シールディングゲート 6・・・コントロール電極 21・・・Siの高抵抗n−基板 24・・・チャンネル領域 26・・・コントロールゲート 27・・・シールディングゲート 28・・・ドレイン 特許出願人 浜松ホトニクス株式会社 代理人 弁理士 井 ノ ロ 壽 才1図 才2図 (0) (b)
FIG. 1 is a cross-sectional view of a conventional pixel cell. FIGS. 2(a), 2(b), 2(c) and 2(d) are cross-sectional views showing the manufacturing process of an embodiment of the method of the present invention. 1... St n+ substrate 2... n''' consisting of a high resistance epitaxial growth process
Layer 3...Drain 4...Control cable +-5.
... Shielding gate 6 ... Control electrode 21 ... Si high resistance n-substrate 24 ... Channel region 26 ... Control gate 27 ... Shielding gate 28 ... Drain Patent applicant Hamamatsu Photonics Co., Ltd. Agent Patent Attorney Jusai 1, 2 (0) (b)

Claims (1)

【特許請求の範囲】[Claims] 高抵抗半導体から形成されたチャンネル領域を介して対
向する一導電型の一主電極領域および地主電極領域を前
記両生電極領域間に流れる電流を制御するために、前記
チャンネル領域に接して設けられた他導電型のコントロ
ールゲート領域とからなる静電誘導トランジスタを含み
、光励起によって生じた電子正孔対の一方がコントロー
ルゲート領域に蓄積され、これによって前記両生電極間
の電流を制御し得るように形成された画素セルを複数個
配列して成る半導体撮像装置の製造方法において、半導
体基板の光入射側面となる方の第1の面と反対側の第2
の面からのみ、半導体基板と同一導電型不純物を拡散す
る工程と、次に第1の面から前記半導体基板と同一導電
型不純物を、その深い部分が、前記第2の面より拡散し
て形成した拡散層と重なり、その浅い部分が前記第2の
面より拡散した不純物が拡散していない基板にあるよう
にイオン注入する工程と、コントロールゲート領域、シ
ールディングゲート領域を形成するための第1の拡散工
程と、ドレイン領域を形成するための第2の拡散工程と
から構成した半導体撮像装置の製造方法。
A main electrode region and a main electrode region of one conductivity type, which face each other via a channel region formed from a high-resistance semiconductor, are provided in contact with the channel region in order to control the current flowing between the two bidirectional electrode regions. The transistor is formed such that one of the electron-hole pairs generated by photoexcitation is accumulated in the control gate region, thereby controlling the current between the two electrodes. In a method of manufacturing a semiconductor imaging device in which a plurality of pixel cells are arranged, a first surface of a semiconductor substrate that is a light incident side surface and a second surface of the semiconductor substrate that is opposite to the light incident side surface of the semiconductor substrate.
a step of diffusing an impurity of the same conductivity type as the semiconductor substrate only from the first surface, and then diffusing an impurity of the same conductivity type as the semiconductor substrate from the first surface, the deeper part of which is more diffused than the second surface. a first step for forming a control gate region and a shielding gate region; 1. A method of manufacturing a semiconductor imaging device comprising a diffusion step and a second diffusion step for forming a drain region.
JP58124989A 1983-07-08 1983-07-08 Manufacture of semiconductor image pickup device Granted JPS6016460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58124989A JPS6016460A (en) 1983-07-08 1983-07-08 Manufacture of semiconductor image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58124989A JPS6016460A (en) 1983-07-08 1983-07-08 Manufacture of semiconductor image pickup device

Publications (2)

Publication Number Publication Date
JPS6016460A true JPS6016460A (en) 1985-01-28
JPH0527268B2 JPH0527268B2 (en) 1993-04-20

Family

ID=14899154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58124989A Granted JPS6016460A (en) 1983-07-08 1983-07-08 Manufacture of semiconductor image pickup device

Country Status (1)

Country Link
JP (1) JPS6016460A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2684153B2 (en) * 1993-11-30 1997-12-03 富士ロビン株式会社 Air vent mechanism for engine fuel supply system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52104076A (en) * 1976-02-27 1977-09-01 Sony Corp Semiconductor unit
JPS58105672A (en) * 1981-12-17 1983-06-23 Fuji Photo Film Co Ltd Semiconductor image pickup device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52104076A (en) * 1976-02-27 1977-09-01 Sony Corp Semiconductor unit
JPS58105672A (en) * 1981-12-17 1983-06-23 Fuji Photo Film Co Ltd Semiconductor image pickup device

Also Published As

Publication number Publication date
JPH0527268B2 (en) 1993-04-20

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