JPS60163299A - Peak holding circuit - Google Patents

Abstract

PURPOSE:To reduce leak current at the time of reverse bias, to prevent a holding capacitor from discharge and to expand the holding time by inserting a circuit obtained by combining diodes between input and output operational amplifiers. CONSTITUTION:In a section until input voltage Vin reaches the 1st peak, diodes D2, D4 are ON, diodes D1, D3 are OFF and an operational amplifier U1 is kept at holding voltage Vout. In a section reducing the voltage Vin less than the holding voltage, the D3 is turned on, the voltage Vc at the nodes of the D2-D4 is limited and the reverse leak current of the D4 is turned to a slight value, so that the holding voltage is held for a long period. In a section increasing the voltage Vin larger than the holding voltage, the holding voltage is held.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a peak hold circuit,
Specifically, the present invention relates to improving the hold characteristics in a high-speed peak hold circuit.

[Prior art]

FIG. 1 is a circuit diagram showing an example of a conventional peak hold circuit, and shows an example of a positive peak hold circuit.

In Figure 1, Ul is the input voltage Vi at the non-inverting input terminal.
n is added to the first operational amplifier. A first diode D1 is connected between the output terminal and the inverting input terminal of the first operational amplifier U1.
The non-inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the second operational amplifier U2 via a second diode D2 which is connected in the forward direction to the first diode D1. Second
The output J terminal of the operational amplifier U2 is the output terminal V o u
t and directly to the inverting input terminal, and further connected via the feedback resistor R to the inverting input terminal of the first operational amplifier U1.

The non-inverting input terminal of the second operational amplifier U2 is connected to a common potential point via a hold capacitor C.

In such a circuit, when the input voltage ViTI becomes lower than the hold voltage of the capacitor C, the output voltage of the first operational amplifier U1 becomes 1111 of the first diode D1.
When the directional voltage is Vdl, it becomes Vin-Vdl, and the first diode D1 becomes reverse biased.

By the way, in a high-speed peak hold circuit, a high-speed diode such as a Schottky is used because the on/off time of the diode is required to be short.

However, since such a high-speed diode has a large leakage current when reverse biased, the charge in the capacitor C is discharged through the first diode D1, making it difficult to hold the peak for a long time. be.

[Purpose of the invention]

The present invention has focused on such points, and its purpose is to provide a peak hold circuit that is fast and has a long hold time.

[Summary of the invention]

The present invention achieves such objects by a first operational amplifier having an input terminal applied to a non-inverting input terminal, and a first operational amplifier connected between an output terminal and an inverting input terminal of the first operational amplifier. a second diode, one end of which is connected to the output terminal of the first operational amplifier so as to be in the forward direction of the first diode; a third diode connected to the other end of the diode, the other end of which is connected to the inverting input terminal of the first operational amplifier via a feedback resistor; One end of the second diode is in the forward direction with the third diode. A fourth diode connected to the connection point of the third diode and the other end connected to the common potential point via a hold capacitor, and a non-inverting input terminal connected to the connection point of the capacitor and the fourth diode. A second operational amplifier whose output terminal and inverting input terminal are connected to the connection point between the feedback resistor and the third diode, and the non-inverting input horn terminals of the second operational tg1 amplifier are selectively connected to a common potential point. It is characterized by consisting of a switch that connects to the

〔Example〕

Hereinafter, a detailed explanation will be given using the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the present invention, and shows an example of a positive peak hold circuit, and the same parts as in FIG. 1 are given the same reference numerals. In Figure 2,
A third diode D3 is connected between the inverting input terminal of the second operational amplifier U2 and the second diode D2 so as to be in the opposite direction to the second diode. A fourth diode D4 is connected between the non-inverting input terminal and the second diode D2 so as to be in the forward direction of the second diode D2. Note that S is the second
A reset switch selectively connects the non-inverting input terminal of the operational amplifier U2 to a common potential point, and r is the discharge resistance of the capacitor C at the time of reset. Here, the first.
Second operational amplifier U1. A high-speed operational amplifier is used as U2, and in particular, one with high input resistance is used as operational amplifier U2. Also, 3rd. Fourth diode D
3, the first as D4. Second diode Di.

Use a fast diode such as a Schottky similar to D2. The feedback resistor R is set to be a sufficiently low ratio with respect to the input impedance of the first operational amplifier Ul.

The operation of the circuit configured in this way will be explained using FIG. 3.

In FIG. 3, the thick solid line represents the input voltage Vin,
The thin solid line represents the voltage at the non-inverting input terminal of the second operational amplifier U2, that is, the hold voltage Va of the capacitor C, the dashed line represents the output voltage vb of the first f4 arithmetic amplifier U1, and the dashed line represents the voltage at the non-inverting input terminal of the second operational amplifier U2. It represents the voltage Vc at the connection point of D3 and D4.

First, in section 1 until the input voltage Vin reaches the first peak P1, the diodes D2 and D4 are turned on and the diodes D1 and D3 are turned off. This allows the first
The operational amplifier U1 has a hold voltage Va of Vin=Va
=Vout.

Next, in section 2 where the input voltage Vjn becomes lower than the hold voltage Va in section 1, diodes D2 and D4 become reverse biased, but when leakage current i flows through diode D2, diode D3 turns on, and diode D2 The voltage Vc at the connection point of D3 and D4 is the voltage Vc of the third diode D3.
If the voltage in one river direction is Vd3, it is limited to Vout-Vd3. As a result, the reverse bias voltage of the diode D4 is limited to 1V or less, the leakage current in the reverse direction becomes very small, and the hold voltage Va in section 1 is held for a long time.

Then, the input voltage Vin is the hold voltage Va in section 2.
In section 3, where the voltage becomes larger, the same operation as in section 1 described above is performed, and the hold voltage Va becomes Vjn=V a -V o
It operates so that u t becomes +1 in input voltage section 4.
+J performs the same operation as in section 2 to increase the hold voltage Va
As a result, the number in section 3 is held.

Note that when resetting the output voltage Vout to 0, the switch S is turned on to discharge the charge in the capacitor C.

Further, although the above embodiment shows an example of a positive peak hold circuit, a negative peak hold circuit can also be configured by reversing the direction of each of the diodes D1 to D4 in FIG. wi2.

〔Effect of the invention〕

As is clear from the above, according to the present invention, a peak hold circuit with a high speed and a long hold time can be realized, and the practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional peak hold circuit, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2. Ul, U2... operational amplifier, Di~D4... diode, C... capacitor, R... feedback resistor, S...
·switch. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 41 a first operational amplifier to which an input voltage is applied to its inverting input terminal; a first diode connected between the output terminal of the first operational amplifier and the inverting input terminal; A second diode, one end of which is connected to the output terminal of the first operational amplifier, and one end of which is connected to the other end of the second diode in the opposite direction to the second diode. is connected to the inverting input terminal of the first operational amplifier via a feedback resistor, and one end of the second diode is connected to the second and third diodes in the Ill direction. A fourth diode is connected to the connection point of the third diode and the other end is connected to a common potential point via a hold capacitor, and a non-inverting input terminal is connected to the connection point of the capacitor and the fourth diode.
a second operational amplifier whose output terminal and inverting input terminal are connected to the connection point between the feedback resistor and the third diode; and a non-inverting input terminal of the second operational amplifier. A peak hold circuit comprising a switch selectively connected to a common potential point.