JPS60160713A - Automatic gain adjusting circuit - Google Patents

Automatic gain adjusting circuit

Info

Publication number
JPS60160713A
JPS60160713A JP1752284A JP1752284A JPS60160713A JP S60160713 A JPS60160713 A JP S60160713A JP 1752284 A JP1752284 A JP 1752284A JP 1752284 A JP1752284 A JP 1752284A JP S60160713 A JPS60160713 A JP S60160713A
Authority
JP
Japan
Prior art keywords
diode
capacitor
automatic gain
voltage
gain adjustment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1752284A
Other languages
Japanese (ja)
Inventor
Junichi Hikita
純一 疋田
Shigeyoshi Hayashi
林 成嘉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP1752284A priority Critical patent/JPS60160713A/en
Publication of JPS60160713A publication Critical patent/JPS60160713A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To quicken the leading of an AGC voltage by inserting a diode between an output of an amplifier outputting a gain control voltage and a capacitor for a filter so as to charge the filter capacitor via said diode. CONSTITUTION:An output of an amplitude detector 8 enters an automatic gain adjusting amplifier 12 and is extracted as a control voltage of a mixer and an intermediate amplifier (not shown in a figure). A parallel circuit comprising a resistor 18 and a diode 22 is inserted between an output terminal 14 of the gain adjusting amplifier 12 and the filter capacitor 16, and when a potential at the terminal 14 is higher than the potential at a terminal 20 in excess of a forward voltage drop of the diode 22, since the capacitor 16 is charged rapidly via the diode 22, the charging speed is quickened and the leading speed of the AGC voltage is improved.

Description

【発明の詳細な説明】 この発明は自動利得調整回路に係り、特にその応答特性
の改善に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic gain adjustment circuit, and particularly to improving its response characteristics.

第1図は一般的な自動利得調整回路を示している。即ち
、アンテナ2に受信されたAM(振幅変1Jl)高周波
信号は、ミキサ回路4で局部発振周波数と混合されて中
間周波数に変更された後、中間周波増幅器6で増幅され
る。この中間周波増幅器6の周波数は、AM検波器8で
検波され、出力端子10から低周波出力として取出され
るとともに、自動利得調整増幅器12に加えられ、利得
制御電圧(AGC電圧)が形成される。
FIG. 1 shows a general automatic gain adjustment circuit. That is, the AM (amplitude variation 1Jl) high frequency signal received by the antenna 2 is mixed with the local oscillation frequency in the mixer circuit 4 and changed to an intermediate frequency, and then amplified by the intermediate frequency amplifier 6. The frequency of this intermediate frequency amplifier 6 is detected by an AM detector 8, taken out as a low frequency output from an output terminal 10, and added to an automatic gain adjustment amplifier 12 to form a gain control voltage (AGC voltage). .

この自動利得制御出力は、端子14に接続されたフィル
タ用コンデンサ16に加えられ、コンデンサ16に発生
した制御電圧は、ミキサ回路4及び中間周波増幅器6に
その利得制御入力として加えられている。この結果、受
信信号レベルに応じてミキサ回路4及び中間周波増幅器
6の利得が調整されるので、受信信号レベルの変動に対
応してそのレベル調整が行われ、一定レベルのオーディ
オ出力を得ることができる。
This automatic gain control output is applied to a filter capacitor 16 connected to terminal 14, and the control voltage generated across capacitor 16 is applied to mixer circuit 4 and intermediate frequency amplifier 6 as their gain control inputs. As a result, the gains of the mixer circuit 4 and the intermediate frequency amplifier 6 are adjusted according to the received signal level, so the level adjustment is performed in response to fluctuations in the received signal level, and it is possible to obtain audio output at a constant level. can.

このような自動利得調整回路において、前記制御電圧に
含まれる信号変調成分による信号波形の歪を小さくする
ためにコンデンサ16の容量を大きくすると、そのフィ
ルタ時定数により、AGC電圧の立上がりが遅くなり、
自動利得調整の応答が鈍くなる。
In such an automatic gain adjustment circuit, when the capacitance of the capacitor 16 is increased in order to reduce distortion of the signal waveform due to the signal modulation component contained in the control voltage, the rise of the AGC voltage is delayed due to the filter time constant.
Automatic gain adjustment response becomes slow.

そこで、従来、コンデンサ16に急速充電回路を付加し
、その充電速度を早めるようにしたものが提案されてい
る。
Therefore, it has been proposed to add a quick charging circuit to the capacitor 16 to increase the charging speed.

しかしながら、従来の急速充電回路では、定常状態で必
要なAGC電圧が、例えばO08■程度であるとすると
、AGC動作が生じ始める電圧、即ち、前記電圧値の半
分の0.4V程度をコンデンサ16にプリチャージし、
定常状態で必要なAGC電圧への充電速度を速めるよう
にしたものである。
However, in the conventional quick charging circuit, if the AGC voltage required in a steady state is, for example, about O08■, the voltage at which AGC operation starts, that is, about 0.4 V, which is half of the voltage value, is applied to the capacitor 16. Precharge,
This is to increase the charging speed to the AGC voltage required in a steady state.

第2図はこの場合のAGC電圧の立上がり状況を示す。FIG. 2 shows how the AGC voltage rises in this case.

時間Tの区間の立上がりは、急速充電回路を設置してい
ない場合と同様である。このため、その速度は緩やかで
あり、十分な応答速度の改善は期待できない。
The rise in the period of time T is the same as in the case where the quick charging circuit is not installed. Therefore, the speed is slow, and a sufficient improvement in response speed cannot be expected.

特に、コンデンサ1゛6の充電速度が遅い場合には、音
割れ、離調・同調操作上正確な調整操作ができない等の
不都合を生じる。即ち、フィルタ時定数は信号波形の歪
率に関係し、これとAGC電圧の立上がり速度とは表裏
の関係にあるため、回路設計においては、歪率かAGC
電圧の立上がり速度の何れかを犠牲にする必要があった
In particular, if the charging speed of the capacitors 1 and 6 is slow, problems such as cracking of the sound and the inability to perform accurate detuning and tuning operations occur. In other words, the filter time constant is related to the distortion rate of the signal waveform, and this and the rising speed of the AGC voltage are two sides of the same coin.
It was necessary to sacrifice either the voltage rise speed.

この発明はコンデンサの容量を大きくするとともにAG
C電圧の立上がり速度を改善することを目的とする。
This invention increases the capacitance of the capacitor and
The purpose is to improve the rise speed of the C voltage.

この発明は、振幅検波出力から利得制御電圧を形成する
自動利得調整増幅器の出力部に、ダイオードを介してフ
ィルタ用コンデンサを設置し、その充電速度を早めるこ
とを特徴とする。
The present invention is characterized in that a filter capacitor is installed via a diode at the output section of an automatic gain adjustment amplifier that forms a gain control voltage from an amplitude detection output, thereby increasing the charging speed.

以下、この発明を図面に示した実施例を参照して詳細に
説明する。
Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

第3図はこの発明の自動利得調整回路の実施例を示し、
第1図の自動利得調整回路と同一部分には間−符号を付
しである。
FIG. 3 shows an embodiment of the automatic gain adjustment circuit of the present invention,
Components that are the same as those in the automatic gain adjustment circuit of FIG.

自動利得調整増幅器12の出力端子14にば、抵抗18
を介して形成した端子20と接地点との間にフィルタ用
コンデンサ16が接続され、抵抗18に対して並列にコ
ンデンサ16を急速充電させるためのダイオード22が
接続されている。即ち、自動利得調整増幅器12の出力
部に抵抗18及びダイオード22を介してフィルタ用コ
ンデンサ16が設置されている。
A resistor 18 is connected to the output terminal 14 of the automatic gain adjustment amplifier 12.
A filtering capacitor 16 is connected between the terminal 20 formed through the capacitor 18 and a ground point, and a diode 22 is connected in parallel to the resistor 18 for rapidly charging the capacitor 16. That is, a filter capacitor 16 is installed at the output section of the automatic gain adjustment amplifier 12 via a resistor 18 and a diode 22.

このように構成すれば、ダイオード22はフローティン
グ型の急速充電回路を構成する。AM検波出力によって
自動利得調整増幅器12の出力端子14にAGC電圧が
発生すると、出力端子14と端子20との間には、その
AGC電圧がコンデンサ16の端子電圧より高い場合、
電位差が発生する。
With this configuration, the diode 22 constitutes a floating type quick charging circuit. When an AGC voltage is generated at the output terminal 14 of the automatic gain adjustment amplifier 12 by the AM detection output, if the AGC voltage is higher than the terminal voltage of the capacitor 16 between the output terminal 14 and the terminal 20,
A potential difference occurs.

この電位差がダイオード22の順方向降下電圧VFを越
えると、ダイオード22は導通状態となり、ダイオード
22を介してコンデンサ16に充電電流が流れる。
When this potential difference exceeds the forward voltage drop VF of the diode 22, the diode 22 becomes conductive, and a charging current flows through the diode 22 to the capacitor 16.

そして、コンデンサ16の充電が進み、端子14.20
間の電位差がダイオード22の順方向降下電圧vF以下
になると、ダイオード22は不導通となり、コンデンサ
16の充電は抵抗18を介して行われることになる。
Then, charging of the capacitor 16 progresses, and the terminal 14.20
When the potential difference between them becomes less than the forward voltage drop vF of the diode 22, the diode 22 becomes non-conductive and the capacitor 16 is charged via the resistor 18.

このようにダイオード22を介してコンデンサ16を充
電すれば、その充電速度はダイオードの動抵抗とコンデ
ンサ容量で決まるため、定常状態で必要なAGC電圧に
コンデンサ16の電圧を到達させる速度が速くなり、自
動利得調整の応答得度を改善することができる。
If the capacitor 16 is charged through the diode 22 in this way, the charging speed is determined by the dynamic resistance of the diode and the capacitor capacity, so the speed at which the voltage of the capacitor 16 reaches the AGC voltage required in a steady state becomes faster. The response of automatic gain adjustment can be improved.

また、このような充電速度の改善によって、通富、ダイ
オードの動抵抗は数Ωないし数十Ωの範囲であるため、
コンデンサ16の容量は、従来の値に対し大きくするこ
とができる。そして、AGC電圧が定常状態となってい
るとき、ダイオード22が非導通となるので、自動利得
調整増幅器12から゛抵抗18及びコンデンサ16で時
定数が設定される結果、信号変會周成分の十分な平滑効
果が得られ、信号波形の歪の発生を防止することができ
る。
In addition, due to this improvement in charging speed, the dynamic resistance of diodes is in the range of several ohms to several tens of ohms, so
The capacitance of capacitor 16 can be increased relative to conventional values. Then, when the AGC voltage is in a steady state, the diode 22 becomes non-conductive, so the time constant is set by the resistor 18 and capacitor 16 from the automatic gain adjustment amplifier 12, and as a result, the signal change frequency component is A smoothing effect can be obtained, and distortion of the signal waveform can be prevented.

また、第4図に示す実施例は、ダイオード22の保護を
図るために限流素子としての抵抗24をダイオード22
に直列に接続したものである。このようにすれば、ダイ
オード22に流れる電流を制限できるため、ダイオード
22の破壊を防止することができる。
In addition, in the embodiment shown in FIG.
are connected in series. In this way, the current flowing through the diode 22 can be limited, so that destruction of the diode 22 can be prevented.

第5図はこの発明の自動利得調整回路のAGC電圧の立
上り特性を示している。特性Aは定常状態でのAGC電
圧が高い場合、特性Bはそれが低い場合であり、これら
特性A、Bは、従来の特性Cに比較し、その速度を大幅
に改善されている。
FIG. 5 shows the rise characteristics of the AGC voltage of the automatic gain adjustment circuit of the present invention. Characteristic A is when the AGC voltage in the steady state is high, and characteristic B is when it is low.Characteristics A and B have greatly improved speeds compared to the conventional characteristic C.

即ち、従来の急速充電回路では、AGC電圧が異なる場
合、それぞれのAGC電圧値に対して急速充電を行う電
圧値を設定することが必要であるのに対し、この自動利
得調整回路では、どのようなAGC電圧値に対してもそ
のAGC電圧より僅か低い電圧値、即ち、定常AGC電
圧よりダイオード22の順方向降下電圧VFだけ低い電
圧値までコンデンサ16を急速充電し、それ以後では抵
抗24及びコンデンサ16の時定数によりその制御動作
が得られる。この自動利得調整回路では、種々のAGC
電圧に対応して急速充電する電圧値が自動的に設定され
、その充電速度を大幅に改善することができる。なお、
このような制御動作により、ダイオード22が非導通と
なる結果、コンデンサ16の容量を大きく設定できる。
In other words, in conventional quick charging circuits, when the AGC voltages are different, it is necessary to set a voltage value for quick charging for each AGC voltage value, but with this automatic gain adjustment circuit, The capacitor 16 is quickly charged to a voltage value slightly lower than the AGC voltage, that is, the voltage value is lower than the steady AGC voltage by the forward drop voltage VF of the diode 22, and after that, the resistor 24 and the capacitor are charged. A time constant of 16 provides its control action. This automatic gain adjustment circuit uses various AGC
The voltage value for rapid charging is automatically set according to the voltage, and the charging speed can be significantly improved. In addition,
As a result of such a control operation, the diode 22 becomes non-conductive, so that the capacitance of the capacitor 16 can be set to a large value.

以上説明したようにこの発明によれば、コンデンサをA
GC電圧の発生に応じて急速に充電することができると
ともに、フィルタ時定数を大きく設定することができる
ので、AGC電圧中の信号変調成分を十分にに平滑して
除くことができ、歪率を低下させることができる。
As explained above, according to the present invention, the capacitor is
In addition to being able to charge rapidly in response to the generation of the GC voltage, the filter time constant can be set large, so signal modulation components in the AGC voltage can be sufficiently smoothed and removed, reducing the distortion factor. can be lowered.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は一般的な自動利得調整回路を示すブロック図、
第2図は従来のAGC電圧の立上がり特性を示す説明図
、第3図はこの発明の自動利得調整回路の実施例を示す
回路図、第4図はこの発明の自動利得調整回路の他の実
施例を示す回路図、第5図はコンデンサにおけるAGC
電圧の立上がり特性を示す説明図である。 12・・・・自動利得調整回路器、16−・フィルタを
構成するコンデンサ、22・・・ダイオード、24・・
・限流素子としての抵抗。 第1図 第2図 1.5間 第3図 第4図 時 間
Figure 1 is a block diagram showing a general automatic gain adjustment circuit.
FIG. 2 is an explanatory diagram showing the rise characteristics of a conventional AGC voltage, FIG. 3 is a circuit diagram showing an embodiment of the automatic gain adjustment circuit of the present invention, and FIG. 4 is another embodiment of the automatic gain adjustment circuit of the present invention. Circuit diagram showing an example, Figure 5 shows AGC in a capacitor
FIG. 3 is an explanatory diagram showing voltage rise characteristics. 12...Automatic gain adjustment circuit, 16--Capacitor constituting filter, 22...Diode, 24...
・Resistance as a current limiting element. Figure 1 Figure 2 1.5 hours Figure 3 Figure 4 Time

Claims (1)

【特許請求の範囲】 (11AM検波出力から利得制御電圧を形成する自動利
得調整増幅器の出力部に、ダイオードを介してフィルタ
用コンデンサを設置したことを特徴とする自動利得調整
回路。 (2) 前記ダイオードには限流素子を直列に接続した
ことを特徴とする特許請求の範囲第1項に記載の自動利
得調整回路。
[Scope of Claims] (An automatic gain adjustment circuit characterized in that a filter capacitor is installed via a diode at the output part of an automatic gain adjustment amplifier that forms a gain control voltage from the 11AM detection output. (2) The above. 2. The automatic gain adjustment circuit according to claim 1, wherein a current limiting element is connected in series to the diode.
JP1752284A 1984-02-01 1984-02-01 Automatic gain adjusting circuit Pending JPS60160713A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1752284A JPS60160713A (en) 1984-02-01 1984-02-01 Automatic gain adjusting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1752284A JPS60160713A (en) 1984-02-01 1984-02-01 Automatic gain adjusting circuit

Publications (1)

Publication Number Publication Date
JPS60160713A true JPS60160713A (en) 1985-08-22

Family

ID=11946277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1752284A Pending JPS60160713A (en) 1984-02-01 1984-02-01 Automatic gain adjusting circuit

Country Status (1)

Country Link
JP (1) JPS60160713A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116846A (en) * 1974-08-02 1976-02-10 Hitachi Ltd Agc denatsuhatsuseikairo

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116846A (en) * 1974-08-02 1976-02-10 Hitachi Ltd Agc denatsuhatsuseikairo

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