JPS60158621A - Superposing mark - Google Patents

Superposing mark

Info

Publication number
JPS60158621A
JPS60158621A JP59011933A JP1193384A JPS60158621A JP S60158621 A JPS60158621 A JP S60158621A JP 59011933 A JP59011933 A JP 59011933A JP 1193384 A JP1193384 A JP 1193384A JP S60158621 A JPS60158621 A JP S60158621A
Authority
JP
Japan
Prior art keywords
mark
electron beam
marks
thick oxide
oxide films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59011933A
Other languages
Japanese (ja)
Inventor
Shinji Okazaki
信次 岡崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59011933A priority Critical patent/JPS60158621A/en
Publication of JPS60158621A publication Critical patent/JPS60158621A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To omit the forming process of a mark by a method wherein projection of an electron beam is performed for the prescribed hours to the referential mark part. CONSTITUTION:Thick oxide films 2 for oxide isolation formed on an Si semiconductor substrate 1 are formed normally according to the LOCOS method, etc. Even when marks 4 for electron beam directly drawing are formed by thick oxide films, because the step difference is not steep, the marks are not formed as the step difference marks. However, when an electron beam is projected for the prescribed hours to this construction, electrons are caught to the thick oxide films, surface electric potential is reduced, and a strong mark signal can be obtained. Accordingly, a mark forming process can be omitted.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は電子線直接描画法に係り、特に高精度な重ね合
せ精度が得られる重ね合せマークの構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an electron beam direct writing method, and particularly to a structure of an overlay mark that can obtain high overlay accuracy.

〔発明の背景〕[Background of the invention]

従来の電子線直接描画用のマークは特別な段差を形成し
たり、重金属をマークとして形成する等通常のLSI製
造工程で得られる構造とは別の構造を特別に形成するこ
とが多く、工程の複雑化やブ[1セス条件の制限が多く
なる等の欠点があった。
Conventional marks for electron beam direct writing are often specially formed with a structure different from that obtained in the normal LSI manufacturing process, such as by forming a special step or using heavy metal as a mark. There were drawbacks such as increased complexity and increased number of restrictions on process conditions.

〔発明の目的〕[Purpose of the invention]

本発明の目的はこのような従来法の欠点をなくし、通常
のLSI製造工程で容易に得られる構造を用いて電子線
直接描画用のマークを提供することにある。
An object of the present invention is to eliminate such drawbacks of the conventional method and to provide a mark for direct writing with an electron beam using a structure that can be easily obtained in a normal LSI manufacturing process.

〔発明の概要〕[Summary of the invention]

電子線直接描画法において電子ビームと半導体ウェハの
相対的位置関係を検出する基準がマークである。通常マ
ークは急峻な段差や、周囲と原子量の違う物質を置くこ
とによりその反射電子の大きさを変えて信号としていた
。この反射電子は半導体の表面電位によっても大きく変
化することは走査型電子顕微鏡の反射電子像等からも知
られている。
In the electron beam direct writing method, marks are the reference for detecting the relative positional relationship between the electron beam and the semiconductor wafer. Marks usually have steep steps or a material with a different atomic weight than the surrounding area, which changes the size of the reflected electrons and uses them as a signal. It is known from backscattered electron images taken with a scanning electron microscope that these backscattered electrons vary greatly depending on the surface potential of the semiconductor.

例えば半導体基板上に形成された厚さの違う絶縁膜や導
体中に置かれた絶縁物は電子ビームの照射によりチャー
ジアップを起し強い反射電子を発生させる。このような
絶縁膜の膜厚変化をマークとすることにより、従来特別
な工程で形成されていた重ね合せマークを全く新しい工
程の追加なしに形成できる。
For example, insulating films of different thicknesses formed on a semiconductor substrate or insulators placed in a conductor are charged up by electron beam irradiation and generate strong reflected electrons. By using such a change in the film thickness of the insulating film as a mark, an overlay mark, which was conventionally formed by a special process, can be formed without adding a completely new process.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の詳細な説明する。 The present invention will be explained in detail below.

実施例1 本実施例ではMO5LSIの酸化物分離層をマークとし
た。
Example 1 In this example, an oxide isolation layer of MO5LSI was used as a mark.

第1図に示すようにSi半導体基板l上に形成した酸化
物分離用の厚い酸化膜2は通常LOCO5法等で形成さ
れ1周囲の薄い酸化膜領域3との境界はなだらかな膜厚
変化を有しており電子線直接描画用のマーク4を厚い酸
化膜で形成しても、段差が急峻でないため段差マークと
はならない。ここで図のa部がマーク形成部、b部が素
子部である。
As shown in FIG. 1, the thick oxide film 2 for oxide isolation formed on the Si semiconductor substrate 1 is usually formed by the LOCO5 method, etc., and the boundary with the surrounding thin oxide film region 3 has a gradual thickness change. Even if the mark 4 for electron beam direct drawing is formed of a thick oxide film, it will not become a step mark because the step is not steep. Here, part a in the figure is a mark forming part, and part b is an element part.

しかし、この構造に30kVの電子線を10A/cI1
12で10mS照射した所、厚い酸化膜に電子が捕捉さ
れ、表面電位が下り1強いマーク信号が得られるように
なった。
However, when applying a 30kV electron beam to this structure at 10A/cI1,
When irradiation was performed for 10 mS at No. 12, electrons were captured in the thick oxide film, the surface potential decreased, and a strong mark signal was obtained.

実施例2 本発明の別の実施例を第2図に示す。本実施例では表面
が平坦化されたMO5LSIに本発明を応用した例であ
る。この場合従来法では全くマーク信号は得られなかっ
たが、実施例1と同様に30kV。
Example 2 Another example of the present invention is shown in FIG. This embodiment is an example in which the present invention is applied to a MO5LSI whose surface is flattened. In this case, no mark signal was obtained using the conventional method, but as in Example 1, the voltage was 30 kV.

10 A / a部2の電子線を1.0mS照射した後
に良好なマーク信号が得られるようになった。
After irradiating the electron beam of 10 A/a part 2 for 1.0 mS, a good mark signal was obtained.

実施例3 本発明の別の実施例を第3図に示す。これはLSIの多
層配線の第一層間膜6に形成したスルーホール用穴8を
マークに利用するものである。
Example 3 Another example of the present invention is shown in FIG. This uses a through-hole hole 8 formed in a first interlayer film 6 of a multilayer wiring of an LSI as a mark.

ここで形成したスルーホールはテーパ状にエツチングさ
れるため、段差マークには使えない。しかし第一配線7
上に孤立した厚い層間膜9は実施例1.2と同様にマー
ク検出前に短時間の電子線照射によりマークとして利用
可能となった。
The through hole formed here is etched into a tapered shape, so it cannot be used as a step mark. However, the first wiring 7
The thick interlayer film 9 isolated on the top can be used as a mark by short-time electron beam irradiation before mark detection, as in Example 1.2.

〔発明の効果〕〔Effect of the invention〕

本発明によれば従来なかなか利用できなかった半導体素
子構造のうち、素子間の絶縁分離用に用いている厚い酸
化膜や、層間絶縁膜を積極的に利用することができるの
で、従来電子線直接描画では不可欠とされていたマーク
の形成工程を省略できるという効果がある。
According to the present invention, thick oxide films and interlayer insulating films, which are used for insulation isolation between elements, can be actively used among semiconductor element structures that have been difficult to utilize in the past. This has the effect of omitting the step of forming marks, which was considered indispensable in drawing.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるマーク構造を通常のLOCO5構
造のMO5LSIに適用した場合の断面図、第2図は表
面平坦化を行った場合の例、第3図は多層配線の層間膜
を用いた場合の例である。 ■・・・Si基板、2・・・厚い素子分離用絶縁膜、3
・・・薄い絶縁膜、4・・・LOCO5法で形成したマ
ーク、5・・・Jダい酸化膜、6・・・層間絶縁膜、7
・・・第1配線層、8・・・第1スルーホール、9・・
・層間絶縁膜により形第 I 口 第 3 口
Figure 1 is a cross-sectional view when the mark structure according to the present invention is applied to a MO5LSI with a normal LOCO5 structure, Figure 2 is an example when the surface is flattened, and Figure 3 is an example when an interlayer film of multilayer wiring is used. This is an example of a case. ■...Si substrate, 2...Thick element isolation insulating film, 3
... Thin insulating film, 4... Mark formed by LOCO5 method, 5... J-resistant oxide film, 6... Interlayer insulating film, 7
...first wiring layer, 8...first through hole, 9...
・Shaped I opening and 3rd opening due to interlayer insulating film

Claims (1)

【特許請求の範囲】[Claims] 電子線直接描画法に於てその重ね合せ基準となるマーク
を厚い絶縁性膜と薄い絶縁性膜の組合せ若しくは絶縁性
膜と導電性膜との組合せで形成し、該基準マーク部に一
定時間電子線照射を行うことを特徴とする重ね合せマー
ク。
In the electron beam direct writing method, a mark that serves as a reference for overlay is formed by a combination of a thick insulating film and a thin insulating film, or a combination of an insulating film and a conductive film, and electrons are applied to the reference mark portion for a certain period of time. An overlay mark characterized by line irradiation.
JP59011933A 1984-01-27 1984-01-27 Superposing mark Pending JPS60158621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59011933A JPS60158621A (en) 1984-01-27 1984-01-27 Superposing mark

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59011933A JPS60158621A (en) 1984-01-27 1984-01-27 Superposing mark

Publications (1)

Publication Number Publication Date
JPS60158621A true JPS60158621A (en) 1985-08-20

Family

ID=11791468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59011933A Pending JPS60158621A (en) 1984-01-27 1984-01-27 Superposing mark

Country Status (1)

Country Link
JP (1) JPS60158621A (en)

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