JPS60158492A - Running mean computing unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an electronic musical instrument that generates musical tones in response to audio input, and more particularly to a moving average calculation device for digital processing of audio input.

[Prior art]

Advances in electronic technology have made it possible to generate musical sound waveforms electronically and to generate musical tones through speakers. This aforementioned device is generally called an electronic musical instrument. This electronic musical instrument generally uses a key to select the musical tone that should be generated. Chi etc., Yo 7, Pier 7, 7) Sound and others. You can specify the sound of an instrument and generate it.

[Problems with conventional technology]

As mentioned above, this electronic musical instrument uses keys to select musical tones, so in order to play it, it is necessary to practice piano skills and how to operate the keys. In other words, it is not possible to simply provide accompaniment to, for example, a person's song, and only those who have the skills to operate an electronic musical instrument can do so.

That is, conventional electronic musical instruments operated by keys have a problem in that they cannot be easily played by anyone.

[Purpose of the invention]

The present invention is intended to solve the above-mentioned problems, and its purpose is to provide a portable electronic musical instrument that can be easily operated and played or accompanied by an electronic musical instrument without having the operating skills for electronic musical instruments. The object of the present invention is to provide an average calculation device.

[Key points of the invention]

The present invention provides a storage means for storing input data, and an accumulation means for selecting and accumulating data in the storage means.

and averaging means for averaging the results of the accumulating means.

It is characterized in that the output of the storage means and the output of the averaging means are selected, accumulated, and averaged.

[Embodiments of the invention]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

This figure shows the configuration of an electronic musical instrument that generates musical tones in response to audio input. The output of the microphone 1, which converts audio into electrical signals, is applied to a preprocessing section 2. The output of the preprocessing section 2 is connected to the pinch extraction section 3. The output of the pitch extractor 3 is applied to the processor (CPU) 5 via the latch 4. The output of the processor 5 is sent to the pitch extractor 3. Storage section 6. Error removal section 7. Moving average calculation unit 8. It is connected to the flag creation section 9.

The output of the storage section 6 is applied to the error removal section 7 and the pitch data control section 10, and the output of the error removal section 7 is applied to the moving average calculation section 8 and the pitch data control section 10, respectively. The output of the moving average calculation section 8 is connected to a pitch data control section 10 and a code generator 11.

Further, the output of the B/7 chip control section 10 is also connected to the code generator 11. The output of the code generator 11 is connected to a musical tone generator 12, and the output of the musical tone generator 12 is connected to a speaker 13 that converts an electrical signal into sound.

The audio signal converted into an electrical signal by the microphone 1 is applied to a preprocessing section 2, where it is preprocessed. This pretreatment is the first
For example, signals outside the band are removed using a low pass filter (LPF) or the like.

This out-of-band removal is done to prevent malfunctions in the pinch extraction performed by the next stage.

Furthermore, the second step of the preprocessing is to amplify the input audio signal from which out-of-band components have been removed by an automatic gain control circuit to a specific amplitude value.

Third, the input audio signal having the above-mentioned specific amplitude value is converted into digital data by an analog/digital conversion circuit. The aforementioned amplification to achieve the specific amplitude value is performed in order to make the number of output bits of this analog/digital conversion circuit effective.

The digital audio signal from the audio signal portion processed by the preprocessing unit 2 is applied to the pinch extraction unit 3. The pinch extractor 3 extracts the pitch of the fundamental frequency of the human voice signal under the control of the processor (CPU) 5. The pinch extractor 3 is an audio data quantization circuit whose details are described in, for example, Japanese Patent Application No. 58-31284, Japanese Patent Application No. 58-31285, and Japanese Patent Application No. 58-31286.

It has a scale extraction circuit and a ternary correlation processing circuit, and performs pinch extraction using these circuits. The data quantization circuit sequentially obtains the maximum and minimum values of the audio digital data over a specific period of time, and uses the maximum and minimum values to determine respective threshold levels for, for example, ternarization.

Then, the input signal is ternarized at that threshold.

The audio extraction circuit is a circuit that delays audio ternary data obtained by ternarizing audio data using the aforementioned audio digital data in correspondence with the scale to be extracted, and multiplies the delayed data by input data. This circuit provides time correlation. This data simply represents a mere temporal correlation between the delayed data and the input data, and is further processed to perform pinch extraction. The above-mentioned ternary correlation processing circuit performs this extraction. The ternary correlation processing circuit is a circuit that performs window processing and the like for pitch extraction. In other words, since multiple pieces of data are output from the aforementioned scale extraction circuit corresponding to the scale to be extracted, this ternary correlation processing circuit performs window processing on the multiple data, in other words, it performs weight estimation in relation to the scale. This is then accumulated over a specific period of time (one frame). Then, find the maximum value from the accumulated value (accumulated value corresponding to the delay time),
The pinch is determined by the delay time corresponding to the maximum value and output. This output is data related to the pitch of the fundamental wave of the input voice (including tonic waves).

The pitch data output from the aforementioned pinch extraction section 3 is processed by Lasoji 4. The data is stored in the storage unit 6 via the processor 5.

The error removal unit 7 uses the data stored in the storage unit 6 to detect a change in specific pinch data, especially a change of one octave or more in only one frame, and when the change is detected, the data is This is a circuit to restore the data before it changes. However, there may be sudden changes in the scale.

At this time, the data changes after one frame. The data from which errors have been removed in the error removal section 7 is averaged in a moving average calculation section 8. This average is, for example, an additive average obtained by multiplying the average up to now and data over six frames. Let me explain in more detail.

In the arithmetic unit 8, pitch data in frame units that are input sequentially is stored in a shift register and shifted in frame units, and the six stages of shift data and the average value are selected by a selector within one frame period. The average is performed by accumulating the values and truncating the lower bits, for example.

The averaged data is output from the moving average calculation unit 8,
It is added to the pitch data control section 1o and performs processing for generating musical tones. In other words, the error removal unit 7 described above detects a malfunction in pinch extraction due to external noise, etc.
This is the circuit to remove.

Some eliminate large step changes in data as a result of pitch extraction malfunctions. The moving average calculating section is a circuit that has a hysteresis effect and averages subtle changes in data due to pitch errors caused by subtle pitch changes in input audio, etc., to stabilize the data.

The human voice is not limited to singing; it also has consonants and vowels.

Vowels contain many fundamental waves, but consonants have very few. For this reason.

While only consonants are being generated (for example, while "'S" is being generated when "SA" is being generated), the pinch of the fundamental wave may be erroneously extracted. The pitch data control section eliminates malfunctions of musical tones due to these erroneous extractions and makes them match the scale of the input voice. Then, this control section selects and outputs the data stored in the storage section 6, the output data of the error removal section 7, or the output data of the moving average calculation section 8, using data such as audio power and audio input detection. do.

The code generator 11 is a circuit that converts the output of the pitch control section 10 described above into the code of the musical tone to be generated by the musical tone generating section 12, that is, musical tone data.

Pinch extractor 3 mentioned above. Storage section 6. Error removal section 7.
The moving average calculation unit 8 is controlled by the processor 5. Also, a pitch data control section 1o.

The code generator 11 is controlled by the processor 5 via the flag generator 9. In other words, the processor 5 sets a flag in the flag creation section 9, and the flag causes the pitch data control section 10.
Code generator 11 operates.

The output of the 2-1 generator 11, that is, the converted data, is applied to the musical tone generator 12, and specifies the musical tone to be output from the speaker 13. In other words, the musical tone generator 1
At step 2, a musical tone electric signal (analog) specified by the conversion data of the code generator 11 is generated and applied to the speaker 13. As a result, the speaker 13 generates a musical tone corresponding to the input voice.

The circuit shown in FIG. 1 represents the configuration of an electronic musical instrument that generates musical tones in response to audio input.

The moving average calculation device of the present invention will be further explained in detail below.

FIG. 2 is a circuit diagram showing the moving average calculating section 8 of FIG. 1 in more detail.

The output of the error removing section 7 is applied to the shift register 15 via the latch 14. The outputs of the shift register 15 and the lunch 16 are applied to the selector 17. Further, the output of the octal counter 18 to which the clock φ0 is applied is also applied to the selector 17. The output of the selector 17 described above is applied to the first input of the adder 19, and the output of the adder 19 is applied to the second input via the latch 20. Additionally, the output of adder 19 is applied to latch 21 via launch 20. Top 8 latch 21
The bit output is applied to the first input of the adder.

The output of the 9th bit of the latch 21 is added to the carry power of the adder 22. The output of the adder is applied to the launch 16 via the latch 23 and is also output to the next stage counter, that is, the pitch data control section 10.

For example, 8-bit data from which errors have been removed by the error removing section 7 is stored in the latch 14 as data for one frame. This latch 14 takes in data at the frame clock φ in order to process the error-removed results in units of frames.

The shift register 15 is a register for shifting 8-bit parallel data, and shifts in accordance with the frame clock φ. That is, the data stored in the launch is sequentially stored in a shift register in units of frames and shifted. In other words, the shift register 15 is a circuit that stores six data preceding the current data in order to calculate an average.

On the other hand, the launch 16 is two sets of latch circuits.

The same data as the output of the moving average calculating section 8 is added to the lunch 16. The same data is stored in the two lunches. The selector 17 is the shift register 1 mentioned above.
6-height (8 bits in 1 byte) data stored in 5 and the same 2-byte data stored in lunch 16
- are sequentially selected within one frame and output. This selection instruction is made by the counter value of the octal counter 18, which is incremented by the clock φ0 having eight clocks during one frame.

Since the output of the adder 19 is applied to the second input via the latch 20, the output of this circuit, that is, the output of the latch 20, sequentially transfers the data applied to the first input of the adder 19 to φ0.
Configure an accumulation counter that accumulates. Furthermore, this lunch 2
0 occurs at the end of one frame, or cent clock φ,
Since it is reset by , it is accumulated in frame units.

The first input of the adder 19 is connected to the shift register 15 . Since the contents of the latch 16 are selected and added, the accumulated output of the above-mentioned accumulation circuit is the sum of the accumulation over six frames and the value twice the currently output data. That is, the data stored in the shift register 15 is converted to D n + I-D n + e, -77
If the data output from chip 23 is Ds, then
The cumulative output Dx of the aforementioned cumulative circuit is =ΣDn+ j! 2 ・Ds ・---・(1)L
++ becomes. With this adder, the value obtained by weighting the average value and the 6 data are accumulated, and an accumulated value for setting a new average value is obtained. Data that is weighted with the previous average value is used as the data to calculate the new average value corresponding to the next frame clock.For example, for the adjacent musical scale "C", "B" or " This is to keep the adjacent data constant since C' often occurs due to pitch extraction errors and the data may fluctuate randomly.The data added to the first input of the adder 19 is 8 bits. The above-mentioned cumulative output becomes 11 pino 1-data.The output is immediately connected to the next latch 2, which sets Dχ/8.
1 and adder 22. Latch 21 stores the accumulated output and adds the upper 8 bits to the input of adder 22. And 9
Add B and G to Adder 22's carry power. 9bi.

The purpose of adding the 9th point to the adder 22 is to consider the 9th point rather than simply truncating the lower three hits of the 11-bit data. That is, when the 9th bit and the 7th bit are "1", 1 is added to the data of the upper 8 bits to obtain an average output, and when it is 0, no addition is made, and the lower 3 bits are discarded and output. As mentioned above, the latch 21 and adder 22 are circuits for outputting the average value with high accuracy, and are used in cases where high accuracy is not required.

It is not necessary in some cases.

The output of adder 22 is stored in latch 23.

This latch 23 is a circuit for keeping the interframe data constant, since its output is used in the next stage and accumulation during the next frame.

In summary, the circuit in Figure 2 uses the average value as part of the input data to create a hysteresis effect in the C average operation, making it more responsive to changes in the lower bits of the data. This is a circuit that prevents

FIG. 3 is a timing diagram showing timing clocks of each circuit in the embodiment of the present invention. The operation shown in FIG. 2 will be further explained using this timing diagram. The frame clock φ is a clock that is generated at the beginning of one frame and is used to store necessary data and shift data.

In FIG. 2, lunches 14, 16. The shift register 15 operates with this clock. By generating this clock, data stored in a latch or the like is fixed for one frame. Then, the clock φ0 is sequentially output eight times during one frame. This clock is for incrementing the octal counter 18 and sequentially selecting the eight data inputted by the selector 17 within one frame. Furthermore, it is also a clock for accumulation. That is, the clock φ
At the rising edge of 0, the octal count 18 advances.

Select data. Then, the selected data is added to the adder 19. At this time, the selected data and the added data up to now have been input to the adder 19.

This adder adds or accumulates. Then, at the falling edge of clock φ0, latch φ0 stores the data. This operation is performed eight times per frame and accumulated. Note that, as described above, this accumulation is an addition of twice the average value of the past six data and the previous data. After the eighth clock is generated, a clock φS is generated and the two accumulated values are stored in the latch 21. At about the same time as this storage, Adder 22
Since the accumulated value is added to , the adder performs the addition with the carry mentioned above and outputs it. This output is the average output.

This process is performed by the next generated clock φ. The clock φ is done before the IJT. The latch 23 stores and outputs the average value. Then, the storage in the latch 20 is reset by the clock φ. This clock is a clock for performing accumulation in units of one frame.

One embodiment of the present invention has been described above in detail.

The present invention is a circuit that calculates a new average value by accumulating the aforementioned 6 data and twice the average value, but this is not limited to 6 data and is not limited to the binary value of the average value. Note that when the number of data or the multiple of the average value is changed other than in the embodiment, a corresponding division circuit is required.

〔Effect of the invention〕

As described above, the present invention accumulates and averages a plurality of pieces of data and multiples of the previous average value, and it is also possible to obtain a moving average calculation device having a hysteresis effect. Further, by using two aspects of the present invention, it is possible to obtain an electronic musical instrument that generates musical tones in response to audio input.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 2 is a more detailed circuit diagram of the moving average calculation section of FIG. 1. FIG. 3 is a timing clock diagram of an embodiment of the present invention. 8...Moving average calculation unit 14.16, 20, 21.23...Latch 15...
Shift 1 to register 17...Selector 18...Counter 19, 22
．． ... Adder patent applicant Yoshiyuki Osuga, patent attorney for Casio Computer Co., Ltd.

Claims (5)

[Claims] (1) It has a storage means for storing input data, an accumulation means for selecting and accumulating the data in the storage means, and an averaging means for averaging the results of the accumulation means, and the output of the storage means and the output of the averaging means, and selects and accumulates and averages. (2) The moving average calculation device according to claim 1, wherein the storage means is a shift register. (3) The accumulating means has a counter, a selector, and an adder, and the select selects the outputs of the storage means and averaging means according to the contents of the counter, and adds the selected outputs to the first input of the adder. 2. The moving average calculation device according to claim 1, wherein the output of the adder is added to the second input. (4) A patent characterized in that the averaging means has a half adder, a plurality of upper bits of the accumulating means are added to the input of the adder, and one bit following the plurality of upper bits is added to the carry power of the adder. A moving average calculation device according to claim 1. (5) The selector has eight input terminals, each input terminal is connected to the output of a storage means consisting of a six-stage shift register, and the output of the averaging means is applied to each of the six input terminals. 3. The moving average calculation device according to claim 2, wherein the moving average calculation device is applied to two input terminals.