JPS60158248U - Failure detection circuit for information processing equipment - Google Patents
Failure detection circuit for information processing equipmentInfo
- Publication number
- JPS60158248U JPS60158248U JP4342484U JP4342484U JPS60158248U JP S60158248 U JPS60158248 U JP S60158248U JP 4342484 U JP4342484 U JP 4342484U JP 4342484 U JP4342484 U JP 4342484U JP S60158248 U JPS60158248 U JP S60158248U
- Authority
- JP
- Japan
- Prior art keywords
- preset
- information processing
- clock signal
- detection circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はウオッチドグタイマの従来例を示す構成図、−
第１Ａ図はその動作を説明するためのタイミング図、第
２図はこの考案の実施例を示す構成図である。
符号説明、１・・・・・・中央処理装置（ＣＰＵ）、２
・・・・・・プリセッタブルカウンタ、３・・・・・・
クロック停止検出回路、４，４１．４２・・・・・・ク
ロックジェネレータ、５・・・・・・オアゲート、６・
・・・・・データバス、７・・・・・・■１０コントロ
ーラ。Figure 1 is a configuration diagram showing a conventional example of a watchdog timer.
FIG. 1A is a timing diagram for explaining its operation, and FIG. 2 is a configuration diagram showing an embodiment of this invention. Code explanation, 1...Central processing unit (CPU), 2
・・・・・・Presettable counter, 3・・・・・・
Clock stop detection circuit, 4, 41.42... Clock generator, 5... OR gate, 6.
...Data bus, 7...■10 controller.
Claims (1)
にもとづいて所定のプログラムを実行し所定周期毎にプ
リセット信号を出力する中央処理装置とを有してなる情
報処理装置において、前記入出力コントローラに対して
与えられる第２のクロック信号を計数し該プリセット信
号を受ける毎に所定値にプリセットされるカウンタを設
けるとともに、前記中央処理装置には該カウンタがプリ
セットされる毎にそれから所定時間経過後のカウント値
をその都度読み込んでこれを所定の値と比較する比較手
段を設け、該比較結果から前記第２クロツク信号の停止
を検出する一方、前記カウントアツプ信号からプログラ
ムの暴走を含む中央処理装置の異常または第１クロツク
の停止を検出することを特徴とする情報処理装置の故障
検出回路。In an information processing device comprising an input/output controller and a central processing unit that executes a predetermined program based on at least a first clock signal and outputs a preset signal at predetermined intervals, A counter is provided that counts the applied second clock signal and is preset to a predetermined value each time the preset signal is received, and the central processing unit is provided with a counter that counts the second clock signal and is preset to a predetermined value each time the counter is preset. A comparison means is provided for reading the clock signal each time and comparing it with a predetermined value, and from the comparison result, the stoppage of the second clock signal is detected, and from the count-up signal, it is possible to detect an abnormality in the central processing unit including a runaway of the program. A failure detection circuit for an information processing device, characterized in that it detects a stoppage of a first clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4342484U JPS60158248U (en) | 1984-03-28 | 1984-03-28 | Failure detection circuit for information processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4342484U JPS60158248U (en) | 1984-03-28 | 1984-03-28 | Failure detection circuit for information processing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60158248U true JPS60158248U (en) | 1985-10-21 |
Family
ID=30555078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4342484U Pending JPS60158248U (en) | 1984-03-28 | 1984-03-28 | Failure detection circuit for information processing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60158248U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08115235A (en) * | 1994-10-14 | 1996-05-07 | Honda Motor Co Ltd | Abnormality detector for controller and method therefor |
-
1984
- 1984-03-28 JP JP4342484U patent/JPS60158248U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08115235A (en) * | 1994-10-14 | 1996-05-07 | Honda Motor Co Ltd | Abnormality detector for controller and method therefor |
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