JPS60164250U

JPS60164250U - Control computer failure monitoring device

Info

Publication number: JPS60164250U
Application number: JP4654184U
Authority: JP
Inventors: 進寺西; 高見　勲
Original assignee: 三菱重工業株式会社
Priority date: 1984-03-30
Filing date: 1984-03-30
Publication date: 1985-10-31

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図〜第３図は従来例を示す図で、第１図は従来の故
障監視装置の構成を示す系統図、第２図はタイマ回路の
動作タイミングを示す図、第３図は制御プログラムの一
例を示す流れ図、第４図〜　　　゛第８図は本考案の一
実施例を示す図で、第４図は一構成を示すブロック図、
第５図はラッチ機能付タイマの基本動作のタイミングを
示す図、第６図は故障検出用の信号を出力する部分を含
む制御プログラム中ムす流れ図、第７図は正常動作時の
各部動作のタイミングを示す図、第８図は異常発生時の
各部動作のタイミングを示す図′である。１０・・・・・・制御用計算機、１１・・・・・・出力
ポート、１２ａ、１２ｂ、１２ｃ・・・・・・ラッチ機
能付タイマ、１３・・・・・・アンド回路、１４・・・
・・・入力ポート、１５・・・・・・表示装置。第５図　− Ｔｉ　２−下一一一一一一−ＴＴＴｘ−一丑（ａ）Ｒ，−＋　　　−−−−−ニーーー□ｉ−−７−
−−−一一−−−二ｙ７７″″Ｘ二（ｂ）　　　Ｒ，：
　　　　　　　　　　　　−−−−−二−−−１−−Ｏ
ＵＴｕ−−二−督−二二二二 □ｉ　　　’−−−　−−−″−−−−−−二ｙ（・）
Ｒｉ−ｊＴ −８゜□−「−一一一］ト一り一一一一一一」Figures 1 to 3 are diagrams showing conventional examples. Figure 1 is a system diagram showing the configuration of a conventional failure monitoring device, Figure 2 is a diagram showing the operation timing of a timer circuit, and Figure 3 is a control program. Flowcharts showing an example, FIG. 4 to FIG. 8 are diagrams showing an embodiment of the present invention, and FIG. 4 is a block diagram showing one configuration,
Figure 5 is a diagram showing the timing of the basic operation of the timer with latch function, Figure 6 is a flowchart of the control program including the part that outputs a signal for failure detection, and Figure 7 is a diagram showing the operation of each part during normal operation. FIG. 8 is a diagram illustrating the timing of the operation of each part when an abnormality occurs. 10... Control computer, 11... Output port, 12a, 12b, 12c... Timer with latch function, 13... AND circuit, 14...・
...Input port, 15...Display device. Fig. 5 - Ti 2-Lower 11111-TTTx-One Ushi (a) R, -+ -------nee □i--7-
---11---2y77″″X2(b) R,:
------2--1--O
UTu--2-Director-2222□i '--- ---''---------2y(・)
Ri-jT -8゜□- "-111]Toichiri111111"

Claims

[Scope of utility model registration request]

In a failure monitoring device for a control computer that takes the form of periodic calculations, a detection output signal routine is provided corresponding to a plurality of detection output signal routines arranged in a program in the control computer in which a failure is detected and the same number of hardware signal outputs. a plurality of timers with latch functions, an AND circuit for obtaining a logical product of the outputs of these timers, and a display device that displays failure details based on the timer outputs. - Computer failure monitoring device.