JPS6015584A - Analogue electronic timepiece - Google Patents

Abstract

PURPOSE:To reduce current consumption during a hand motion stopped state, by cutting off the connection with a power source of a first circuit system containing an oscillator circuit during the hand motion stopped state while subjecting the frequency dividing circuit of the circuit system always connected to the power source to initial setting. CONSTITUTION:When a switch 25 is closed, the output of a chattering preventing circuit 11' comes to H and the frequency dividing circuits 5, 6 of a circuit system always connected to a power source is reset while a motor drive pulse and detection pulse forming circuit 16 and a motor driver and detection signal amplifier circuit 17 does not respond to be brought to a motion stopped state. At the same time, the output of a power source change-over control circuit 18 changes to L and N type transistors 19, 20 are turned OFF while a P type transistors 21 is turned ON and the connection of a low constant voltage circuit 4 and a low voltage operation part 3 containing an oscillator 1 are cut off. By this mechanism, even in a power-saving type timepiece of a step motor correcting drive system, only a small current or a leak current consumed by the circuit 4 and a pull-down resistor 7 come to a consumed current and current consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for reducing power consumption when an analog electronic timepiece is in a state where hand movement is stopped.

In recent years, there have been many complaints in the market that the period from the time a watch is purchased to the end of its battery life is short due to power consumption during distribution and inventory. For analog electronic watches, a well-known method for saving power during distribution and inventory is to stop the movement of the hands of the analog electronic watch and stop the operation of the step motor. However, with the invention of a correction drive system for step motors, it is no longer possible to achieve the same power saving effect as in the past even when the hand movement is stopped, especially in two-hand analog electronic watches such as 20-second movement and 1-minute movement. In fact, there is a possibility that a large amount of electricity will be consumed even when the hands are moving.

The above-mentioned drawbacks will be explained in detail using FIG.

Figure 1 shows two models that have introduced a step motor correction drive system.
This is an example of a circuit configuration of an analog electronic watch with a 0-second movement.

Each component in FIG. 1 will now be described in detail.

In FIG. 1, an oscillation circuit 1 is composed of an inverter for oscillating an ultra-small level oscillator, a phase shifting resistor, a capacitor, etc., and generates a signal φ5hr2s7h of 32768 Hz.

The frequency dividing circuit 2 sequentially divides the signal φ:H768 to 2048
Outputs a Hz signal φ2o48.

Reference numeral 6 indicates a low constant voltage operation section, which operates with the voltage (VDD-VSL) supplied from the low constant voltage circuit 4. Although not shown, parts other than the low-voltage moving part are directly connected to the battery voltage (VDD-V
SEI). In this example, a silver oxide battery is used as the battery, and (VDD-VSEI) is 1.58
It is V. Also, the low constant voltage (VDD-Vsn) is 1.1
It is set to V.

The frequency dividing circuit 5 sequentially divides the signal φ2o48 to 1. H2
In addition to outputting the signal φ1, the chattering prevention circuit 1
128Hz synchronization signal WR used in 1.

In addition, a motor drive pulse forming and detection pulse forming circuit 16
Forms and outputs various frequency signals used in

The switch 25 is an external operating member (in this embodiment, the first stage, the second stage
It is linked to the stage (with two states) and closes when the stage is in the second stage.

Note that in the second stage of the stage, the watch does not stop moving, but the position of the hour and minute hands can be corrected by rotating the stage.

N-type MO8) Langstaff and 8 connect the Res terminal to VSS
Please pull down to Fr, Tr', 7 is always ONL, T
r, 8 is turned ON only when switch 25 is opened. In this embodiment, Tr, 7. The ON resistance value of 'J'r, 8 is 30. It is set to MΩ and 100 to Ω, and when the switch 25 is open, 'rr and 8 are turned on, so it is resistant to noise. When the switch 25 is closed, Tr and 8 are turned off, so it is connected from the Res terminal. The inflow current flows only to Tr 7, and its value is extremely small (LO5μA).

9.10 is an inverter.

The chattering prevention circuit 11 forms each signal shown in the timing chart of FIG. 2 from the waveform generated at the RθS terminal by opening and closing the switch 25.

The frequency dividing circuit 6 divides the signal φ into 1/2 to 1/2.
Outputs °Hz signal φ〆0.

The frequency dividing circuit 12 further divides the signal φL/(,2o into X6G and outputs the signal φ〆zoo.

13 is the %amp down counter, its contents (α
. β, γ) are the signals N output from the rotation detection circuit 14
The signal φ"A2oo 1c, which is amplified by r and outputted from the branch circuit 12, goes down by 9.

The motor drive pulse and detection pulse forming circuit 15 generates a normal drive pulse 21m, a correction drive pulse P2°, a drive pulse P3 when detecting an alternating magnetic field. An alternating current magnetic field detection pulse SPl and a rotation detection pulse SPz are generated once every 20 seconds at the timing shown in FIG. 6. Normal drive pulse Pl is 2.44m5 to 4.15m5
8 types (PI a,
~plh) are prepared, and one of them is output according to the contents (α, β, γ) of the amplifier down counter 16. The correction drive pulse P2 is set so that the steng motor always rotates, and is output whenever the steng motor does not rotate with the normal drive pulse Pl and the rotation detection circuit 14 outputs the signal Nr. AC magnetic field detection circuit 15
When an alternating current magnetic field is detected and signal Mf is output, alternating current IMf and magnetic field detection drive pulse P3 are output instead of normal drive pulse P1, and rotation detection pulse SP2 and correction drive pulse P2 are not output.

The main components of the motor driver and detection signal amplification circuit 17 are shown in FIG. In this configuration, P-type MO8Tr, 4
The inputs of 1 and 43 and NgM OS Tr, 42 and 44 are separated respectively, and the Tr of 41 to 44 are OF at the same time.
Detection resistors 47, 48 for detecting rotation and non-rotation of the steng motor, and P-type MQSTr 45, 4 for swifting these resistors.
It has 65.

Each pulse output from the motor drive pulse and detection pulse forming circuit 16 is decoded and inputted to the input terminal of the valley Tr as shown in FIG. With this configuration, it is possible to extract as a voltage value the difference between the induced current flowing in the coil 49 of the step motor due to an alternating current magnetic field, and the induced current flowing in the F coil 49 due to the rotano vibration of the step motor after normal drive Hals Pl is applied. can.

The rotation detection circuit 14 generates a voltage at the output terminal O1 (or .2) using the 1g1 rotation detection pulse sP2. SP2
is compared with the preset voltage Vcomp, and Vs
p2 (Vcomp, it is determined that the step motor has not rotated, and a signal Nrf is output.

The alternating current magnetic field detection circuit 15 detects a voltage vsp1 generated at the output terminal O1 (or 02) by the alternating current magnetic field detection pulse light.
and the preset voltage VXNV, vsp
l) When VINV, it is determined that an alternating magnetic field is being generated and a signal Mfi is output.

This completes the explanation of each component in FIG. 1, and next, the operation of FIG. 1 will be explained.

In FIG. 1, when switch 25 is open,
Signal SR output from chattering prevention (b) path 11
The logic state of 'Res' becomes 1L", the frequency dividing circuits 5, 6, and 12 each perform the normal frequency dividing operation, and the clock is in the wrong state. In this state, the normal drive pulse Pl
When the step motor cannot rotate due to this, the correction drive pulse P2 is supplied and the contents of the amplifier down counter -15 are incremented by 1, so the pulse width of the next normal drive pulse P1 is longer by a244 me9, and the step motor is It becomes easier to rotate. On the other hand, the normal drive pulse P
When the rotation continues for several steps, the content of the amplifier down counter 16 is decremented by 1 from the frequency dividing circuit 12 output signal φ"/32oo VC, and the pulse width of the normal drive pulse Pl becomes 0. 244ms Taff becomes shorter.

Through the above operations, the pulse width of the normal drive pulse P is
This is approximately the minimum pulse width that can drive the step motor in the current state, and the electric power for fully driving the step motor is always at an appropriate value. Furthermore, when an alternating current magnetic field is detected, the circuit 16 outputs the driving pulse P3, which is most likely to rotate in the father-flow field, instead of Pl, so that it operates stably even in the alternating current field. .

When the switch 25 is closed, chattering prevention (b) path 1
The logic state of the signals SR' and Res' output from 1 becomes ''H//, and the 64 F (z and subsequent frequency division stages of the frequency divider circuit 5, the frequency divider circuit 6, and the frequency divider circuit 12 are reset, Each output signal no longer leaks, and the clock stops operating.

When the switch 25 is opened again from this state, each branch station (B)
20 seconds after the clockwise cent state is released and the switch 25 is opened, VCI Ao is output from the frequency divider circuit 6, and the clock resumes its hand movement state.

This concludes the explanation of the operation shown in FIG.

In a watch that uses the correction drive system as shown in Figure 1, the length of the drive pulse during normal operation is affected by calendar loads, large internal resistance of the battery, and drop in can pressure at the end of its life. There is no need to include a margin, and the power required to drive the step motor, which conventionally required about 2 μW or more per step, is reduced to about 0.8 to 1.6 IiW. Especially for d1 at the time of 2 nails, if the correction drive method is adopted, the electric power required to drive the step motor is 5fCfAt, i(, Approximately 0.05~cLO5μA is sufficient for the current.
Even with the new 1fL, which uses a low constant voltage drive method, the V during normal operation is approximately 0.16μA,
Furthermore, when the hands are stopped, current also flows through the switch terminal resistor (Tr, 7 in FIG. 1), so there is a possibility that the current consumption will be higher than during normal operation. In this way, when returning to analog electronic watches that use a correction drive system, even if the hour i is stopped, it is no longer possible to obtain the power saving effect as in the past. In some cases, no power saving effect can be obtained at all, and on the contrary, even when the hands are moving, a large amount of power is required.

The present invention eliminates such drawbacks and its purpose is to:
By completely stopping the oscillation, the current consumption of the circuit when the analog electronic clock is in a stopped state is reduced, thereby increasing the power saving effect during the distribution and inventory period or during use, allowing users to use the analog electronic clock. It is advisable to lengthen the period.

The present invention will be described in detail below based on the embodiments shown in FIGS. 6 and 8.

Figure 6 is based on the first embodiment of the present invention.
, 21.1Km, a new force 1 was added to the cutting control rotation i'18'.
There are 1 shi.

Each component of %18 to 21 will be explained below. ′
The trace source switching control circuit 18 is a chattering prevention circuit 11'.
Signals RR' and Res' with higher output power and frequency dividing circuit 5
The output signal φ1 is output from the Tr. 19,20゜2
Signal ai to control switching of C1+03
Full output. (, f-signal cl, C2, C3 are output to signals φl, SR', Re'VC at the timing shown in FIG. 7. Tr, 19 is ONL when the logic state of signal C1 is 1''. In this state, the low constant voltage operating section 6 operates at a low abrasive pressure (VDD-4sL).Tr, 2D
is ONL when the logic state of the signal C2 is "H", and in this state, the low constant voltage operating section 6 directly controls the battery voltage (VDD-VS
S). Tr. 21, the logic state of signal C3 is 1
It turns on when the voltage is L", and in this state, there is no potential difference between (g) and (→ of the low constant voltage operating section 6, and the low constant voltage operating section 6 does not operate.

Now that the valley components 18 to 21 have been explained, the operation of FIG. 6 will be explained.

In FIG. 6, when the switch 25 is closed, the chatter link prevention circuit 11' outputs a signal S_R/.

Res' becomes 1H". This causes the υ frequency divider circuit 5°6.
When the clock hits 12 cents, the clock stops moving. Furthermore, the power supply switching control circuit 18. c) Output signal C□,
Both C2 and 03 become ゞL //, Tr, 19
and 20 are turned off, and Tr and 21 are turned on. Therefore, the low voltage operation section 6 is disconnected from the power supply, and the 1-frequency division of oscillation of this section is stopped. In this state, the oscillation circuit 1,
The current consumption of the frequency divider circuit 2 becomes 0, and since the frequency of driving the MOS Tr, which constitutes each circuit in other circuits, becomes 0, the current consumption is consumed by the low constant voltage circuit 4. Approximately 0.02 μ person, about 0.0 consumed by Tsuldakun resistance 7
In addition to 5 μA, the leakage current is approximately 0.01 μA.
The current consumed by the entire circuit is approximately 0.08μ.
Next to A.

When the switch 25 opens again, the anti-chattering circuit 11
The signal SR', Res' output from y' is 'L''
As a result, the frequency divider circuits 5, 6, and 12 are released from the reset state, and the signals C1*C2-C3 output from the power supply switching control circuit 18 are each 1L''.

H, El" Tr, 20 is turned on, and the low constant voltage operating section 6 is directly supplied with battery voltage (VDD-vss),
The clock will start moving. After 1+α (α is the oscillation start time) from the moment the switch 25 opens, the signal (3t,
C2,03 becomes that (REゝR",'L""H" and T
r, 19 is turned on, and the low constant voltage operation section 6 is supplied with a low constant voltage (
VDD-V8L) is supplied, and the circuit enters a normal operating state. Similarly, the oscillation start time α is determined by directly applying the battery's voltage (VDD-VSS) to the oscillation circuit 1 when the lock operation stop state is released.
) is supplied, so it becomes a small value within 0.2 seconds. Furthermore, if the ``DC amplification factor'' of the oscillation inverter is configured to be larger than the normal value while the signal C2 is ``R'', the value of α becomes even smaller.

This concludes the explanation of the operation shown in FIG.

When using the circuit shown in Figure 6, the current consumption when the hands are stopped is about 008 μA, which is compared to the current consumption of 0.17 μA when the hands are moving (about 004 μA for the STEP MOME and about 0.15 μA for the circuit). That's about 47 candies, so the power saving effect per 1 piece is very large. In the circuit shown in Fig. 6, the oscillation also stops when the time is adjusted, but since each frequency dividing circuit is at tt while the clock is not operating, the circuit enters the operating state and the first time from the furnace. Since the drive pulse is outputted after 20+α, accurate time adjustment is possible.

Next, a second embodiment will be explained with reference to FIG.

Fig. 8 is compared with Fig. 6, and shows that the '〆0 frequency divider circuit 6 has been removed and it has become a circuit for the button every second, and a new AND
Gate 22, A frequency dividing circuit 26, recent signal forming circuit 2
The tail is different in that 4 is added. The signal output from the recent signal forming circuit 24 is the signal SR↑,,s tl H/ output from the chattering prevention circuit 11''.
/, or when the signal Sc output from the external frequency dividing circuit 26 becomes ``H'', or when the signal BR↓ output from the chattering prevention circuit 11'' becomes ``H''. Sometimes it is 2H// and other times it is ``L//.

The operation of the VC shown in FIG. 8 will be explained below.

When the switch 25 is closed, the chattering prevention circuit 11''
When the signal BR+SR' output from F becomes "L" υ, the signal φl output from the frequency dividing circuit 5 is inhibited by the AND gate 22, and the motor drive pulse and detection pulse are no longer output from the circuit 16, E+f. becomes a continuous stop state. At the same time, the signal SR↑ causes the 1fVC7z9 frequency divider circuits 5 and 12 to be reset instantaneously! Then, the time elapsed after the switch 25 was closed begins to be counted. Father, Shie Frequency divider circuit 2
6 is released from the reset state because the signal S R', R, e 8' becomes 'L'' VC.

As shown in Figure 9, after the switch 25 is closed, Mi
When the J circuit 5 outputs 160 pulses of signal φl, the frequency divider circuit 1)2 outputs the signal φ'Ago, and the output signal SC of the differential frequency circuit 26 becomes もH//. The operation is similar to the circuit shown in the figure.

After the S・R border 25 is closed, the signal φl is output from the frequency dividing circuit 5.
When the switch 25 is opened before 160 shots are output, the output signal Sc of the A frequency dividing circuit 25 becomes jh.
In order to inherit L//, the signals 01 and C2*C3 output from the power switching control subcircuit are also IH//, respectively.
``L'' and ``H'' states are maintained, so the low constant voltage (vvD=v8L) continues to be supplied to the low constant voltage operating section 6,
The oscillation circuit 1 and the frequency dividing cap 2 continue to operate. In addition, the moment the switch 25 opens 'fc', the signal SR↓ goes to 1H'' and instantaneously resets the frequency divider circuits 5 and 12, so the first drive pulse is generated exactly 1 second after the 1 state is reached. Operate.

This concludes the explanation of the operation shown in FIG.

If the circuit is configured as shown in Figure 8, if the time is adjusted within 160 seconds, the oscillation will not stop even if the clock is stopped, so when the time adjustment is finished and the clock is returned to the operating state, it will be accurate. It is possible to create an analog electronic clock that turns on the button after 1 second and achieves a large power saving effect when the button is turned off for more than 160 seconds. Furthermore, in the configuration shown in FIG. 8, the frequency dividing circuit 12, which is originally phased for the correction drive system, is used as a counter for setting the time adjustment time, so the IC size does not need to be large. There is an advantage.

This concludes the description of the embodiment.

As described above, the analog electronic timepiece according to the present invention has a means for disconnecting the first circuit system including the oscillation circuit from the power supply when in the uncoupled stop state, and a second circuit that is always connected to the power supply. Is this an analog electronic watch that consumes very little power during υ hand movement using a correction drive method, etc., in order to provide a means to initialize the frequency dividing circuit included in the system? However, the time can be adjusted accurately, and the power saving effect is greatly increased as shown in Table 1, which has the advantage of extending the user's usage period as shown in Table 2. be.

Adjustment table: 22 years of usage period after hand movement is stopped (for battery capacity 4 mAh) In the same example, the state in which the crown is pulled out from the first click to the second click (time adjustment state) becomes the power saving state. However, a kakunter is provided that counts the signal formed by repeatedly pulling out and pushing in the crown within a short period of time (for example, 10 seconds), and the output signal of the kakunter is converted into the signal shown in Fig. 6. If the signal SC shown in FIG. 6 is used in an appropriate manner, it is possible to bring the first stage of the crown into a power saving state.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a configuration example of a conventional 2@''I analog electronic clock circuit, Fig. 2 is a timing chart of signals output from the chattering prevention circuit 11, and Fig. 6 is a motor drive pulse. and detection pulse forming circuit 1
6 is a timing chart of the signals output from 6, FIG. 4 is a diagram showing a configuration example of a motor driver and a detection signal amplification circuit, FIG. 5 is a timing chart of FIG. 4, and FIG.
FIG. 7 is a timing chart of the power supply switching control circuit 18. FIG. FIG. 8 is a diagram showing an example of the +h configuration of a six-button analog electronic watch circuit according to the present invention, and FIG. 9 is a timing chart diagram of FIG. 1... Oscillation circuit 2, 5.6.12... Frequency dividing circuit 6... Low voltage operating section 4... Low constant voltage circuit 7.8... Nru MOS transistor 9.10 . . . Inverter 11 . . Chattering prevention circuit 15 . . Un-a-down counter 14 . . . Rotation detection circuit 15 .・Motor driver and detection signal amplification circuit 18...Power supply switching control circuit 19.20...N type MOS transistor 21 River P
Type MOS I' transistor 22...AND gate 26...A frequency divider 24...Resent signal forming circuit

Claims (1)

[Claims] means for controlling a hand movement state and a hand movement stop state using a signal formed by the operation of an external operating member; a first circuit system that is disconnected from a power source during the hand movement stop state;
and a second circuit system that is always connected to the power supply regardless of the tilt operation state and the hand movement stop state, the first circuit system includes at least an oscillation circuit, and the second circuit system: An analog electronic timepiece characterized in that it includes a frequency dividing circuit that is initially set during the hand movement stop state.