JPS60155230U - programmable counter device - Google Patents
programmable counter deviceInfo
- Publication number
- JPS60155230U JPS60155230U JP4314184U JP4314184U JPS60155230U JP S60155230 U JPS60155230 U JP S60155230U JP 4314184 U JP4314184 U JP 4314184U JP 4314184 U JP4314184 U JP 4314184U JP S60155230 U JPS60155230 U JP S60155230U
- Authority
- JP
- Japan
- Prior art keywords
- count value
- target
- program
- target count
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Programmable Controllers (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案装置のハードウェア構成を示すブロック
図、第２図はユーザプログラムＲＡＭの内容を示すメモ
リマツプ、第３図はプログラムバンクの内容を示すメモ
リマツプ、第４図は共通ブロック図の内容を宗すメモリ
マツプ、第５図は操作部および表示部の外観構成を示す
正面図、第６図はワーキングＲＡＭの内容を示すメモリ
マツプ、第７図、第８図は本考案装置のシステムプロ
−グラム構成を示すフローチャート、第９図は本
考案装置を工作機械装置に一適用した場合のシステム構
成を示す了゛ロック図、第１０図はカウント完了信号の
出力態様を示すタイミングチャートである。
１・・・被カウント７メル支入力回路、２・・・ＣＰＵ
、３・・・制御信号入力回路、４・・・制御信号出力回
路、５・・・ユーザプログラムＲＡＭ、６・・・操作部
、７・・・表示部、８・・・ワーキンク玉ＡＭ、９・・
・ＲＯＭ、 ｌ Ｑ・・・工作機械、１１・・・プロ
グラマブル・カウンタ、装置、１２・・・種別検出器、
１３，１４・・・センサ、Ｗｏ、Ｗｌ、Ｗ２・・・ワー
ク。Fig. 1 is a block diagram showing the hardware configuration of the device of the present invention, Fig. 2 is a memory map showing the contents of the user program RAM, Fig. 3 is a memory map showing the contents of the program bank, and Fig. 4 is the contents of the common block diagram. Fig. 5 is a front view showing the external configuration of the operation section and display section, Fig. 6 is a memory map showing the contents of the working RAM, and Figs. 7 and 8 are system programs of the device of the present invention.
FIG. 9 is a block diagram showing the system configuration when the device of the present invention is applied to a machine tool, and FIG. 10 is a timing chart showing the output mode of the count completion signal. 1... Counted 7-mel branch input circuit, 2... CPU
, 3... Control signal input circuit, 4... Control signal output circuit, 5... User program RAM, 6... Operation section, 7... Display section, 8... Working ball AM, 9・・・
・ROM, l Q... Machine tool, 11... Programmable counter, device, 12... Type detector,
13, 14...Sensor, Wo, Wl, W2...Work.
Claims (1)
ント入力端子と； 外部制御対象に接続される複数９外部出力端子と； プログラムバンク指定情報が供給されるべき外部制御入
力端子と； 前記外部カウント入力端子に供給基れる被カウントパル
スをカウントするカウンタ手段と；目標カウント値が一
時記憶される目標カウント値一時記憶手段と； 前記カウンタ手段におけるカウント値と、前記目標カウ
ント値一時記憶手段に記憶された目標カウント値との一
致を判別する一致判別手段と；複数のプログラムバンク
を有し、かつ各プログラムバンクには各ステップ番号毎
に、／目標〃ウント値を記憶するための目標カラシト値
エリアと、／当該ステップの目標カウント値をカウント
完了した際に外部出力を発すべき出力端子を指定する情
報を記憶するための出力端子指定エリアとが少くとも設
けられたプログラム記憶部と１；前記一致判別手段づ目
標ワウンド値との一致ケ判別されるたびに、前記プログ
ラムバンク指定情報で指定されるプログラムバンクの目
標カウント値エリアの内容をステップ順に読出し、これ
により前記目標カウント値一時手段の内容番更新する目
標カウント値更新制御手段と； 前記一致判別手段で目標カウント値との一致が判別され
るたびに、前記プログラム記憶部の当該ステップに係わ
る出力端子指定エリアの情報に応じて、所定の信号形態
により当該する出力端子にカウント完了信号を出力する
出力制御手段と；、 前記プログラム記憶部の各エリア
に該当する情 、報を書込むための書込み制御手段と
からなることを特徴とするプログラマブル・カウンタ装
置。[Claims for Utility Model Registration] ゛ An external count input terminal connected to a pulse generation source to be counted; A plurality of nine external output terminals connected to an external control target; An external terminal to which program bank specification information is to be supplied a control input terminal; a counter means for counting pulses to be counted supplied to the external count input terminal; a target count value temporary storage means for temporarily storing a target count value; a count value in the counter means; a coincidence determination means for determining coincidence with a target count value stored in the count value temporary storage means; having a plurality of program banks, and each program bank stores a /target count value for each step number; A program that is provided with at least a target count value area for counting the target count value of the step, and an output terminal designation area for storing information that designates the output terminal that should output an external output when the target count value of the step is completed. storage unit; 1; each time the coincidence determination means determines whether or not there is a match with the target wound value, the content of the target count value area of the program bank designated by the program bank designation information is read out in step order; target count value update control means for updating the content number of the count value temporary means; each time the coincidence determination means determines a match with the target count value, information in an output terminal designation area related to the relevant step in the program storage unit; output control means for outputting a count completion signal to the corresponding output terminal in a predetermined signal format in accordance with the above; and write control means for writing information corresponding to each area of the program storage unit. A programmable counter device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4314184U JPS60155230U (en) | 1984-03-26 | 1984-03-26 | programmable counter device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4314184U JPS60155230U (en) | 1984-03-26 | 1984-03-26 | programmable counter device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60155230U true JPS60155230U (en) | 1985-10-16 |
| JPH0426884Y2 JPH0426884Y2 (en) | 1992-06-29 |
Family
ID=30554534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4314184U Granted JPS60155230U (en) | 1984-03-26 | 1984-03-26 | programmable counter device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60155230U (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5523559A (en) * | 1978-08-09 | 1980-02-20 | Toshiba Corp | Schedule operation control unit |
| JPS5611503A (en) * | 1979-07-11 | 1981-02-04 | Japan Atom Energy Res Inst | Control method of timing |
| JPS56137404A (en) * | 1980-03-28 | 1981-10-27 | Hitachi Ltd | Sequence controller |
| JPS5811810A (en) * | 1981-07-14 | 1983-01-22 | Matsushita Electric Ind Co Ltd | Cycle timer device |
-
1984
- 1984-03-26 JP JP4314184U patent/JPS60155230U/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5523559A (en) * | 1978-08-09 | 1980-02-20 | Toshiba Corp | Schedule operation control unit |
| JPS5611503A (en) * | 1979-07-11 | 1981-02-04 | Japan Atom Energy Res Inst | Control method of timing |
| JPS56137404A (en) * | 1980-03-28 | 1981-10-27 | Hitachi Ltd | Sequence controller |
| JPS5811810A (en) * | 1981-07-14 | 1983-01-22 | Matsushita Electric Ind Co Ltd | Cycle timer device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0426884Y2 (en) | 1992-06-29 |
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