JPS60154641A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS60154641A
JPS60154641A JP59011294A JP1129484A JPS60154641A JP S60154641 A JPS60154641 A JP S60154641A JP 59011294 A JP59011294 A JP 59011294A JP 1129484 A JP1129484 A JP 1129484A JP S60154641 A JPS60154641 A JP S60154641A
Authority
JP
Japan
Prior art keywords
metal
integrated circuit
aluminum
semiconductor integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59011294A
Other languages
Japanese (ja)
Inventor
Hiroshi Ishioka
石岡　浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59011294A priority Critical patent/JPS60154641A/en
Publication of JPS60154641A publication Critical patent/JPS60154641A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To improve the moisture resistance of a semiconductor integrated circuit device by coating a metal which is hardly corroded on the surface of an exposed aluminum wiring pattern when a bonding is completed, thereby preventing the aluminum from corroding. CONSTITUTION:When a semiconductor integrated circuit device is dipped in an electrolyte which contains the prescribed metallic ions at the bonding step completing time and electrically plated with a base ribbon as a cathode, the prescribed metal film 10 can be coated on the entire surface of the exposed metal. A metal which has an ionization trend lower than the aluminum is selected as the metal film to be coated, but since the ribbon is frequency formed of an alloy of nickel, tin, copper, silver or gold which has an ionization trend lower than it is desired. Since the surface of the exposed aluminum is coated with the metal 10 having lower ionization trend after the plating step, the possibility of disconnecting the metal wirings due to corrosion when moisture is invaded through resin after sealing with resin is very reduced.

Description

【発明の詳細な説明】 イ、産業上の利用分野 本発明は、半導体集積回路装置の耐湿性向上に関する。[Detailed description of the invention] B. Industrial application field The present invention relates to improving moisture resistance of semiconductor integrated circuit devices.

口、従来技術 プラスチックパッケージが半導体集積回路装置（ｊ（、
ＩＣ）の刺止材料として広範囲に使用されるにつれて、
ＩＣ素子の耐湿性向上が重要な問題となっている。これ
は、封止用の樹脂は、気密封止用のセラミックや金属と
異なり、本質的に水を通すため、侵入した水分が配勝利
料のアルミを腐食させ、アルミ配線の断線を引き起すた
めである。ＩＣ素子の表面は、一般にアルミ配線上にパ
ッシベーション膜をかぶせて、侵入した水分とアルミ配
線とが接触しないようにしているが、このパッシベーシ
ョン膜にクラック（ひび割れ）やピンホールなどがある
と、アルミ配線が鮎出し、そこからアルミの腐食が発生
する。さらに、ＩＣ素子とパッケージ端子とを接続する
だめのポンディングパッドには、バッジページＢ７膜を
かぶせていないため、アルミの腐食が発生してしまう。However, conventional plastic packages are used for semiconductor integrated circuit devices (j(,
As it has been widely used as a stabbing material for IC),
Improving the moisture resistance of IC devices has become an important issue. This is because sealing resin, unlike ceramics and metals for airtight sealing, inherently allows water to pass through, and the moisture that enters corrodes the aluminum of the distribution material, causing disconnection of the aluminum wiring. It is. On the surface of an IC element, a passivation film is generally placed over the aluminum wiring to prevent intruding moisture from coming into contact with the aluminum wiring. However, if there are cracks or pinholes in this passivation film, the aluminum Wiring comes out and the aluminum begins to corrode. Furthermore, since the bonding pad that connects the IC element and the package terminal is not covered with the Badge Page B7 film, corrosion of the aluminum occurs.

パッシベ−ジョン膜のクラックやピンホールは、パッシ
ベーション膜の材質や被着方法を改善する事で発生を低
減する事は可能であるが、ボンディングバソド部は必然
的にパッシベーション膜からアルミがむき出てＬまう小
になる。Although it is possible to reduce the occurrence of cracks and pinholes in the passivation film by improving the material and attachment method of the passivation film, aluminum inevitably comes out from the passivation film at the bonding bath. L becomes small.

ハ１発明の目的 本発明は、これらの問題点を解決し、耐湿性を向上させ
た半導体集積回路装置を提供することを目的とする。C.1 Objective of the Invention The object of the present invention is to solve these problems and provide a semiconductor integrated circuit device with improved moisture resistance.

二６発明の構成 本発明によ′ｉｔば、半導体基板の一主面上に形成され
た半導体素子と、これら素子間を接続する金属配線層と
、前記半導体基板の一生＋ｒｌを穣うパッシベーション
膜とを有し、さらに前記配線層の６１■記パツシベーシ
ヨン膜から露出している部分が前記配線層の金属よりイ
オン化傾向の低い他の金属で櫟われた半導体集積回路装
置が得られる。26 Structure of the Invention According to the present invention, there is provided a semiconductor element formed on one main surface of a semiconductor substrate, a metal wiring layer connecting these elements, and a passivation film that covers the entire life of the semiconductor substrate. Further, a semiconductor integrated circuit device is obtained in which the portion of the wiring layer exposed from the passivation film No. 61 is made of another metal having a lower ionization tendency than the metal of the wiring layer.

ホ、実施例 つぎに本発明を実施例により説明する。E, Example Next, the present invention will be explained by examples.

第１図と第２図は、本発明の一実施例に係る、金属配線
層のパッシベーション膜からの露出部を他の金属膜で覆
う工程について説明するだめの部分断面図である。第１
図において、１は１ｃ素子をマウントした、ベースリボ
ンのアイランド部、２は同じベースリボンの内部リード
端子、３はアイランド１にマウントしたシリコン基板、
５はシリコン基板の一主面上に設けられた配線層のうち
ノホンティングパッドおよびそれにつながるアルミ配線
、６は内部のアルミ配線、７はアルミ配線を含むシリコ
ン基板の一生面を覆うパッシベーション膜、８／′ｉバ
ンシベーシヨン膜７Ｋ１４：、したクラックまたはピン
ホール、９はボンディングバノド５とリード端子２間を
接続するボンティング勝である０ プラスチックパッケージで用いるベースリボンは、１の
アイランドと、複数のリード端子２を含むリード＃ｉｌ
＋はすべてつながって一体に形成されている。従って、
ポンディング工程が終了した段階で、半導体集積回路装
置を所定の金属イオンを含む電解液に浸し、ベースリボ
ンを陰極として′電気メッキを行うと、露出した金Ｉ４
表面全部に、第２図に示す所定金属膜１０を被着する事
が出来る。FIGS. 1 and 2 are partial cross-sectional views illustrating a step of covering the exposed portion of the metal wiring layer from the passivation film with another metal film, according to an embodiment of the present invention. 1st
In the figure, 1 is the island part of the base ribbon on which the 1c element is mounted, 2 is the internal lead terminal of the same base ribbon, 3 is the silicon substrate mounted on the island 1,
5 is a nohonting pad and aluminum wiring connected thereto among the wiring layers provided on one main surface of the silicon substrate; 6 is internal aluminum wiring; 7 is a passivation film that covers the entire surface of the silicon substrate including the aluminum wiring; 8/'i banshibasion film 7K14: crack or pinhole, 9 is the bonding hole connecting between the bonding board 5 and the lead terminal 20 The base ribbon used in the plastic package has one island and a plurality of Lead #il including lead terminal 2
All + signs are connected and formed into a single piece. Therefore,
When the bonding process is completed, the semiconductor integrated circuit device is immersed in an electrolytic solution containing a predetermined metal ion, and electroplating is performed using the base ribbon as a cathode to remove the exposed gold I4.
A predetermined metal film 10 shown in FIG. 2 can be deposited on the entire surface.

ＰチャネルシリコンゲートのＭＯ８型集ｊｆｉ、回路を
例にとると、リード端子２から直接に電圧を印加さ几る
ボンティンダパソドのアルミ表面はもちろん、拡散ＩＶ
ｉ４　（Ｐ型）からシリコン基板３（Ｎ型）へと電流が
流れるため、拡散層と接続されている内部のアルミ配線
上で発生したクラックやピンホールによって露出したア
ルミ表面にも所定金属膜を被着する隼が出来る。電気メ
ソ上によって被りＨする金属膜としては、アルミよりイ
オン化傾向の低い金属を選ぶが、ベースリボンが鉄とニ
ッケルの合金で作ら几る事が多いため、それらより低い
イオン化傾向を侍つスズ（Ｓｎ）、銅（Ｃｕ　）　。Taking a P-channel silicon gate MO8 type circuit as an example, the aluminum surface of the bonding pad to which a voltage is directly applied from the lead terminal 2, as well as the diffused IV
Since current flows from i4 (P type) to silicon substrate 3 (N type), a prescribed metal film is also applied to the aluminum surface exposed by cracks and pinholes that occur on the internal aluminum wiring connected to the diffusion layer. A falcon is formed. For the metal film to be coated on the electrolyte layer, a metal with a lower ionization tendency than aluminum is selected, but since the base ribbon is often made of an alloy of iron and nickel, tin (which has a lower ionization tendency than aluminum) is selected. Sn), copper (Cu).

銀（Ａｇ）、金（Ａ、ｕ）等が望゛ましい。実用的には
、スズメッキであろう。メッキ工程後、語用していたア
ルミ表面は、イオン化ｉ頃向の低い金）ｆ４１゜で覆わ
れるため、樹脂封止後、樹脂を通って水分が侵入した場
合に腐食によって金属配線が断線する可能性は非常に小
さくなる。Silver (Ag), gold (A, u), etc. are preferable. Practically speaking, it would be tin plated. After the plating process, the aluminum surface is covered with gold (gold) with a low ionization rate, so if moisture enters through the resin after resin sealing, the metal wiring will break due to corrosion. The chances are very small.

へ８発明の効果 以上詳細に説明したように、本発明は、集積１回路装置
パッケージ組立途中のボンディング完了時に、露出して
いるアルミ配線パターン表面に腐食しにくい金属を被着
する事により、前記集積回路装置におけるアルミ腐食の
発生を防ぎ耐湿性を向上させるという効果が得られる。8. EFFECTS OF THE INVENTION As explained in detail above, the present invention provides the above-mentioned effects by depositing a corrosion-resistant metal on the exposed aluminum wiring pattern surface when bonding is completed during assembly of an integrated single circuit device package. The effects of preventing aluminum corrosion in integrated circuit devices and improving moisture resistance can be obtained.

なお、実施例に限らず、金属配線が外部端子と巾：気的
に直接または間接に接続されている検量の素子に広く適
用すると七ができる事は註うまでもない。It goes without saying that the invention can be applied not only to the embodiment but also to a wide range of calibration elements in which metal wiring is connected directly or indirectly to external terminals.

インク完了時の半導体集積回路装置の部分断面図、第２
図は第１図に引続いて電気メッキをほどこしたあとの半
導体集積回路装置の部分断面図である。Partial cross-sectional view of the semiconductor integrated circuit device when ink is completed, 2nd
This figure is a partial cross-sectional view of the semiconductor integrated circuit device after electroplating has been applied following FIG. 1.

１・゛゛ベースリボンアイランド、２・・・・・・ベー
スリボンの内部リード端子、３・・自・・シリコン基板
、４・・・・・・拡散層、５・・−・・・ボンディング
パノドとそれにつながるアルミ配線、６・・・・・・内
部のアルミ配線、７・・・・・・パッシベーション膜、
８・・団・パッシベーション膜に生じたクラック又はピ
ンホール、９・・・・・・ポンディング線、１０・・・
・・・電気メッキによって被着した金属層。1.Base ribbon island, 2.Base ribbon internal lead terminal, 3.Self silicon substrate, 4.Diffusion layer, 5.Bonding panode. and aluminum wiring connected to it, 6... internal aluminum wiring, 7... passivation film,
8... Cracks or pinholes generated in the passivation film, 9... Ponding lines, 10...
...A metal layer deposited by electroplating.

第１　凹 第２図1st concave Figure 2

Claims (1)

【特許請求の範囲】 １、　半導体基板と、その−主表面上に設けられた半導
体素子と、前記素子間を接続する金属配線層と、前記主
表面を傑うパッジページｑン膜とを有する半導体集積回
路装置において、前記金属配線層の前記パッシベーショ
ン膜から島田している部分が煎記配腺金属より゛もイオ
ン化傾向の低い他の金属膜で覆われている事ヲ特徴とす
る半導体集積回路装置。 ２、　上記金桝配＃Ｊ層の露出部を覆う他の金属膜は、
電気メッキによって被層されてなるものであることを特
徴とする特徴請求の範囲第１項記載の半導体集積回路装
置。[Claims] 1. A semiconductor substrate, comprising a semiconductor element provided on the main surface thereof, a metal wiring layer connecting the elements, and a pad page film extending over the main surface. A semiconductor integrated circuit device, characterized in that a portion of the metal wiring layer extending from the passivation film is covered with another metal film having a lower ionization tendency than the metal wiring. Device. 2. The other metal film covering the exposed part of the metal #J layer is
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is coated by electroplating.
JP59011294A 1984-01-25 1984-01-25 Semiconductor integrated circuit device Pending JPS60154641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59011294A JPS60154641A (en) 1984-01-25 1984-01-25 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59011294A JPS60154641A (en) 1984-01-25 1984-01-25 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS60154641A true JPS60154641A (en) 1985-08-14

Family

ID=11773972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59011294A Pending JPS60154641A (en) 1984-01-25 1984-01-25 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS60154641A (en)

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