JPH04174546A - Manufacture of semiconductor lead frame - Google Patents

Manufacture of semiconductor lead frame

Info

Publication number
JPH04174546A
JPH04174546A JP2301696A JP30169690A JPH04174546A JP H04174546 A JPH04174546 A JP H04174546A JP 2301696 A JP2301696 A JP 2301696A JP 30169690 A JP30169690 A JP 30169690A JP H04174546 A JPH04174546 A JP H04174546A
Authority
JP
Japan
Prior art keywords
lead frame
layer
thickness
plating
substratum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2301696A
Other languages
Japanese (ja)
Inventor
Takafumi Morikawa
貴文 森川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP2301696A priority Critical patent/JPH04174546A/en
Publication of JPH04174546A publication Critical patent/JPH04174546A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent diffusion of substratum metal, by forming a substratum layer of 0.05-2.0mum in thickness in a specified region of a metal lead frame main body, by Ni-plating process using sulfamic acid Ni plating bath, and forming a noble metal layer on the substratum layer. CONSTITUTION:In a specified region of a metal lead frame main body having leads and pad parts, an Ni substratum layer of 0.05-2.0mum in thickness is formed by Ni-plating process using sulfamic acid Ni plating bath. In the case where the substratum layer is thinner than 0.05mum, the number of pin holes increases, and corrosion and diffusion of substratum metal can not be restrained. In the case where the thickness exceeds 2.0mum, cracks are generated in the substratum layer at the time of bending process. The thickness is desirable to be 0.2-1.0mum. After that, by Pd-plating process on the Ni substratum layer, a noble metal layer is formed of 0.2mum in thickness, and a lead frame is formed. Thereby excellent bondability and soldeability can be realized.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は、電子部品を実装するための半導体リードフレ
ームの製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor lead frame for mounting electronic components.

[従来の技術〕 一般に、トランジスタ、IC等の電子部品を実装する基
体として金属製のリードフレームが使用されている。こ
のリードフレームは、第1図に示すように構成されてい
る。図中1は、リードフレームを示す。リードフレーム
1は、バラ)’部10゜複数のインナーリード11、複
数のアウターリード12、およびインナーリード11と
アウターリード12とを連結して支持するタイバ一部1
3からなっている。複数のインナーリード11は、パッ
ド部10の周囲に互いに離隔して配置されており、パッ
ド部10上にダイボンディングされたSiチップ等の半
導体チップ14の電極パッド(図示せず)とワイヤボン
ディングにより電気的に接続される。アウターリード1
2は、素子が実装される基体の導電部分と半田付けによ
り電気的に接続される。このようなリードフレームは、
通常Fe−Ni合金やCu合金からなる金属板状材にプ
レス加工やエツチング処理を施し所定形状のリードフレ
ーム本体(以下、基体と称す)を作製し、半導体チップ
14がダイボンディングされるパッド部10および半導
体チップ14の電極パッドとワイヤボンディングされる
インナーリード11に酸化防止のためにAg等の貴金属
を厚さ3〜5μmで部分的にメッキすることによって製
造される。
[Prior Art] Generally, a metal lead frame is used as a base on which electronic components such as transistors and ICs are mounted. This lead frame is constructed as shown in FIG. In the figure, 1 indicates a lead frame. The lead frame 1 includes a separate part 10, a plurality of inner leads 11, a plurality of outer leads 12, and a tie bar portion 1 that connects and supports the inner leads 11 and the outer leads 12.
It consists of 3. The plurality of inner leads 11 are arranged around the pad part 10 at a distance from each other, and are connected by wire bonding to electrode pads (not shown) of a semiconductor chip 14 such as a Si chip die-bonded onto the pad part 10. electrically connected. Outer lead 1
2 is electrically connected to the conductive portion of the base on which the element is mounted by soldering. This kind of lead frame is
A lead frame main body (hereinafter referred to as a base body) having a predetermined shape is produced by press working or etching a metal plate material usually made of Fe-Ni alloy or Cu alloy, and a pad portion 10 to which a semiconductor chip 14 is die-bonded. It is manufactured by partially plating the inner leads 11 to be wire-bonded to the electrode pads of the semiconductor chip 14 with a noble metal such as Ag to a thickness of 3 to 5 μm to prevent oxidation.

第2図に示すような電子部品をリードフレームを用いて
組み立てる場合、以下のようにして行われる。
When assembling an electronic component as shown in FIG. 2 using a lead frame, it is performed as follows.

まず、接着剤20を用いてパッド部10上に半導体チッ
プ14をダイボンディングする。次いで、半導体チップ
14上にあらかじめ形成された電極バッド21とインナ
ーリード11をA u SA 1、Cuからなるワイヤ
22によりワイヤボンディングする。次いで、エポキシ
樹脂等の封止樹脂23によりボンディング部分を封止す
る。次いで、アウターリード12の半田付は性を向上さ
せるために、アウターリード12に5n−Pbメッキを
施す。その後、タイバ一部13を切断し、パリとりを行
い、アウターリード12に曲げ加工を施す。
First, the semiconductor chip 14 is die-bonded onto the pad section 10 using the adhesive 20. Next, the electrode pads 21 previously formed on the semiconductor chip 14 and the inner leads 11 are wire-bonded using wires 22 made of A u SA 1 and Cu. Next, the bonding portion is sealed with a sealing resin 23 such as epoxy resin. Next, in order to improve the soldering properties of the outer leads 12, the outer leads 12 are plated with 5n-Pb. Thereafter, the tie bar part 13 is cut, the edges are removed, and the outer lead 12 is bent.

このようにして製造された電子部品は、プリント配線基
板上に半田付けにより実装される。
The electronic components manufactured in this way are mounted on a printed wiring board by soldering.

この組み立てにおいて、アウターリード12へのメッキ
は通常溶融メッキまたは電気メッキにより行われる。溶
融メッキを用いる場合は、浴温度が240〜300℃と
非常に高いのでメッキ中にヒートショックを受けて封止
樹脂とリードフレームとの間に細かい間隙が生じる。ま
た、電気メ・ツキを用いる場合は、アルカリ性または酸
性の溶液に浸漬されるので封止樹脂中にイオンが侵入し
てしまい、このイオンがワイヤや電極パッドを腐食させ
てしまう。このため、いずれのメッキ方法を用いても部
品の信頼性が低下するという問題がある。
In this assembly, the outer leads 12 are usually plated by hot-dip plating or electroplating. When hot-dip plating is used, the bath temperature is very high at 240 to 300° C., so heat shock occurs during plating, resulting in small gaps between the sealing resin and the lead frame. Furthermore, when using electric metal, ions enter the sealing resin because they are immersed in an alkaline or acidic solution, and these ions corrode the wires and electrode pads. Therefore, no matter which plating method is used, there is a problem in that the reliability of the parts decreases.

この問題を解決するために、最初にアラターリ−F 1
21: S n −P bの電気メッキを施す方法があ
る。しかしながら、この場合は後工程であるボンディン
グ工程における加熱によりSnもしくは5n−Pbのメ
ッキ層が溶融したり、リードフレーム材料(基体)EC
uを使用したときにはメ・ツキ層の5n−PbとCuが
互いに拡散してSnとCuとの化合物を形成し、半田付
は性を劣化させてしまう。
In order to solve this problem, first Aratari-F 1
21: There is a method of applying Sn-Pb electroplating. However, in this case, the Sn or 5n-Pb plating layer may melt due to heating in the bonding process, which is a subsequent process, or the lead frame material (substrate) EC may melt.
When U is used, 5n-Pb and Cu in the metal layer diffuse into each other to form a compound of Sn and Cu, resulting in poor soldering properties.

そこで、特開昭59−168659号公報、特開昭63
−2358号公報、および特開平2−42753号公報
において、貴金属としてPdをメッキ等により被着した
リードフレームが提案されている。Pdは空気中で安定
であるため酸化しにくく、しかも熱拡散をほとんど起こ
さない。したがって、Pdをリードフレーム本体に被着
することにより、リードフレームに必要とされる優れた
ボンディング性、半田付は性、および樹脂密着性等を達
成させることができる。この結果、従来の高度な技術を
要するAgスポットメッキ(部分的メッキ)等を施す必
要がなくなる。また、アウターリードに半田付は性を向
上させるための5n−pbメッキを施す必要もなくなる
Therefore, Japanese Patent Application Laid-open No. 59-168659, Japanese Patent Application Laid-open No. 63
In JP-A-2358 and JP-A-2-42753, a lead frame is proposed in which Pd is coated as a noble metal by plating or the like. Since Pd is stable in air, it is difficult to oxidize and also hardly causes thermal diffusion. Therefore, by applying Pd to the lead frame body, it is possible to achieve the excellent bonding properties, soldering properties, resin adhesion, etc. required for the lead frame. As a result, there is no need to perform Ag spot plating (partial plating), etc., which requires conventional advanced technology. Furthermore, it is no longer necessary to apply 5N-PB plating to the outer leads to improve solderability.

しかしながら、Pdは非常に高価であるので、できるだ
けPd層の厚さを薄くすることが望まれている。そのた
めには基体金属の腐食を防止するための下地層が必要で
ある。そこで、Pd層の下にNi下地層を設けてPd層
の厚さを薄くすると共に基体金属の腐食を防止している
。従来、このNi下地層を設ける際には、ワット浴が使
用されている。
However, since Pd is very expensive, it is desired to reduce the thickness of the Pd layer as much as possible. For this purpose, a base layer is required to prevent corrosion of the base metal. Therefore, a Ni underlayer is provided under the Pd layer to reduce the thickness of the Pd layer and to prevent corrosion of the base metal. Conventionally, a Watts bath has been used when providing this Ni underlayer.

[発明が解決しようとする課題] しかしながら、ワット浴を用いて形成したNi下地層は
、ピンホールが多いので基体金属の腐食を充分に防止す
ることができない。また、特に、前記基体金属にCuま
たはCu合金を用いた場合は、Niメッキ膜のピンホー
ルを通してPdメッキ浴中にCuが腐食溶解し、そのC
uイオンが局部電池作用により、Pdに引き寄せられて
Pd層内にCuの腐食生成物が生じる。このCu腐食生
成物は半田付は性やボンディング性を劣化させる。
[Problems to be Solved by the Invention] However, the Ni underlayer formed using a Watts bath has many pinholes and cannot sufficiently prevent corrosion of the base metal. In particular, when Cu or Cu alloy is used as the base metal, Cu corrodes and dissolves in the Pd plating bath through pinholes in the Ni plating film, and the C
U ions are attracted to Pd due to the local battery action, producing corrosion products of Cu within the Pd layer. This Cu corrosion product deteriorates soldering and bonding properties.

ピンホールの発生を防止するためにNi下地層の厚さを
厚くすると、アウターリードに曲げ加工を施す時にクラ
ックが発生するという問題がある。・本発明はかかる点
に鑑みてなされたものであり、基体金属の腐食や基体金
属イオンの拡散を充分に防止することができ、アウター
リードに曲げ加工を施す際のクラックの発生を防止し、
しかも、優れたボンディング性、半田付は性、および樹
脂密着性を発揮することができるリードフレームを得る
ことができる半導体リードフレームの製造方法を提供す
ることを目的とする。
If the thickness of the Ni underlayer is increased to prevent the formation of pinholes, there is a problem in that cracks occur when the outer lead is bent. - The present invention has been made in view of these points, and can sufficiently prevent corrosion of the base metal and diffusion of base metal ions, prevent the occurrence of cracks when bending the outer lead,
Moreover, it is an object of the present invention to provide a method for manufacturing a semiconductor lead frame that can produce a lead frame that exhibits excellent bonding properties, soldering properties, and resin adhesion.

[課題を解決するための手段] 本発明は、リードおよびパッド部を有する金属製のリー
ドフレーム本体の所定の領域にスルファミン酸Ni浴を
用いたNiメッキ処理により厚さ0.05〜2.0μm
のNi下地層を設け、次いで、該Ni下地層上に貴金属
層を設けることを特徴とする半導体リードフレームの製
造方法を提供する。
[Means for Solving the Problems] The present invention provides Ni plating treatment using a Ni sulfamate bath on a predetermined region of a metal lead frame body having leads and pad portions to a thickness of 0.05 to 2.0 μm.
Provided is a method for manufacturing a semiconductor lead frame, characterized in that a Ni underlayer is provided, and then a noble metal layer is provided on the Ni underlayer.

ここで、Ni下地層の厚さは0.05〜2.0μmに設
定する。これは、Ni下地層の厚さが0.05μm未満
であるとNi下地層にピンホールが多くなり、基体金属
の腐食や拡散を充分に抑制できず、Ni下地層の厚さが
2.0μmを超えると曲げ加工を施した際にNi下地層
にクラックが発生するからである。特に好ましくは、N
i下地層の厚さは0.2〜1.0μmである。
Here, the thickness of the Ni underlayer is set to 0.05 to 2.0 μm. This is because if the thickness of the Ni base layer is less than 0.05 μm, there will be many pinholes in the Ni base layer, and corrosion and diffusion of the base metal cannot be sufficiently suppressed. This is because if it exceeds this, cracks will occur in the Ni underlayer when bending is performed. Particularly preferably, N
The thickness of the i-base layer is 0.2 to 1.0 μm.

貴金属層の貴金属としては、Pd以外にAu。The noble metal of the noble metal layer includes Au in addition to Pd.

Ag、Pt等の貴金属を用いることができる。この貴金
属をNi下地層に被着する方法としては、通常用いられ
る電気メッキ法、無電解メッキ法等を用いることができ
る。
Noble metals such as Ag and Pt can be used. As a method for depositing this noble metal on the Ni underlayer, a commonly used electroplating method, electroless plating method, etc. can be used.

スルファミン酸Ni浴の液組成としては、例えば、スル
ファミン酸Ni200〜700g/i!。
The liquid composition of the Ni sulfamate bath is, for example, 200 to 700 g/i of Ni sulfamate! .

塩化Ni5〜60g/it、ホウ酸30〜50g/gで
ある。この他にビット防止剤としてラウリル酸ナトリウ
ムを加えてもよい。
Ni chloride is 5 to 60 g/it, and boric acid is 30 to 50 g/g. In addition, sodium laurate may be added as a bit inhibitor.

スルファミン酸Ni浴を用いたNiメッキ処理の条件は
、液温か25〜70℃、pHが2.5〜4.5、電流密
度が2〜2OA/dm2であることが好ましい。これは
、この範囲外の条件でメッキ処理を施しても充分な特性
を有するNi下地層が得られないからである。なお、こ
れらのメッキ処理条件は、スルファミン酸Ni浴の液組
成に応じて適宜設定する。
The conditions for Ni plating using a Ni sulfamate bath are preferably a liquid temperature of 25 to 70°C, a pH of 2.5 to 4.5, and a current density of 2 to 2 OA/dm2. This is because even if plating is performed under conditions outside this range, a Ni underlayer with sufficient properties cannot be obtained. Note that these plating processing conditions are appropriately set according to the liquid composition of the Ni sulfamate bath.

[作用] 本発明の半導体リードフレームの製造方法によれば、金
属製のリードフレーム本体にスルファミン酸Ni浴を用
いたNiメッキ処理によりNi下地層を設け、次いで、
Ni下地層上に貴金属層を設ける。
[Function] According to the method for manufacturing a semiconductor lead frame of the present invention, a Ni base layer is provided on a metal lead frame body by Ni plating using a Ni sulfamate bath, and then,
A noble metal layer is provided on the Ni underlayer.

スルファミン酸Ni浴を用いたNiメッキ処理により得
られたNi被膜は、ワット浴を用いたNiメッキ処理に
よるNi被膜より延性があり、しかも表面に残留する応
力も小さい。したがって、アウターリードの曲げ加工に
よるクラックの発生を防止することができる。また、ス
ルファミン酸Ni浴を用いたNiメッキ処理により得ら
れたNi被膜は、結晶粒が緻密であるのでピンホールが
非常に少ない。このため、基体金属の腐食や貴金属層へ
の拡散を充分に防止することができる。
The Ni coating obtained by Ni plating using a Ni sulfamate bath is more ductile than the Ni coating obtained by Ni plating using a Watts bath, and the stress remaining on the surface is also smaller. Therefore, it is possible to prevent cracks from occurring due to bending of the outer lead. Further, the Ni film obtained by Ni plating using a Ni sulfamate bath has very few pinholes because the crystal grains are dense. Therefore, corrosion of the base metal and diffusion into the noble metal layer can be sufficiently prevented.

[実施例コ 以下、本発明の実施例について具体的に説明する。[Example code] Examples of the present invention will be specifically described below.

実施例1 まず、Cu−0,3Cr−0,25Sn −0,2Zn
合金条にプレス加工を施し、第1図に示す形状のDIP
(デュアルインラインパッケージ)型リードフレーム本
体を得た。次いで、このリードフレーム本体全面に液組
成がスルファミン酸Ni600g/#、塩化Ni10g
/it、ホウ酸40 g/l)であるスルファミン酸N
i浴を用いてNiメッキ処理を施し、厚さ0.2μmの
N1下地層を形成した。このとき、Niメッキ処理の条
件は、液温60℃、pH3、電流密度10A/d112
とした。その後、Ni下地層上にPdメッキ処理(日中
貴金属社製バラデックス110使用)を施し、厚さ0.
2μmの貴金属層を形成した。
Example 1 First, Cu-0,3Cr-0,25Sn-0,2Zn
The alloy strip is pressed to form a DIP with the shape shown in Figure 1.
(Dual inline package) type lead frame body was obtained. Next, the liquid composition was 600g/# of Ni sulfamate and 10g/# of Ni chloride on the entire surface of this lead frame main body.
/it, boric acid 40 g/l)
Ni plating treatment was performed using an i-bath to form an N1 base layer with a thickness of 0.2 μm. At this time, the conditions for Ni plating treatment were: liquid temperature 60°C, pH 3, current density 10A/d112
And so. After that, Pd plating treatment (using Varadex 110 manufactured by Nichiki Kikinzoku Co., Ltd.) was applied to the Ni base layer to a thickness of 0.
A 2 μm noble metal layer was formed.

このとき、Pdメッキ処理の条件は、液温60℃、pH
8,5、電流密度3 A / dg+2とした。このよ
うにして、リードフレーム(実施例1)を作製した。
At this time, the conditions for Pd plating treatment were: liquid temperature: 60°C, pH:
8,5, and the current density was set to 3 A/dg+2. In this way, a lead frame (Example 1) was produced.

その後、リードフレームのボンディング性、樹脂密着性
、曲げ加工時のNi下地層のクラック発生の有無、並び
に半田付は性を調べた。その結果を下記第1表に示す。
Thereafter, the bonding properties of the lead frame, resin adhesion, the occurrence of cracks in the Ni underlayer during bending, and soldering properties were examined. The results are shown in Table 1 below.

なお、ボンディング性はワイヤーの引張り試験により判
断し、ワイヤー破断の場合をO、ワイヤーが基板の界面
で剥離した場合をXとした。樹脂密着性は剪断強度によ
り判断し、Cu素材のみと比較して同等以上である場合
を01同等以下である場合をXとした。半田付は性は半
田の濡れ面積により判断し、95%以上の場合を019
5%未満の場合をXとした。曲げ加工時のクラックの発
生の有無は曲げ加工後のSEM観察により判断した。
Note that the bonding property was determined by a wire tensile test, and the case where the wire broke was rated O, and the case where the wire peeled off at the interface of the substrate was rated X. Resin adhesion was judged by shear strength, and when compared with Cu material only, cases where it was equivalent or higher were rated 0, and cases where it was equivalent or lower were rated X. The quality of soldering is judged by the wetted area of the solder, and if it is 95% or more, it is 019.
The case where it was less than 5% was designated as X. The presence or absence of cracks during bending was determined by SEM observation after bending.

実施例2〜4 Ni下地層の厚さを下記第1表に示す値にすること以外
は実施例1と同様にして実施例2〜4のリードフレーム
を作製した。
Examples 2 to 4 Lead frames of Examples 2 to 4 were produced in the same manner as in Example 1, except that the thickness of the Ni underlayer was set to the value shown in Table 1 below.

得られた実施例2〜4のリードフレームについて実施例
1と同様にボンディング性、樹脂密着性、曲げ加工時の
クラック発生の有無、並びに半田付は性を調べた。その
結果を下記第1表に併記する。
The lead frames of Examples 2 to 4 obtained were examined in the same manner as in Example 1 for bonding properties, resin adhesion, occurrence of cracks during bending, and soldering properties. The results are also listed in Table 1 below.

比較例1.2 Ni下地層の厚さを下記第1表に示す値にすること以外
は実施例1と同様にして比較例1.2のリードフレーム
を作製した。
Comparative Example 1.2 A lead frame of Comparative Example 1.2 was produced in the same manner as in Example 1 except that the thickness of the Ni underlayer was set to the value shown in Table 1 below.

得られた比較例1,2のリードフレームについて実施例
1と同様にボンディング性、樹脂密着性、曲げ加工時の
クラック発生の有無、並びに半田付は性を調べた。その
結果を下記第1表に併記する。
The resulting lead frames of Comparative Examples 1 and 2 were examined in the same manner as in Example 1 for bonding properties, resin adhesion, occurrence of cracks during bending, and soldering properties. The results are also listed in Table 1 below.

比較例3 Cu−0,3Cr−0,25Sn−0,2Zn合金条に
プレス加工を施し、第1図に示す形状のDIP型リード
フレーム本体を得た。次いで、このリードフレーム本体
全面に液組成が硫酸Ni250g/l)、塩化Ni50
g/#、ホウ酸40g/flであるワット浴を用いてN
iメッキ処理を施し、厚さ0.2μmのNi下地層を形
成した。このとき、Niメッキ処理の条件は、液温10
℃、pH4、電流密度3 A / di2とした。
Comparative Example 3 A Cu-0,3Cr-0,25Sn-0,2Zn alloy strip was pressed to obtain a DIP type lead frame body having the shape shown in FIG. Next, the entire surface of this lead frame body was coated with a liquid composition of Ni sulfate (250 g/l) and Ni chloride (50 g/l).
g/#, N using a Watts bath with boric acid 40 g/fl.
An i-plating process was performed to form a Ni underlayer with a thickness of 0.2 μm. At this time, the conditions for Ni plating treatment are as follows: liquid temperature: 10
°C, pH 4, and current density 3 A/di2.

その後、Ni下地層上にPdメッキ処理(日中貴金属社
製バラデックス110使用)を施し、厚さ0.2μmの
貴金属層を形成した。このとき、Pdメッキ処理の条件
は、液温60℃、pH8,5、電流密度3A/da2と
した。このようにして、リードフレーム(比較例3)を
作製した。
Thereafter, Pd plating treatment (using Varadex 110 manufactured by Nichi-Kizoku Kogyo Co., Ltd.) was performed on the Ni base layer to form a noble metal layer with a thickness of 0.2 μm. At this time, the conditions for the Pd plating treatment were a liquid temperature of 60° C., a pH of 8.5, and a current density of 3 A/da2. In this way, a lead frame (Comparative Example 3) was produced.

得られた比較例3のリードフレームについて実施例1と
同様にボンディング性、樹脂密着性、曲げ加工時のクラ
ック発生の有無、並びに半田つけ性を調べた。その結果
を下記第1表に併記する。
The resulting lead frame of Comparative Example 3 was examined in the same manner as in Example 1 for bonding properties, resin adhesion, occurrence of cracks during bending, and soldering properties. The results are also listed in Table 1 below.

比較例4〜6 Ni下地層の厚さを下記第1表に示す値にすること以外
は比較例3と同様にして比較例4〜6のリードフレーム
を作製した。
Comparative Examples 4 to 6 Lead frames of Comparative Examples 4 to 6 were produced in the same manner as Comparative Example 3 except that the thickness of the Ni underlayer was set to the value shown in Table 1 below.

得られた比較例4〜6のリードフレームについて実施例
1と同様にボンディング性、樹脂密着性、曲げ加工時の
クラック発生の有無、並びに半田付は性を調べた。その
結果を下記第1表に併記する。
The lead frames of Comparative Examples 4 to 6 obtained were examined in the same manner as in Example 1 for bonding properties, resin adhesion, occurrence of cracks during bending, and soldering properties. The results are also listed in Table 1 below.

第1表から明らかなように、本発明により得られたリー
ドフレーム(実施例1〜4)は、優れたボンディング性
、樹脂密着性、並びに半田付は性を発揮し、しかもアウ
ターリードの曲げ加工時にNi下地層にクラックは発生
しなかった。これに対して、本発明の範囲外のNi下地
層厚を有するリードフレーム(比較例1.2)、ワット
浴を用いた方法により得られたリードフレーム(比較例
3〜6)は、基体金属の腐食や基体金属イオンの拡散に
よりボンディング性および半田付は性が悪く、しかもア
ウターリードの曲げ加工においてNi下地層にクラック
が発生した。
As is clear from Table 1, the lead frames obtained according to the present invention (Examples 1 to 4) exhibit excellent bonding properties, resin adhesion properties, and soldering properties, and also exhibit excellent bending properties of the outer leads. No cracks occurred in the Ni underlayer. On the other hand, lead frames having a Ni underlayer thickness outside the range of the present invention (Comparative Example 1.2) and lead frames obtained by a method using a Watts bath (Comparative Examples 3 to 6) have a base metal Bonding and soldering properties were poor due to corrosion and diffusion of base metal ions, and cracks occurred in the Ni underlayer during bending of the outer leads.

[発明の効果] 以上説明した如く本発明の方法によると、基体金属の拡
散を充分に防止することができ、アウターリードに曲げ
加工を施す際のクラックの発生を防止し、しかも、優れ
たボンディング性、半田付は性、および樹脂密着性を発
揮することができるリードフレームを得ることができる
[Effects of the Invention] As explained above, according to the method of the present invention, it is possible to sufficiently prevent the diffusion of the base metal, prevent the occurrence of cracks when bending the outer lead, and achieve excellent bonding. It is possible to obtain a lead frame that exhibits good solderability, good solderability, and resin adhesion.

また、Ni下地層を設けることにより、貴金属層の厚み
が薄くなり経済性がよくなる。
Further, by providing the Ni underlayer, the thickness of the noble metal layer can be reduced and economical efficiency can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は半導体リードフレームの平面図、第2図は電子
部品の一例を示す断面図である。 1・・・リードフレーム、10・・・パッド部、11・
・・インナーリード、12・・・アウターリード、13
・・・タイバ一部、14・・・半導体チップ、20・・
・接着剤、21・・・電極パッド、22・・・ワイヤ、
23・・・封止樹脂。 出願人代理人 弁理士 鈴江武彦
FIG. 1 is a plan view of a semiconductor lead frame, and FIG. 2 is a sectional view showing an example of an electronic component. DESCRIPTION OF SYMBOLS 1... Lead frame, 10... Pad part, 11.
...Inner lead, 12...Outer lead, 13
...Part of tie bar, 14...Semiconductor chip, 20...
・Adhesive, 21... Electrode pad, 22... Wire,
23... Sealing resin. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

【特許請求の範囲】[Claims] リードおよびパッド部を有する金属製のリードフレーム
本体の所定の領域にスルファミン酸Ni浴を用いたNi
メッキ処理により厚さ0.05〜2.0μmのNi下地
層を設け、次いで、該Ni下地層上に貴金属層を設ける
ことを特徴とする半導体リードフレームの製造方法。
A Ni sulfamate bath was used to inject Ni into a predetermined area of a metal lead frame body having leads and pads.
A method for manufacturing a semiconductor lead frame, which comprises providing a Ni base layer with a thickness of 0.05 to 2.0 μm by plating, and then providing a noble metal layer on the Ni base layer.
JP2301696A 1990-11-07 1990-11-07 Manufacture of semiconductor lead frame Pending JPH04174546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2301696A JPH04174546A (en) 1990-11-07 1990-11-07 Manufacture of semiconductor lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2301696A JPH04174546A (en) 1990-11-07 1990-11-07 Manufacture of semiconductor lead frame

Publications (1)

Publication Number Publication Date
JPH04174546A true JPH04174546A (en) 1992-06-22

Family

ID=17900052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2301696A Pending JPH04174546A (en) 1990-11-07 1990-11-07 Manufacture of semiconductor lead frame

Country Status (1)

Country Link
JP (1) JPH04174546A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268132A (en) * 1993-03-16 1994-09-22 Mitsui High Tec Inc Lead frame for semiconductor device
EP0621633A2 (en) * 1993-04-10 1994-10-26 W.C. Heraeus GmbH Leadframe for integrated circuits

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268132A (en) * 1993-03-16 1994-09-22 Mitsui High Tec Inc Lead frame for semiconductor device
EP0621633A2 (en) * 1993-04-10 1994-10-26 W.C. Heraeus GmbH Leadframe for integrated circuits
EP0621633A3 (en) * 1993-04-10 1995-01-11 Heraeus Gmbh W C Leadframe for integrated circuits.
US5486721A (en) * 1993-04-10 1996-01-23 W.C. Heraeus Gmbh Lead frame for integrated circuits
JPH08111484A (en) * 1993-04-10 1996-04-30 W C Heraeus Gmbh Lead frame

Similar Documents

Publication Publication Date Title
JP3760075B2 (en) Lead frame for semiconductor packages
US7245006B2 (en) Palladium-spot leadframes for high adhesion semiconductor devices and method of fabrication
KR100381302B1 (en) Semiconductor device and manufacturing method thereof
KR0183645B1 (en) Semiconductor leadframe having composite plating
US7148085B2 (en) Gold spot plated leadframes for semiconductor devices and method of fabrication
CA2118758C (en) Lead frame for integrated circuits
JP2009526381A (en) Aluminum lead frame for semiconductor QFN / SON devices
US6706561B2 (en) Method for fabricating preplated nickel/palladium and tin leadframes
KR100275381B1 (en) Lead frame for semiconductor package and method for plating lead frame
JP2000269398A (en) Aluminum lead frame for semiconductor device and manufacture thereof
JP2925815B2 (en) Lead frame for mounting semiconductor chip and method of manufacturing the same
US5958607A (en) Lead frame for semiconductor device
JPH10284667A (en) Material for electric electronic device component having superior corrosion resistance and oxidation resistance
US20030137032A1 (en) Pre-finished leadframe for semiconductor devices and method fo fabrication
JPH07326701A (en) Conductive material for electric-electronic part, lead frame and semiconductor integrated circuit using the same
US6545342B1 (en) Pre-finished leadframe for semiconductor devices and method of fabrication
JPH11121673A (en) Lead frame
KR100378489B1 (en) Ag or Ag-alloy plated Lead frame for semiconductor package and the method of manufacturing the same
KR100998042B1 (en) A lead frame and the method for manufacturing semiconductor package comprising the same
JPH04174546A (en) Manufacture of semiconductor lead frame
JP3402228B2 (en) Semiconductor device having lead-free tin-based solder coating
KR100203334B1 (en) Multi-layer plateded lead frame
KR20030063835A (en) Multi-layer plating lead frame and method of manufacturing the same
KR100209264B1 (en) Semiconductor lead frame
JPH10284666A (en) Electronic component device