JPS60154582A - Hall element - Google Patents

Hall element

Info

Publication number
JPS60154582A
JPS60154582A JP59010458A JP1045884A JPS60154582A JP S60154582 A JPS60154582 A JP S60154582A JP 59010458 A JP59010458 A JP 59010458A JP 1045884 A JP1045884 A JP 1045884A JP S60154582 A JPS60154582 A JP S60154582A
Authority
JP
Japan
Prior art keywords
region
junction
schottky
bias voltage
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59010458A
Other languages
Japanese (ja)
Inventor
Hiroshi Morikawa
博司 森川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59010458A priority Critical patent/JPS60154582A/en
Publication of JPS60154582A publication Critical patent/JPS60154582A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00Hall-effect devices
    • H10N52/101Semiconductor Hall-effect devices

Abstract

PURPOSE:To prevent dispersion among elements or variation by a temperature by forming a Schottky junction or a P-N junction on an input current path and applying bias voltage to the junction from the outside. CONSTITUTION:A region 1 consists of an N type single crystal layer, and a region 2 is composed of a Schottky metal forming a Schottky junction with the region 1. A region 3 represents a depletion layer by the Schottky junction, and the thickness (l) of the region 3 can be changed by reverse bias voltage V applied from the outside. Consequently, the thickness d-l of a path for input currents I can be altered by reverse bias voltage, and Hall output voltage can be controlled by voltage V. The object can be attained even when a P layer is formed in place of the Schottky metal 2 at that time.

Description

【発明の詳細な説明】 (発明の技術分野) 本発明はホール素子の構造に関するものである。[Detailed description of the invention] (Technical field of invention) The present invention relates to the structure of a Hall element.

(従来技術) ホール素子は磁電変換素子としてV’l’R,プレーヤ
ー等に使用されるモーターに最近非常に多く使われてい
る。
(Prior Art) Hall elements have recently been widely used as magnetoelectric conversion elements in motors used in V'l'Rs, players, and the like.

ホール素子の形状は通常、第1図に示すように半導体を
十字形状に形成したもので、素子に垂直な外部磁場Bの
下で端部A−A’に入力電流を流すと端部C−C’にホ
ール出力電圧VHが得られる。この場fr、ホール出力
電圧VHの大きさは、よく知られ1いるように下式で表
わされる。
The shape of a Hall element is usually a cross-shaped semiconductor as shown in Fig. 1. When an input current is passed through an end A-A' under an external magnetic field B perpendicular to the element, an end C- Hall output voltage VH is obtained at C'. In this case, the magnitude of the field fr and the Hall output voltage VH is expressed by the following equation, as is well known.

””BI/eNd ここでBは外部磁場、■は入力電流、Nはキャリア濃度
、dは素子厚さ、eは電子の電荷量である。
BI/eNd Here, B is the external magnetic field, ■ is the input current, N is the carrier concentration, d is the element thickness, and e is the amount of electron charge.

通常出力電圧VHの大きさと入力抵抗あるいは消費TJ
L 力を考慮して、N−1×1011−3d=o、2〜
0.3μmK選ぶのが適当である。
Normal output voltage VH size and input resistance or consumption TJ
Considering L force, N-1×1011-3d=o, 2~
It is appropriate to choose 0.3 μmK.

しかしながら、実際の結晶製作の際には、濃度及び厚さ
がウェハー間はもちろんのことウェハー面内でもかなシ
ばらつき、この為前記の式からも明らかなように同一の
電流、磁場の下でも各素子によシ出力紙圧がかなシ違う
という事態が生ずる。
However, in actual crystal manufacturing, the concentration and thickness vary slightly not only between wafers but also within the wafer surface, so as is clear from the above equation, even under the same current and magnetic field, each A situation arises in which the output paper pressure varies depending on the element.

(発明の目的) 本発明の目的は出力電圧のバラツキの少いホール素子を
得る仁とにある。
(Object of the Invention) An object of the present invention is to obtain a Hall element with less variation in output voltage.

(発明の構成) 本発明によれは、入力電流通路上にシgyyトキ接合あ
るいはPN接合を設け、との接合に外部よりバイアス電
圧を加え素子の厚さdを加減することにより、出力電、
圧を一定としたホール素子を得る。かかるホール素子に
よれば濃度、厚さのばらつきによシ出力電圧が違ってく
るという従来の欠点を解消できる。
(Structure of the Invention) According to the present invention, an output current is
A Hall element with constant pressure is obtained. Such a Hall element can eliminate the conventional drawback that the output voltage varies depending on variations in concentration and thickness.

(発明の実施例) 以下、本発明と図面を参照してよシ詳細に説明する。(Example of the invention) Hereinafter, the present invention will be described in detail with reference to the drawings.

第2図は本発明の一実施例によるボール素子断面の略図
である。領域1は不純物濃度I X 101’13 ぼ のN型単結晶層であり領域2はN型単結晶層の領域
1とショットキー接合を形成するようなショットキーメ
タルである。領域3はショットキー接合による空乏層で
あり、この長さlは外部よシ印加する逆バイアス電圧V
によって変化させることがf%る。従って入力電流工の
通路の厚さd−jが、逆バイアス電圧によって可変であ
シ、前記式よシわかるようにホール出力電圧VHを外部
バイアス電圧■によって制御できることになる。
FIG. 2 is a schematic diagram of a cross section of a ball element according to an embodiment of the present invention. Region 1 is an N-type single crystal layer with an impurity concentration of about I x 101'13 , and region 2 is a Schottky metal that forms a Schottky junction with region 1 of the N-type single crystal layer. Region 3 is a depletion layer formed by a Schottky junction, and its length l is determined by the externally applied reverse bias voltage V.
It can be changed by f%. Therefore, the thickness d-j of the input current path can be varied by the reverse bias voltage, and as can be seen from the above equation, the Hall output voltage VH can be controlled by the external bias voltage (2).

本発明によるホール素子の実際の構造の平面を第3図に
示す。図中斜線で示した部分がショットキーメタルであ
る。辷れは上記説明から明らかなように入力電流通路の
うち、出力電圧を取り出す一部のみに形成すれば充分で
ある。ショットキーメタルの代わシにP層を形成しても
目的が達成されるととも上記説明から明白である。また
出力電圧の温度による変動も外部電圧によって補正でき
る。
A plan view of the actual structure of the Hall element according to the invention is shown in FIG. The shaded area in the figure is Schottky metal. As is clear from the above description, it is sufficient to form the sag only in the part of the input current path from which the output voltage is taken out. It is clear from the above description that the purpose can be achieved even if a P layer is formed instead of the Schottky metal. Furthermore, fluctuations in the output voltage due to temperature can be corrected by an external voltage.

以上のように本発明によればホール出力電圧を外部バイ
アス電圧によっ°C制御でき、素子間のばらつきあるい
は温度による変動を防ぐことができる。
As described above, according to the present invention, the Hall output voltage can be controlled by degrees Celsius using an external bias voltage, and variations between elements or variations due to temperature can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のホール素子を示す斜視図でおυ。 第2図は本発明の一実施例によるホール素子の断、、、
Tよ、あ、、□3よ。よ。−□6よ、オ □ニール素子
の斜視図である。 1・・・・・・N型単結晶層、2・・・・・・ショット
キメタル。 3・・・・・・空乏層。 代理人 弁理士 内 原 晋 h1図 筋1図 第3 図
Figure 1 is a perspective view of a conventional Hall element. FIG. 2 shows a cut-out of a Hall element according to an embodiment of the present invention.
T, ah, □3. Yo. -□6 is a perspective view of an O'Neill element. 1... N-type single crystal layer, 2... Schottky metal. 3... Depletion layer. Agent: Susumu Uchihara, Patent Attorney H1 Figure 1 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 入力電流通路の・一部にショットキ接合あるいはPN接
合を設け、該接合部にバイアス電圧を印加し前記入力電
流通路の厚さを変化させ得るようにしたことを特徴とす
るホール素子。
A Hall element characterized in that a Schottky junction or a PN junction is provided in a part of an input current path, and the thickness of the input current path can be changed by applying a bias voltage to the junction.
JP59010458A 1984-01-23 1984-01-23 Hall element Pending JPS60154582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59010458A JPS60154582A (en) 1984-01-23 1984-01-23 Hall element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59010458A JPS60154582A (en) 1984-01-23 1984-01-23 Hall element

Publications (1)

Publication Number Publication Date
JPS60154582A true JPS60154582A (en) 1985-08-14

Family

ID=11750692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59010458A Pending JPS60154582A (en) 1984-01-23 1984-01-23 Hall element

Country Status (1)

Country Link
JP (1) JPS60154582A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122184A (en) * 1985-11-20 1987-06-03 Sharp Corp Semiconductor device
JPS62122185A (en) * 1985-11-20 1987-06-03 Sharp Corp Semiconductor device
US6542068B1 (en) * 1998-04-27 2003-04-01 Myonic Ag Vertical hall effect sensor and a brushless electric motor having a vertical hall effect sensor
CN102881817A (en) * 2011-07-14 2013-01-16 迈克纳斯公司 Magnetic field sensor and method for determining the offset voltage of a magnetic field sensor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122184A (en) * 1985-11-20 1987-06-03 Sharp Corp Semiconductor device
JPS62122185A (en) * 1985-11-20 1987-06-03 Sharp Corp Semiconductor device
JPH0478196B2 (en) * 1985-11-20 1992-12-10 Sharp Kk
JPH0478195B2 (en) * 1985-11-20 1992-12-10 Sharp Kk
US6542068B1 (en) * 1998-04-27 2003-04-01 Myonic Ag Vertical hall effect sensor and a brushless electric motor having a vertical hall effect sensor
CN102881817A (en) * 2011-07-14 2013-01-16 迈克纳斯公司 Magnetic field sensor and method for determining the offset voltage of a magnetic field sensor
US9689931B2 (en) 2011-07-14 2017-06-27 Tdk-Micronas Gmbh Magnetic field sensor and method for determining and correcting an offset voltage of a magnetic field sensor

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