JPS60154526A - Pattern forming process - Google Patents

Pattern forming process

Info

Publication number
JPS60154526A
JPS60154526A JP59010452A JP1045284A JPS60154526A JP S60154526 A JPS60154526 A JP S60154526A JP 59010452 A JP59010452 A JP 59010452A JP 1045284 A JP1045284 A JP 1045284A JP S60154526 A JPS60154526 A JP S60154526A
Authority
JP
Japan
Prior art keywords
film
silver
patterns
substrate
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59010452A
Other languages
Japanese (ja)
Inventor
Teruo Iino
飯野 輝夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59010452A priority Critical patent/JPS60154526A/en
Publication of JPS60154526A publication Critical patent/JPS60154526A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/06Silver salts

Abstract

PURPOSE:To produce organic high molecular film patterns efficiently by a method wherein an organic high molecular film, an oxide film, a halogenated silver emulsion film are exposed for development on an Si substrate to be successively etched utilizing silver patterns as masks. CONSTITUTION:When a halogenated silver emulsion film 4 is selectively exposed to be processed in developing and fixing solution and distilled water utilizing a contracted projection type aligner, silver patterns 4' are separated in gelatin at the exposed parts while the other silver patterns 4'' at the unexposed parts are resolved leaving gelatin only. After heating an Si substrate 1 in H2 at 150 deg.C, RIE is performed by using Ar+N2 and only silver paterns 4' are left. Next an SiO film 3 is etched utilizing CF4+He and masks 4'' and finally RIE is performed using O2 to open holes in an organic high molecular film 2 simultaneously etching the silver patterns 4'. In such a constitution, the halogenated silver emulsion film 4 may be exposed from around 0.1X10<-7>sec while it is being shifted improving the exposing function of a wafer by 5-10 times magnitude utilizing the contracted projection type aligner.

Description

【発明の詳細な説明】 本発明はIC,LSIなどの半導体装置の製造方法にお
けるパターン形成法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern forming method in a method of manufacturing semiconductor devices such as ICs and LSIs.

単一半導体基板上に多数の半導体素子を組み込んだモノ
リシック型集積回路では、その中のすべての半導体素子
はプレーナ型構造になっている。
In a monolithic integrated circuit that incorporates a large number of semiconductor elements on a single semiconductor substrate, all the semiconductor elements therein have a planar structure.

この様な半導体装置は、不純物の選択的拡散、裏面酸化
膜のコンタクト用窓明け、半導体表面保時のための絶縁
膜の形成、および最後のリード線取り出し用のボンディ
ングバット部分のみ配線層の露出などの工程を経て形成
される。
This type of semiconductor device requires selective diffusion of impurities, opening of contact windows in the backside oxide film, formation of an insulating film to preserve the semiconductor surface, and exposing only the wiring layer at the bonding butt portion for taking out the final lead wire. It is formed through the following steps.

近年LSIなどの半導体装置の素子数の増大は目ざまし
く−それに従い半導体基板上に実現すべき素子パターン
は微細化を余儀なくされている。
In recent years, the number of elements in semiconductor devices such as LSIs has increased dramatically - and accordingly, element patterns to be realized on semiconductor substrates have been forced to become finer.

しかるに、インプレンゴムに架槁剤を加えたネガ型フォ
トレジスト例えばイーストマンコダック社製のKMER
などを半導体基板上に塗布し、カスバー社製2001P
I 等の様な密着露光式アライナ−で、KMER上に選
択的露光を行い、その後現像処理によシ、レジストパタ
ーンを形成する。従来のパターン形成方法では3〜4μ
以下の微細パターンを実現することが困難なため、近年
当該業界では1例えば、AZ1470のごときフェノー
ルノボラック樹脂にナフトキノンジアジド等の感光剤を
加えたポジ型フォトレジストを採用し、アライナ−とし
てGCA社製のDSW4800のごとき縮少投影型露光
装置を使用することが多くなって来ている。ここで、上
記投影型アライナ−は半導体ウェハーを載せる載物台と
、その上に半導体装置の素子パターンを縮少して該ウェ
ハー上に焼きつけるための照明系と光学系を有し、該ウ
ェハー上に1チツプずつ露光しながら、載物台を間欠送
シをするというものである。上記のポジ型フォトレジス
トと縮少型露光装置の採用によシ、半導体基板上に実現
できるパターンは約1.0μm付近まで可能となシ、著
しく半導体素子の微細化を促進し。
However, negative photoresists made by adding cross-linking agents to imprene rubber, such as KMER manufactured by Eastman Kodak Company,
2001P made by Kasbar Co., Ltd.
Selective exposure is performed on the KMER using a contact exposure type aligner such as I, and then a resist pattern is formed by development processing. 3-4μ in conventional pattern formation method
Because it is difficult to realize the following fine patterns, in recent years the industry has adopted positive photoresists made by adding photosensitizers such as naphthoquinone diazide to phenolic novolac resins such as AZ1470, and as aligners manufactured by GCA Co., Ltd. Reduced projection type exposure apparatuses such as DSW4800 are increasingly being used. Here, the projection type aligner has a stage on which the semiconductor wafer is placed, and an illumination system and an optical system for reducing the element pattern of the semiconductor device and printing it on the wafer. The stage is moved intermittently while exposing one chip at a time. By employing the above-mentioned positive photoresist and reduced size exposure equipment, it is possible to realize patterns down to approximately 1.0 μm on a semiconductor substrate, significantly promoting the miniaturization of semiconductor elements.

半導体装置の機能向上に貢献した。Contributed to improving the functionality of semiconductor devices.

しかしながら上記、ポジ型フォトレジストと縮少投影型
アライナ−は素子の微細化には画期的な進歩をもたらし
たものの、単位時間当シに露光処理可能な半導体ウェハ
ーの数、即ち装置の処理能力が従来の密着直光方式に比
べて1/2〜1/3とかなシ劣るという欠点がある。こ
の理由として。
However, although the above-mentioned positive photoresists and reduced projection aligners have brought about revolutionary progress in the miniaturization of devices, the number of semiconductor wafers that can be exposed per unit time, that is, the processing capacity of the equipment It has the disadvantage that it is about 1/2 to 1/3 inferior to the conventional contact direct lighting method. For this reason.

半導体ウェハー上の全パターンを従来の様に一括して露
光するのではなく、1チツグ乃至数チップずりのパター
ンを露光しながら半導体ウェノ・−を載せる載物台を間
欠送シしているためである。即ち1チツグ乃至数チップ
のパターンを露光した後載物台を移動し、所定の距離移
動した後載物台を停止して露光をくシ返すため、従来の
密着霧光型アライナ−に比べて、露光時間および載物台
の移動時間が長いため、著しく半導体ウェハーの処理枚
数が少くなる。
This is because the stage on which the semiconductor wafer is placed is moved intermittently while exposing patterns that are one to several chips apart, rather than exposing all the patterns on the semiconductor wafer at once as in the conventional method. be. That is, after exposing a pattern of one chip to several chips, the stage is moved, and after moving a predetermined distance, the stage is stopped and the exposure is repeated. Since the exposure time and the moving time of the stage are long, the number of semiconductor wafers to be processed is significantly reduced.

また縮少投影型アライナ−は、複雑な機構、および光学
系、照明系および制御用の電子回路を有するため、従来
のアライナ−に比べて、はるかに広大な専有面積が必要
となり、かつ装置自体の価格も数倍と格段に鳥くなって
いる。このため前記 Iの欠点は、縮少投影式アライナ
−によυ処理された半導体装置のコストに悪い影軛を与
えることは自明である。
In addition, because the reduced projection aligner has a complex mechanism, optical system, illumination system, and control electronic circuit, it requires a much larger area than conventional aligners, and the device itself The price has also become much more expensive, several times as expensive. Therefore, it is obvious that the above-mentioned drawback I has a negative impact on the cost of semiconductor devices processed by the reduction projection aligner.

本発明は上記の問題を解決するためになされたものであ
シ、縮少投影式アライナ−の処理能力を従来のポジ型フ
ォトレジストを使用する方式に比べて数倍υ上に改良す
る新規のパターン形成法を提供するものである。
The present invention has been made to solve the above problems, and is a novel method that improves the throughput of a reduction projection aligner by several times υ compared to the conventional system using positive photoresist. A pattern forming method is provided.

本発明によるパターン形成法は縮少投影型アライナ−に
おいて半導体ウェハー処理中の載物台を停止することな
く露光することが可能となるので、該アライナ−の処理
能力を著しく向上させることが可能となる。
The pattern forming method according to the present invention makes it possible to perform exposure without stopping the stage during semiconductor wafer processing in a reduced projection aligner, so it is possible to significantly improve the processing capacity of the aligner. Become.

本発明の特徴は、半導体基板の一生面上に、有機高子分
層、酸化硅素膜、およびハロゲン化銀乳剤膜を順次付着
する工程と、縮少投影型路光装置において該基板を載せ
た載物台を停止することなく、露光処理を行う工程と、
該基板を所定の写真現像、定着および停止処理を行って
該ハロゲン化銀乳剤膜中の銀を選択的に析出させる工程
と、所定の成分のガスプラズマ中で該銀パターンをマス
クにして、酸化硅素膜を選択的に除去し、次に該酸化硅
素パターンをマスクにして、所定のガスプラズマ中で有
機高分子膜を選択的に除去し、所定の核高分子膜パター
ンを形成するパターン形成法にある。
The present invention is characterized by a step of sequentially depositing an organic polymer layer, a silicon oxide film, and a silver halide emulsion film on the whole surface of a semiconductor substrate, and a step of mounting the substrate in a reduction projection type path light device. A process of performing exposure processing without stopping the stage;
The substrate is subjected to predetermined photographic development, fixing and stop treatments to selectively precipitate silver in the silver halide emulsion film, and oxidation is performed using the silver pattern as a mask in gas plasma of predetermined components. A pattern forming method in which a silicon film is selectively removed, and then an organic polymer film is selectively removed in a predetermined gas plasma using the silicon oxide pattern as a mask to form a predetermined core polymer film pattern. It is in.

以下図面を参照しながら本発明の実施例を詳細に説明す
る。
Embodiments of the present invention will be described in detail below with reference to the drawings.

珪素基板lの一生面上にフェノールボラック樹脂のごと
き有機高分子膜2を1.5〜2.0μの厚さ■スピンコ
ード法によシ妥布する9、(第1図) 次に該高分子層2上に酸化珪素の薄層3を真空蒸着法に
よシ0.2〜0.3μの厚さに付着させる。
An organic polymer film 2 such as phenol borac resin is deposited on the whole surface of the silicon substrate 1 to a thickness of 1.5 to 2.0 μm by the spin cord method 9 (Fig. 1). A thin layer 3 of silicon oxide is deposited on the polymer layer 2 by vacuum evaporation to a thickness of 0.2 to 0.3 .mu.m.

(第2図) 次いで、該薄層上にゼラチンにハロゲン化銀を混合した
。ハロゲン化銀乳剤膜4をスピンコード法によシ0.5
〜1.0μの厚さに塗布する。(第3図) 次に、基板1を縮少投影型アライナ−にょシ選択的な露
光を行う。この場合光源として出力2KW、 。
(Figure 2) Silver halide was then mixed with gelatin on the thin layer. The silver halide emulsion film 4 was formed by the spin coding method.
Apply to a thickness of ~1.0μ. (FIG. 3) Next, the substrate 1 is selectively exposed to light using a reduction projection type aligner. In this case, the light source has an output of 2KW.

ランプ電圧26Vのキセノンフラッシェランプを用いる
。その後、ハン゛ドロキノンを主成分にした現像法によ
る現像処理1次いで、チオ泥酔ソーダを主成分にした定
着液による定着処理最後に純水による水洗を行うと一1
該乳剤膜4のうち、選択的に露光された部分は銀がゼラ
チン中に析出して4′とな#)l露光されない部分は銀
が溶は去ってゼラチンのみに欧る(第4図)。続いて硅
素基板1を水素雰囲気中、温度150℃で20分程度加
熱後、平行平板型の反応性イオンエツチング装置におい
て、アルゴンと窒素の混合したガスプラズマによる処理
を行う。この場合の処理条件として、電極間隔10〜1
5cwL、ガス圧力は6 X 10−” 〜から10 
X 10 Torr 、アルゴンと窒素の混合比は1:
3高周波出力は100〜120Wである。
A xenon flash lamp with a lamp voltage of 26V is used. After that, a development process using a development method using handroquinone as the main component, followed by a fixing process using a fixer containing thio-intoxicating soda as a main component, and finally washing with pure water.
In the selectively exposed areas of the emulsion film 4, silver precipitates into the gelatin and becomes 4'); In the unexposed areas, the silver dissolves and remains only in the gelatin (Figure 4). . Subsequently, the silicon substrate 1 is heated in a hydrogen atmosphere at a temperature of 150° C. for about 20 minutes, and then processed using a gas plasma containing a mixture of argon and nitrogen in a parallel plate type reactive ion etching apparatus. In this case, the processing conditions include an electrode spacing of 10 to 1
5 cwL, gas pressure from 6 x 10-” to 10
X 10 Torr, the mixing ratio of argon and nitrogen is 1:
3 High frequency output is 100-120W.

上記の条件で10〜15分処理すると、ゼラチン膜部分
4”は除去され、銀パターン4′のみが残る。(第5図
) 次に前記の反応性イオンエラチン装置のエツチング条件
中、ガスをCF、とヘリウムの混合ガス(混合比1:1
)ガス圧力フ、5X10″″1〜9.0×10−”fo
rr 、高周波出力を150〜180Wに変更して、嘔
らにエツチング処理を10〜12分程度行程度、銀パタ
ーン4′の下t;外の酸化珪素3は除去される。(第6
図) 最後に、エツチング条件中ガスを酸素、ガス圧力0.5
〜0.6 Torrに変更してエツチング処理を加える
と銀パターン4′の下の部分以外の有機高分子膜2およ
び簀パターン4′が除去される。
After processing for 10 to 15 minutes under the above conditions, the gelatin film portion 4'' is removed, leaving only the silver pattern 4' (Fig. 5).Next, under the etching conditions of the reactive ion etching apparatus described above, the gas is and helium (mixing ratio 1:1)
) Gas pressure, 5X10″1~9.0×10-”fo
Then, the high frequency output was changed to 150 to 180 W, and the etching process was continued for about 10 to 12 minutes to remove the silicon oxide 3 at the bottom of the silver pattern 4'. (6th
Figure) Finally, during the etching conditions, the gas was oxygen and the gas pressure was 0.5.
When the etching process is performed by changing the pressure to 0.6 Torr, the organic polymer film 2 and the screen pattern 4' are removed except for the portion under the silver pattern 4'.

これによシ選択的に露光された部分のみ有機高分子膜2
および酸化シリコン膜3が残シ、素子パターンが形成さ
れる(第7図)。
This allows only the selectively exposed portions of the organic polymer film 2 to be exposed.
Then, the silicon oxide film 3 remains, and an element pattern is formed (FIG. 7).

本発明によれば2選択的露光の際、光源を強力なキセノ
ンフラッシュランプ感光層として、現行のフォトレジス
トよりIO’〜10’倍もの感度を有すハロゲン化銀乳
剤を用いているので、露光時間を現行の0.5秒から0
.1〜0.2X1’0−’秒に短縮することが可能とな
る。従って縮少投影型アライナ−で露光する場合、従来
の様にいちいち載物台を停止する必要がなくなシ、移動
させなから1フラツシエさせることが可能となる。何故
ならば曳行の該アライナ−の載物台の移動速度は最大団
朋/秒程度である。露光時間0.2 X 10.’秒中
の半導体基板の移動距離′は50寵/秒X0.2X10
秒=o、oiμとなシ、現行の素子パターンの最小寸法
1〜2μの1/ 程度と無視しうる値とな00 るからである。
According to the present invention, during two-selective exposure, a strong xenon flash lamp photosensitive layer is used as a light source, and a silver halide emulsion having a sensitivity IO' to 10' times that of current photoresists is used. Change time from current 0.5 seconds to 0
.. It is possible to shorten the time to 1 to 0.2 x 1'0-' seconds. Therefore, when exposing with a reduction projection type aligner, there is no need to stop the stage each time as in the conventional case, and it is possible to perform one flash without moving it. This is because the moving speed of the stage of the aligner being towed is about the maximum speed per second. Exposure time 0.2 x 10. 'Distance traveled by the semiconductor substrate in seconds' is 50 cm/sec x 0.2 x 10
This is because when second=o, oiμ, the value becomes negligible, which is about 1/ of the minimum dimension of 1 to 2μ of the current element pattern.

以上の理由によシ本発明によるパターン形成法によれ1
〆x1縮少投影型アライナ−による半導体ウェハーの布
先処理能力は従来に比べて格段に向上しほぼ5〜10倍
に達する。
For the above reasons, the pattern forming method according to the present invention
The ability to process the edge of a semiconductor wafer using the x1 reduction projection type aligner is significantly improved compared to the conventional method, reaching approximately 5 to 10 times.

例えば、該アライナ−として、米国GCA社製り、8.
 W4800 f、 f、プf イス5. Oy、 X
 5.0鮎のチップを4“ ウニ・・−に焼き伺ける場
合、現 1状では、240回載物台を停止し、その都度
、0.5秒前後露光する必要がちるので、合計の露光時
間として120秒、&たステージの移動時間が約30秒
程度必要なので、一枚のウェハーを処理するのに、最低
150秒は必要となる。
For example, as the aligner, manufactured by GCA, USA, 8.
W4800 f, f, pf chair5. Oy, X
In the current situation, if a 5.0 sweetfish chip can be baked into a 4" sea urchin... Since the exposure time is 120 seconds and the stage movement time is about 30 seconds, a minimum of 150 seconds is required to process one wafer.

従って現行の方法では該アライナ−での4”ウェハーの
露光処理能力はせいぜい、1時間白シ20〜30枚程度
となる。一方1本発明によるパターン形成法によれば、
該アライナ−の載物台を停止する必要がないので、前記
の条件の4“ ウェハーでは1枚の処理時間がせいぜい
30秒以内となシ、従って、該装置でのウェハー処理能
力は1時間当fi、120枚と、現行5〜6倍程度の処
理が可能となる。
Therefore, in the current method, the exposure processing capacity of 4" wafers using the aligner is at most about 20 to 30 blanks per hour. On the other hand, according to the pattern forming method according to the present invention,
Since there is no need to stop the stage of the aligner, the processing time for one 4" wafer under the above conditions is at most 30 seconds. Therefore, the wafer processing capacity of this apparatus is 1 hour. fi, 120 sheets, which is about 5 to 6 times the current processing rate.

以上述べたごとく、本発明によるパターン形成法により
、縮少投影型アライナ−のウェハー処理能力を従来の数
倍に増大することが可能となシ。
As described above, the pattern forming method according to the present invention makes it possible to increase the wafer processing capacity of a reduced projection aligner several times that of the conventional one.

半導体装置のコスト低減に貢献する所大である。This is a major contribution to reducing the cost of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第7図は本発明の一実施例をポす工程別断面
図である。 尚1図において、1・・・・・・珪素基板、2・・・・
・・有機高分子膜%3・・・・・・酸化珪素薄膜、4・
・・・・・ハロゲン化銀乳剤膜、4′・・・・・・鍋、
4“・・・・・・ゼラチン。
1 to 7 are cross-sectional views showing steps of an embodiment of the present invention. In Figure 1, 1... silicon substrate, 2...
...Organic polymer film%3...Silicon oxide thin film, 4.
...Silver halide emulsion film, 4'...pan,
4 "...Gelatin.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の一主面上に、有機高子分膜、酸化硅素膜、
およびハロゲン化銀乳剤膜を順次付着する工程と、縮少
投影型露光装置において該基板を載せた載物台を停止す
ることなく、露光処理を行う工程と、該基板を所定の写
具現像、定着および停止処理を行って該ハロゲン化銀乳
剤膜中の銀を選択的に析出させる工程と、所定の成分の
ガスプラズマ中で該銀パターンをマスクにして、酸化硅
素膜を選択的に除去し、次に該酸化硅素パターンをマス
クにして、所定のガスプラズマ中で有機高分子膜を選択
的に除去し、所定の該高分子膜パターンを形成ことを特
徴とするパターン形成法。
On one main surface of the semiconductor substrate, an organic polymer film, a silicon oxide film,
and a step of sequentially depositing a silver halide emulsion film, a step of performing an exposure process without stopping the stage on which the substrate is placed in a reduction projection type exposure device, and a step of developing the substrate in a predetermined photographic device. A step of selectively precipitating the silver in the silver halide emulsion film by performing fixing and stopping treatment, and selectively removing the silicon oxide film using the silver pattern as a mask in gas plasma of predetermined components. . Next, using the silicon oxide pattern as a mask, the organic polymer film is selectively removed in a predetermined gas plasma to form the predetermined polymer film pattern.
JP59010452A 1984-01-23 1984-01-23 Pattern forming process Pending JPS60154526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59010452A JPS60154526A (en) 1984-01-23 1984-01-23 Pattern forming process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59010452A JPS60154526A (en) 1984-01-23 1984-01-23 Pattern forming process

Publications (1)

Publication Number Publication Date
JPS60154526A true JPS60154526A (en) 1985-08-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP59010452A Pending JPS60154526A (en) 1984-01-23 1984-01-23 Pattern forming process

Country Status (1)

Country Link
JP (1) JPS60154526A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE39895E1 (en) 1994-06-13 2007-10-23 Renesas Technology Corp. Semiconductor integrated circuit arrangement fabrication method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE39895E1 (en) 1994-06-13 2007-10-23 Renesas Technology Corp. Semiconductor integrated circuit arrangement fabrication method

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