JPS60153564A - Picture processor - Google Patents

Abstract

PURPOSE:To remove unnatural state such as the distortion of a picture and to attain accurate and faithful picture processing corresponding to the purpose of picture deformation by providing an address converting circuit, an averaging circuit and a clock generating circuit to the titled device. CONSTITUTION:When a deformed picture is to be formed by coordinate conversion, an address conversion circuit 35 executes prescribed arithmetic processing on the basis of address data generated from an address generating circuit 31 and outputs (n) conversion address groups close to a remarked address. The output data are averaged by an averaging circuit 36 through the 1st picture memory 32 and outputted as picture data PB. The data PB are inputted to the 2nd picture memory 33 by using address data from a delay circuit 34 as its writing address. When a pulse is inputted synchronously with a supplied clock, a coordinate-converted picture converted at the same timing as the output of the picture data from the circuit 36 is inputted to the memory 33. Thus, accurate and faithful picture processing corresponding to the purpose of picture deformation can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image processing device that creates a deformed image that is deformed by coordinate transformation based on original image data stored in an image memory.

(Conventional technology) Conventionally, this is a device that performs coordinate transformation on images.

A circuit configuration as shown in FIG. 1 is known.

In FIG. 1, the address generation circuit (11, address conversion circuit (2), 1st 1st image memo January 3rd), 1st ? The image memory (4) and the delay circuit (5) are each connected to the f clock generation circuit (6).

The address generation circuit +11 generates an initialize pulse (P
) and clock (CKυ) are input and address data (XA
.

yA) is output. The address conversion circuit (2) reads the address data (x, a, yA) using the clock (CK, ), performs a preset calculation, and converts the converted address data (XB yn) into the first image memory. 1
Output on month 3). Image memo January 3) is the clock (C
K,) receives address data (Xo yn) as a read address and outputs image data (pB) from the corresponding memory area.

First, the delay circuit (5) includes a clock (CK, ),
(CK,) is supplied, and the input address data (X
A yA) is held as is at the clock (CK, ), and is taken into the second image memo (January 4) along with the image data (pB) at the clock (CK, ). In the image memo January 4), image data (1)B) is written using the address data (XA, yA) as the write address.

In this way, the original image data stored in the first image memo January 3) is written into the second image memo January 4) as an image transformed by coordinate transformation.

Each circuit block constituting the above-described conventional image processing device is shown in FIGS. 2 to 4.

FIG. 2 shows an address generation circuit (1) which can sequentially increment and output X address (XA) + X address (yA).

That is, when an initializing pulse (PI) is first input to the RS flip-flop (7) to set it, a "1" signal is input to each load input (LD) of the counter (81, (91). At this time, Counter (8).

At the first look of the clock (CK, ) supplied to (9), the counter (8) is loaded with the start address (Xs), and the counter (9) is loaded with the start address (ys). is loaded.

Comparator αQ is supplied with the final value end address (XE) of the ing. Therefore, during initialization, the output of the counter (8) is the start address (Xs),
The output of the counter (9) becomes the start address (ys').

Next, at the second look of the clock (CK,), the 5 counter (8
) output (XA) is incremented by 1,
The X address (XA) is Xs+1, but the counter (
9) has an enable input of "0" and maintains its initial state.

In this way, every time the clock (CK,) is input, only the X address (X,) becomes XS + 1 r Xs+2 +・
When the value increases to XE, "1" is supplied to the load input hole of the counter (8).The clock (CK) causes the X address (XA) to become the start address (Xs
). At that time, the enable input of the counter (9) (since the y is set to "1", the X address (yA)
is incremented by one.

The clock (CK,) is stopped when the address becomes XE, yE9, and from the address generation circuit (11), the clock (CK,) generates (x
S.

Address data (XA
, yA) are sequentially output.

FIG. 3 shows the address conversion circuit (2), which includes multiplication circuits 0~, 031, Q4), 0 phrase, and addition circuit u.
EU power and D flip-flop (1 (11) n.

In this address conversion circuit (2), address data (X
A, yA) can be received and converted into an output (xB yu) by performing an affine transformation represented by the following equation.

(Xu, yu) - (XA, yA) (bd) + (tx
, ty) a and c are respectively n multiplication circuits Q21 (+4
With the constant signal input to +, the X address (XA) and the multiplication are combined, b.

d is a constant signal input to each multiplication circuit α31 (151), and the multiplication is combined with the X address (yA).

Adder circuit 06) outputs aXA and byA and a constant signal (
tx) is added, and the output XB(-aXA+byA+
t・) can be obtained.

In the adder circuit U output, outputs CXA and dyA and a constant signal (t
, ) are added, and the output ys (-CXA×dyA×t
, ) can be obtained.

Figure 4 shows the D flip-flop c! 0) and (211) are connected in series, and the input address data (XA, yA) is delayed by supplying clocks CK and CK delayed by one pulse to each of them as shown in FIG. This is a delay circuit (5) that outputs the signal.

This delay circuit (5) holds the address data of the address generation circuit (1) for the required time and outputs the first image memo.
) output and writing timing of image data (PB) can be matched.

In the conventional image processing apparatus, for example, the L-shaped line segment pattern shown on the left side of FIG.
month 3), if you try to obtain a figure rotated by an angle of 0 using the conversion circuit (2), the second
An L-shaped line segment pattern shown on the right side of FIG. 6 is written on the image memo January 4). In the figure, the number "4"
indicates the density on the line segment of the pattern.

As shown in the figure, the rotated figure is more distorted than the figure before rotation, and has the disadvantage that the line segments of the outline of the original pattern cannot be faithfully reproduced.

In addition, when obtaining a new image pattern as a reduced figure based on the checker pattern shown on the left side of FIG. 7, the address conversion circuit (2) that does not require coordinate conversion
, by thinning out address data according to the reduction rate.

There is a possibility that this pattern will result.

That is, the conventional image processing apparatus has a drawback that when the thinning interval and the characteristic fine pattern become synchronized due to reduction, the characteristic pattern disappears.

Furthermore, when rotation and reduction are performed at the same time, due to the periodicity of the thinning interval and the periodicity of distortion of one image, there are also drawbacks such as the appearance of pseudo patterns due to a type of moiré phenomenon that does not exist in the original image data. Ta.

(Objects and Structure of the Invention) The present invention has been made in view of the above-mentioned drawbacks, and is based on the original image data stored in the first storage means, and is stored in the second storage means based on the converted address data. In an image processing device that writes a modified image, for each original address data sequentially output from the address generation means, an address conversion means outputs n neighboring converted address data, and an address conversion means for outputting n neighboring converted address data; The purpose of one-image transformation is to remove unnaturalness such as image distortion that is seen in conventional transformed images, and to perform predetermined calculation processing on the read original image data. The purpose of the present invention is to provide an image processing device with high precision and fidelity according to the image quality.

(Description of Embodiments) Hereinafter, embodiments of the present invention will be described based on the drawings.

In the embodiment shown in FIG. 8, the address generation circuit Oυ, the first image memory 02, the second image memory (to), and the delay circuit are the same as those in the conventional device shown in FIG. Address conversion circuit according to the invention 0! The configuration and operation of i1, the average circuit (to), and the clock generation circuit C37+ will be described below.

The address conversion circuit C35) shown in FIG. 9 converts the address data (XA y
A) and performs predetermined arithmetic processing to convert a group of n converted addresses (XBI, 'Is
υ.

(XBI, '/Bt) □... (xnn, ynn
) is output.

The clock (CK, ) is supplied to the D flip-flop (to) to which the X address (XA) is input, and the D flip-flop 0!1 to which the X address (, yA) is input, and the n-ary counter (41) is supplied with the clock (CK, ). , a clock (CK, ) is supplied.

As shown in FIG. 11, the clock (CK, ) is the frequency of the clock (CK, ) multiplied by n (n: integer, in this case,
4) is the multiplied signal.

Output 1 of the n-ary counter (i=o, 1..., (n-1)
)) is supplied to the lookup table (4υ), and outputs data (△X, ), (Δyt) according to the count content i.k3, (431 is the n-rn addition circuit, Circuit (in 42, X address (XA) and data (△
X, ) are added to the address (XA + △XO) in the vicinity of the X address (XA).

(XA+ △X+) + ”' (XA + △x, -
+) is output n, and the adder circuit θ3 outputs the X address (y
A) and data (△yt) are added to obtain the X address (
Address near yA) (to yA+8V), (yA+
ΔyI) r ”' (yA+Δy, -+) is output n
Ru.

The circuit after the adder circuit f41D, (d) is a multiplier circuit (451(461(4η) and an adder circuit (4s
G19) The circuit is configured as a VC and performs an affine transformation expressed by the following equation.

(XB +, 3' B 1) ”” (XA ten △X
l, yA + △y + d is multiplied by a multiplier circuit (45i (constant signal input to 471, y address fJA+Δy+)).

In the adding circuit decoy, the output is a(XA + △x,), and (yA
+△y+) and constant signal tx are added, and the output data (
) can be obtained. Also, the addition circuit (49)
Then, the outputs C(XA+ΔX+), d(yA+Δyt), and constant signal t are added to obtain output data (yn+). That is, Xn, = a()(A+△x+)+b(yA+△yt)+
txyB1-c(XA+△xυ+d(yA+△3'l
)+t.

(However, i=Q, 1...n-1) is obtained as converted address data.

The converted address data (XB + + V Bυ is stored in the first image memory o based on the clock (CK,)
2, the image data in the corresponding memory area (
pnt). - clock (CK, ) for power and delay circuit (2);

(CK, ) is supplied, and the input address data (xA, yi) of interest is held as is for the required time by the clock (CK6). It is supplied to

FIG. 10 shows n image data (1)B1), (1)B2), - output from the first image memory Gz.
(1) B, ) (n-4 in this case) inputs the average circuit (
An example of the following is shown.

The image data (pn:) is taken into the D flip-flop 50) at the first glance of the clock (CK, ). At the same time, the n-ary counter 6υ counts the output (i)-1. This counter output (i) is supplied to the lookup table 62 and the count content (i
Data (G1) corresponding to 1 is output.

531 is a multiplication circuit in which image data (po:) is multiplied by coefficient data (α·). The multiplied output data (α+put) is supplied to the adder circuit 54) and fed back via the D flip-flop 59.
It is designed to be added to the data (α·pnt) when the value is 1.

The output (j) from the n-ary counter 62 becomes j=1 at the first look of the clock (CK,), and then at the n-th
j-0 is held until the -1st shot, and its output (j) is supplied as the clear input of the D flip-flop 65).

Therefore, the output data of the adder circuit 64) is (αIpB+
), the timing of the second annotation is (α + pB + ten α2p
112) Each f'LD flip-flop 6!
il as Σα+p old at the timing of the i-th view.

In this way, at the timing of the nth note of clock CK5,
This average circuit 0G) outputs pB =, person α+p old.

The equalized image data (pB) is taken into the second image memory (c) using the address data (XAyA) read out from the delay circuit G4 by the clock (CK, ) as a write address.

The second image memo 'J C331 has a clock (CK,
) is supplied, and as shown in FIG. 1I, the average circuit ( The modified image that has undergone coordinate transformation can be stored in this second image memory in synchronization with the output of image data (pB) from the second image memory.

According to the apparatus of the present invention configured as described above, n converted image data (pB) obtained from original image data (pA) are obtained by converting n converted image data (pB) in the vicinity of each target original image address data. Using the weighted average using the address data obtained, as explained below, can be accurately and faithfully reproduced in digital image processing that performs reduction and rotation at the same time.

FIG. 12 shows a method of reading out the first image memory 0 based on the address data converted by the apparatus of the embodiment.

A solid line square schematically shows an address space for one pixel in the first image memory, and image data of a predetermined density value is stored corresponding to each square.

On the other hand, a square indicated by a dashed line is a one-pixel data area that has been reduced, rotated, and converted. That is, all the image data within the dashed-dotted line corresponds to one pixel of the converted image.

In the conventional device, the converted image data (pn) is data corresponding to the center point A, that is, X-3°y=
However, in the apparatus of the present invention, only data corresponding to n points near point A, such as (pBl) and (pB-), are used.

(pBs), (pn-), Pn-(pu+
-1,! to write 10 pBI + pns + pB4) into the second image memory (to). -2i) In this case, how to select the n neighbors can be determined, for example, by the settings of the lookup table @υ, and in order to improve the reproduction accuracy, the number n of data to be used can be increased. .

However, if necessary, it is also possible to emphasize data at the center and use pBs as data at point A (pe). In this case as well, each of the nine coefficients can be arbitrarily determined by setting the lookup table 6z of the averaging circuit.

FIG. 13 shows a deformed image obtained by rotating an L-shaped pattern by an angle θ using the apparatus of the present invention, similar to that shown in FIG. 6.

Compared to the conventional apparatus, the distortion of the L-shaped line segment is less noticeable, and an image that is correctly recognized as an L-shape can be obtained.

FIG. 14 shows a checkered pattern in a reduced size, similar to that shown in FIG. 7.

By using n neighboring converted address data for each original address data, n fine patterns included in the original image are averaged, and the converted image data is
By setting the density to "chi", a middle tone can be expressed.

In this way, with reduction, the fine patterns of the original image may disappear, but by averaging the entire image, unnaturalness such as distortion of a single image can be reliably removed, which can be used for the purpose of transforming a single image. Accurately reproduced images can be obtained.

[Brief explanation of drawings]

1 to 7 are diagrams for explaining a conventional image processing device, FIG. 8 is a circuit configuration diagram showing an embodiment of the present invention, and FIG. 9 is a diagram showing an example of an address conversion circuit. Circuit configuration diagram. FIG. 10 is a circuit configuration diagram showing an example of an averaging circuit. FIG. 11 is an operation timing diagram showing the clocks used in the device of the above embodiment. 6υ Address generation circuit 02 First image memory (To) Second image memory Delay circuit ) Average circuit 0n Clock generation circuit Fig. 3 2 and - 2 Fig. 4 Fig. 11 CH2 - - - 1 "1 - "l" - Fig. 13 Fig. 14

Claims (4)

[Claims] (1) In an image processing device in which a modified image is written into a second storage means based on address data obtained by converting the original image data stored in the first storage means, the modified image is sequentially output from the address generation means. An address converter outputs an appropriate number of converted address data in the vicinity for each n original address data, and predetermined arithmetic processing is performed on the original image data read out based on the converted address data. 1. An image processing device comprising: arithmetic processing means for performing calculation processing. (2) The image processing apparatus according to claim 11, wherein the address conversion means constitutes an affine conversion circuit. (3) The arithmetic processing means is capable of simply averaging original image data based on a plurality of converted address data. The image processing device described. (4) The arithmetic processing means is capable of weighted averaging of original image data based on a plurality of converted address data. The image processing device described.