JPS60153535U - Packages for integrated circuits - Google Patents

Packages for integrated circuits

Info

Publication number
JPS60153535U
JPS60153535U JP4127284U JP4127284U JPS60153535U JP S60153535 U JPS60153535 U JP S60153535U JP 4127284 U JP4127284 U JP 4127284U JP 4127284 U JP4127284 U JP 4127284U JP S60153535 U JPS60153535 U JP S60153535U
Authority
JP
Japan
Prior art keywords
packages
integrated circuits
integrated circuit
circuit package
abstract
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4127284U
Other languages
Japanese (ja)
Inventor
修 近藤
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP4127284U priority Critical patent/JPS60153535U/en
Publication of JPS60153535U publication Critical patent/JPS60153535U/en
Pending legal-status Critical Current

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  • Structure Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す平面図、第2図は本考
案の他の実施例を示す平面図である。 尚、図において、a・・・・・・集積回路用パッケージ
、b・・・・・・端子、C・・・・・・1ピン表示用凹
部、d・・・・・・品名捺印、e・・・・・・本考案に
よる端子番号識別マークの捺印、1〜64・曲・端子番
号である。
FIG. 1 is a plan view showing one embodiment of the present invention, and FIG. 2 is a plan view showing another embodiment of the present invention. In the figure, a... Integrated circuit package, b... Terminal, C... 1 pin display recess, d... Product name stamp, e . . . The terminal number identification mark according to the present invention is stamped with numbers 1 to 64, songs, and terminal numbers.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 集積回路用パッケージの品名捺印面に複数の端子番号識
別マークを捺印したことを特徴とする集積回路用パッケ
ージ。
An integrated circuit package characterized by having a plurality of terminal number identification marks stamped on the product name stamping surface of the integrated circuit package.
JP4127284U 1984-03-23 1984-03-23 Packages for integrated circuits Pending JPS60153535U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4127284U JPS60153535U (en) 1984-03-23 1984-03-23 Packages for integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4127284U JPS60153535U (en) 1984-03-23 1984-03-23 Packages for integrated circuits

Publications (1)

Publication Number Publication Date
JPS60153535U true JPS60153535U (en) 1985-10-12

Family

ID=30550942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4127284U Pending JPS60153535U (en) 1984-03-23 1984-03-23 Packages for integrated circuits

Country Status (1)

Country Link
JP (1) JPS60153535U (en)

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