JPS60153054U - line interface circuit - Google Patents
line interface circuitInfo
- Publication number
- JPS60153054U JPS60153054U JP4014684U JP4014684U JPS60153054U JP S60153054 U JPS60153054 U JP S60153054U JP 4014684 U JP4014684 U JP 4014684U JP 4014684 U JP4014684 U JP 4014684U JP S60153054 U JPS60153054 U JP S60153054U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- signal
- transistor
- diode
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Monitoring And Testing Of Exchanges (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の回線インタフェイス回路の構成を示す図
、第2図は本考案の二実施例を示す回路図である。
1.2・・・局線端子、7,8・・・電圧出力端子、9
・・・増幅器、14・・・スピーカ、20,22,23
゜25・・・抵抗、21・・・トランジスタ、24・・
・ダイオード、26・・・ツェナーダイオード、27・
・・平滑コンデンサ、28・・・コンデンサ、29・・
・信号出力端子。FIG. 1 is a diagram showing the configuration of a conventional line interface circuit, and FIG. 2 is a circuit diagram showing two embodiments of the present invention. 1.2... Office line terminal, 7, 8... Voltage output terminal, 9
...Amplifier, 14...Speaker, 20, 22, 23
゜25...Resistor, 21...Transistor, 24...
・Diode, 26...Zener diode, 27・
...Smoothing capacitor, 28...Capacitor, 29...
・Signal output terminal.
Claims (1)
れたトランジスタと、局線端子間に直列接続された第2
および第3の抵抗と、この第2および第3の抵抗の接続
点電圧を前記トランジスタのベースにバイアス電圧とし
て与えるダイオードと、前記第1の局線端子信号電圧を
前記第2および第3の抵抗の接続点に与える第1のコン
デンサと前記トランジスタのコレ多夕と第2の局線端子
との間に接続され、その出力電圧を増幅器電源電圧とし
て電圧出力端子から送出するツェナーダイオードと、第
1の局線端子から直流電圧に重畳して入力される交流信
号を信号出力端子に送出する第2のコンデンサとを備え
、前記信号出力端子から送出される交流信号を該信号の
モニタ回路に供給する回線インタフェイス回路。A transistor whose emitter is connected to a first station line terminal via a first resistor, and a second transistor whose emitter is connected in series between the station line terminals.
and a third resistor, a diode that applies a voltage at the connection point of the second and third resistors to the base of the transistor as a bias voltage, and a diode that applies the voltage at the connection point of the second and third resistors to the base of the transistor, and a diode that supplies the first office line terminal signal voltage to the second and third resistors. a Zener diode connected between the first capacitor applied to the connection point of the transistor and the second office line terminal, and transmitting the output voltage from the voltage output terminal as the amplifier power supply voltage; a second capacitor for sending an AC signal superimposed on the DC voltage input from the station line terminal to the signal output terminal, and supplying the AC signal sent from the signal output terminal to a monitor circuit for the signal. Line interface circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4014684U JPS60153054U (en) | 1984-03-21 | 1984-03-21 | line interface circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4014684U JPS60153054U (en) | 1984-03-21 | 1984-03-21 | line interface circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60153054U true JPS60153054U (en) | 1985-10-12 |
Family
ID=30548765
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4014684U Pending JPS60153054U (en) | 1984-03-21 | 1984-03-21 | line interface circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60153054U (en) |
-
1984
- 1984-03-21 JP JP4014684U patent/JPS60153054U/en active Pending
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