JPS60152129A - Read solomon code and coding circuit - Google Patents

Abstract

PURPOSE:To obtain a read Solomon code coding circuit with ease of data transmission and reception by constituting all the systems with an RAM and an error correction code generating circuit transmitting and receiving RAM data. CONSTITUTION:An input signal 22 is inputted to an exclusive OR circuit 9 through a data bus 20 from the RAM and when an input control signal 21 is an H level, the signal is inputted to g3 coefficient circuits 5-8 through a gate circuit 10, and when the last input data A4 is inputted, the input control signal 21 goes to L, check words A3-A0 of a remainder term left in D flip-flop D3FF4- D0FF1 are outputted to the data bus 20 as an output signal 23b via a tri-state buffer 25 being in conductive state.

Description

BACKGROUND ART The present invention relates to a Reed-Solomon code/encoding circuit used as an error correction code in digital audio equipment and the like.

Conventional digital audio equipment employs error correction codes because burst errors due to defects in recording media or random errors due to jitter, noise, etc. are unavoidable.

The compact disc system uses so-called CIRC, which combines the conversion of burst errors into random errors by interleaving and the Reed-Solomon code, which has a high error correction ability for random errors. As a combination method, an error correction code is added before and after interleaving, that is, a data length of "24" is added before interleaving.
After interleaving, a Reed-Solomon code with a block length of -P is generated and combined with a Reed-Solomon code with a data length of -P and a block length of ``32''. They are called a C2 encoder and a C1 encoder, respectively.

Conventionally, the above-mentioned interleaving has been performed by using an interleaving memory and utilizing the relationship between loading and reading, but the interleaving memory and the error correction code generation circuit have been separate. In the CIRC mentioned above, input data is attached with a check code by a C2 encoder, then guided to an interleap memory, and the output data of the interleap memory is guided to a C+ encoder, a check signal is attached, and the CIRC is
It was output as an RC signal.

The conventional method is improved, and in the entire error correction code system, those related to memory write and read operations (for example, data delay, rearrangement, and interleaving) are executed in one RAM, By placing only the error correction code generation circuit that cannot be executed in memory outside the RAM, receiving data from the RAM, and sending the output data of the aforementioned generation circuit back to the RAM, the entire system can be configured very simply. I can do it.

DISCLOSURE OF THE INVENTION In view of the above circumstances, it is an object of the present invention to configure an entire error correction code system from one RAM and a 5-error correction code generation circuit that exchanges data with the RAM. The object of the present invention is to provide a Reed-Solomon code/encoding circuit that facilitates data exchange in a system.

The principle of generating a Reed-Solomon code is well known, but will be explained below using a C2 encoder used in compact discs as an example. With this C2 encoder, the data length is “24”.
", a Reed-Solomon code with a block length of 1 pi is generated. Here, the block length "28" represents the number of words, and one word is 8 bits. Also, the data length "24" is i
Since it shows the number of ft report words, the number of inspection word company is 4.

Primitive polynomial F(M, generator polynomial G(X
) is the following formula.

F(X)=X8+X'+X"+X"+ I C1)G(
X)=X'+α75X3m"X"10α78X"-C6(
21 N, α is the root of the primitive polynomial F (XI. From the human information words A4 to A27, the next polynomial representation A (material) is
Give A flash = A4 X' +AsX5+...+A26X26
＋Azy can get.

In principle, the circuit shown in FIG. 1 can be considered as this division circuit. Here, D is a delay element that transfers data every l clock. When all the data is input manually, the desired remainder remains in each delay element.

Based on the above principle, the Reed-Solomon code/encoding circuit according to the present invention is a circuit that inputs a block signal consisting of a plurality of words stored in RAMVC, generates a check word of a Reed-Solomon code, and outputs it again to RAMK. So, the generator polynomial xm10, , gm-, xm-" +
・＋g.

The number of D-type flip-flops equal to the order m of FF is DaFF (a = o).

-, m -1) and ga coefficient circuit (a=o, -, m-
1) and fr l l, It 8I'j'l to 1/1 human power 1++ 'j r', ``Ill + i'l+'
(C output signal is added, and each ga output signal is added via a gate circuit.
The above-mentioned g is input to the coefficient circuit and is input to DoFF. The output of the coefficient circuit is input, and the previous stage Da-
□The above-mentioned p a FF * g a coefficient circuit is connected so that the output of the FF and the output of the ga coefficient circuit are added manually, and the above-mentioned gate circuit is connected for each block signal from the RAM. Open it manually, shift the data by the clock signal, and when the block signal is finished,
This gate circuit is closed, and the test words remaining in each DaFF are shifted from the Dnl-1FF through the buffer by a clock signal and output to the RAM.

As an effect of the present invention, the input signal to be encoded is RAMK
Since the check words output from the circuit of the present invention to RA and M are combined with the information words stored in the RAM, they are stored in the RAM as two-elite Solomon encoded blocks. Therefore, as a whole error correction code system, the next interleaving is performed using this RA.
It can be put into a state where it can be executed immediately with "M"2. When a combination of dual encoders (CI, C2) and interleaving is performed, such as in the case of compact discs, the entire system is integrated into one IT A.
Since it can be configured from M and an encoder, the system system can be simplified.

BEST MODE FOR CARRYING OUT THE INVENTION Specific examples will be described below. FIG. 2 is a circuit block diagram of the C2 encoder.

Regarding the C2 encoder, the primitive polynomial and generator polynomial are shown in equations (1) and (2). The D-type FFs include I)o FFI to D3 FF4, and the g coefficient circuits include g coefficient circuits 5 to g3 coefficient circuits 8. Each coefficient circuit receives an input signal g. ,~rg
Multiply by 3. In the figure, the multiplication width of the primitive light is shown, but in the actual circuit, it is expressed as a polynomial and the product with the human input signal is calculated.

The input signal 22 is input from the RAM (not shown) to the OR circuit 9 (hereinafter all OR circuits mean exclusive OR circuits) via a data bus. When the human power control signal 21 is H', the gate circuit 10 is opened and the human power signal 22 passes through the gate circuit 10 to each ga.
The coefficient circuits 5 to 8 are manually operated. Note that the input signal 22 is (3
)A27#A261...
・He comes in.

The output of the go coefficient circuit 5 is directly output. The outputs of gl"""-g3 coefficient circuits 6 to 8 are inputted manually to FFI, but the outputs of gl"""-g3 coefficient circuits 6 to 8 are input to 'DFFI to D2FF by OR circuits 11 to J3, respectively.
D, FF2~D3FF,
4 will be done manually. The output of D31i'F4 is added as 23a to the human input signal 22 in the OR circuit 9.

Clock signal 24 shifts data through the circuit. When the last human input data A4 is input manually, the input control signal 21 becomes L'', the gate circuit 10 is closed, and the 3-state buffer station becomes conductive.At this time, D3FF4 to DoFF1 are filled with the remainder term of the division result. remains. This is the check word A3 of the Reed-Solomon code.
+ A2 + At + An. In this state, since clock number 1 U arrives, the test word A3 and the following are outputted from D3FF4 to the data bus as an output signal 23b via the 3-state buffer 25. Also, since the gate circuit 10 is closed, a zero signal is input, so each one is different. FF2 to D3FF4 have an output of zero.

Since the above check word A o ''-A s is stored in the RAM and the Reed-Solomon code is easily held as a block signal in the RAM, subsequent interleaving operations can be performed in a timely manner.

Note that the C1 encoder also uses the same generating polynomial and therefore has the same circuit configuration, so its details will be omitted here.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the principle of Reed-Solomon encoding, and FIG. 2 is a circuit block diagram of a specific embodiment of the present invention. 1~4...Da Mitsurilipflop a='0~3),
5-8...ga coefficient circuit (a=0-3), 9, 11
, 12, 13...OR circuit, 10...gate circuit, addition...data bus, n...input signal, 23a, b...output signal of D3 flip 70 tube, 2
4...Clock, 25...3 suite buffer, 26...Clear signal.

Claims (1)

[Scope of Claims] A block signal consisting of a plurality of words stored in a RAM is manually inputted to generate a check word of a Reed-Solomon code, and then the circuit outputs the 1 (AM) again to the generating polynomial x ``10 gm, However, a is the same as above a), and the output signal of the DIn-1 flip-flop among the Da flip-flops is added to the input signal from the RAM, and this is added to the g8 coefficient circuit through the gate circuit. In addition, among the 70 Da flip-flops, the output of the go coefficient circuit is input to the Do flip-flop, and the output of the previous stage Da-1 flip-flop and the output of the gaQ number circuit are input to the other 70 Da flip-flops. The Da mitsu flip-flop and the ga
The connection between the coefficient circuits is set, and the gate of the gate circuit is opened so that data is shifted and inputted from the RAM by the clock signal for each block signal to each of the go coefficient circuits, and When the input is completed, by closing the gate of the gate circuit, the test hood remaining in each Da flip-flop is supplied from the Drn-□ flip-flop to the RAM by the clock signal through the buffer. A Reed-Solomon code/encoding circuit featuring: