JPS60152057A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60152057A JPS60152057A JP59007215A JP721584A JPS60152057A JP S60152057 A JPS60152057 A JP S60152057A JP 59007215 A JP59007215 A JP 59007215A JP 721584 A JP721584 A JP 721584A JP S60152057 A JPS60152057 A JP S60152057A
- Authority
- JP
- Japan
- Prior art keywords
- type
- diode
- junction
- region
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、＃！ｉに２種以上の電源電
圧を必要とする装置に好適な半導体装置に関するもので
ある。[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device. The present invention relates to a semiconductor device suitable for devices requiring two or more types of power supply voltages for i.
半導体装４、とりわけＭ Ｎ ＯＳ （Ｍｅｔａｌ Ｎ
１ｔｒｉｄｅＯｘｉｄｅ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ
） ｉランジスタをメモリ菓子としているよりなＥＥ
ＦＲＯＭでは、例えばゲート電圧として２０Ｖが、また
モード選択用として１０ｖが必要とされる等、２種類の
電圧が必要とされる。この種の電圧は通常半導体装置外
から印加しているが、その煩雑さを避けるため、半導体
装置内に形成した内部昇圧回路で生成することが考えら
れる。この場合異なる電圧を生成するために、は電圧に
対応しｆｃ耐圧を有するダイオード等の素子を電圧数だ
け設ける必要がある。このため、前述の例では２０Ｖ、
ＩＯＶの各耐圧を有するダイオードを半導体装置内に形
成する必要がある。Semiconductor devices 4, especially M N OS (Metal N
1trideOxide Sem1conductor
) Yorina EE that uses i-transistor as a memory confectionery
FROM requires two types of voltages, for example, 20V as a gate voltage and 10V as a mode selection voltage. This kind of voltage is normally applied from outside the semiconductor device, but in order to avoid the complexity, it is conceivable to generate it in an internal booster circuit formed within the semiconductor device. In this case, in order to generate different voltages, it is necessary to provide as many elements as the number of voltages, such as diodes, which correspond to the voltages and have fc withstand voltages. Therefore, in the above example, 20V,
It is necessary to form diodes having respective breakdown voltages of IOV in the semiconductor device.
このように耐圧の異なるダイオードを形成するためＫＦ
ｉ各ダイオードにおける不純物の導入量を変える方法が
考えられる。しかし、この方法では各ダイオードを形成
するために夫々個別に不純物をドープさせなければなら
ず製造工程が繁雑なものになってし貫うという問題が生
じる。In order to form diodes with different breakdown voltages, KF
One possible method is to change the amount of impurity introduced into each diode. However, this method has the problem that each diode must be individually doped with an impurity to form it, making the manufacturing process complicated.
本発明の目的＃ｉ製造工程を複雑にすることなくかつ占
有面積を極端に大′１ｆｃは小にすることなく耐圧の異
なるクイオードを得ることができ、これにより異なる基
準電圧な容易に得ることのできる半汎体装丁りを提供す
ることにある。Purpose of the present invention #i It is possible to obtain quardios with different withstand voltages without complicating the manufacturing process and without making the occupied area extremely small. This makes it possible to easily obtain different reference voltages. Our goal is to provide a semi-universal binding that is possible.
本発明の前記ならびにそのほかの目的と新規な％徴は、
本明細曹の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel characteristics of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すわば、下記のとおりである。A brief summary of typical inventions disclosed in this application is as follows.
すなわち、同一プロセスで製造しｆｃ接合の形状の異な
る２種類のダイオードの異なる接合耐圧を利用して夫々
異なる耐圧の定電圧ダイオードとして構成することＶＣ
より、同一プロセスでかつ同一の不純物導入量で異なる
耐圧のダイオードを形成でき、しかも極端に大小のない
占有面積で形成でき、こねにより異なる基準１イ、圧を
容易に得ることができるものである。In other words, by utilizing the different junction breakdown voltages of two types of diodes manufactured by the same process and having different fc junction shapes, they are configured as constant voltage diodes with different breakdown voltages.VC
Therefore, diodes with different withstand voltages can be formed in the same process and with the same amount of impurity introduced, and can be formed in an area that is not extremely large or small, and different standard pressures can be easily obtained by kneading. .
第１図（Ａｌ−（Ｄｉは本発明をＭＮＯＳ）ランジスタ
をメモリセルとするＥＥＰＲＯＭに適用した実施例の製
造工程１哩の断面図であり、第２図は完成状態の平面図
である。以下、製造工程に従って説明する。FIG. 1 is a cross-sectional view of one step in the manufacturing process of an embodiment applied to an EEPROM using an Al-(Di represents the present invention as MNOS) transistor as a memory cell, and FIG. 2 is a plan view of the completed state. , will be explained according to the manufacturing process.
先ず第１図（Ａ）のように、例えばＮ型のシリコン単結
晶基板（手導体基板）１の主面に基板の選択的な熱酸化
によりフィールド絶縁Ｂ！Ａ（Ｓｉ２０膜）２を形５Ｖ
（、、このフィールド絶縁膜２によりメモリセル領域３
、ｍｌのダイオード領域４、第２のダイオード領域５を
画成する。その上で、ボロン等のＰ型不純物を低濃度で
工面に拡散しＰ型低嬢度ウェル領域６． ７． ８を各
伸域３，４．５に形成する。First, as shown in FIG. 1A, field insulation B! is applied to the main surface of, for example, an N-type silicon single crystal substrate (hand conductor substrate) 1 by selective thermal oxidation of the substrate. A (Si20 film) 2 type 5V
(,,This field insulating film 2 allows the memory cell area 3 to
, ml, and a second diode region 5 are defined. Then, a P-type impurity such as boron is diffused into the work surface at a low concentration to form a P-type low-density well region 6. 7. 8 is formed in each stretch area 3, 4.5.
次いで同図（Ｂｌのようにメモリセル領域３の一部と、
第１のダイオード領域４の全何と、第２のダイオード領
域５の略中央部とを除いた部分にホトレジストマスク９
を形叙し、ボロン等のＰ型不純物を拡散又はイオン打込
みする。こねにより、メモリセル領域３のＰ−型ウェル
６にはＰ型のウェルコンタクト１０が形成さね、第１の
ダイオード領域４のＰ−型ウェル７には帯状にＰｍ層１
１が形成さＪｌ、ｖＰｊ２のダイオードル１域５のＰ−
型ウェル８には略中央ＫＰ型層１２が形成さｆする。こ
れらのＰ型層（Ｐ型半導体領域）１１．１２は夫々同−
深さに形成されることは言うまでもない。Next, in the same figure (as shown in Bl, a part of the memory cell area 3,
A photoresist mask 9 is applied to the entire first diode region 4 except for the approximate center of the second diode region 5.
and diffuse or ion-implant P-type impurities such as boron. By kneading, a P-type well contact 10 is formed in the P-type well 6 of the memory cell region 3, and a band-shaped Pm layer 1 is formed in the P-type well 7 of the first diode region 4.
1 is formed Jl, vPj2 diode 1 region 5 P-
A substantially central KP type layer 12 is formed in the type well 8. These P-type layers (P-type semiconductor regions) 11 and 12 are the same as -
Needless to say, it is formed at great depth.
次に同図（Ｃ１σ）ように、メモリセル領域３上に薄い
ｓｔｏ、膜１６．その上のＳｔ、Ｎ、膜１５．その上の
多結晶シリコン層１４およびＳＩＯｔＭ１６よりも厚い
８１０．［１３，その上の多結晶シリコン＃１４を常法
により形成しｆｃ上で、リン等のＮ型不純物を基板１主
面に拡散又はイオン打込みする。Next, as shown in the same figure (C1σ), a thin sto film 16. St, N, film 15. Thicker than the overlying polycrystalline silicon layer 14 and SIOtM 16 810. [13. Polycrystalline silicon #14 is formed thereon by a conventional method, and an N-type impurity such as phosphorus is diffused or ion-implanted into the main surface of the substrate 1 on fc.
このとき、前記ウェルコンタクト１０上にはホトレジス
トマスク１７を設けておくことが好ましい。At this time, it is preferable to provide a photoresist mask 17 on the well contact 10.
これによりメモリセル領域３にはゲートＴＩ１．＆に自
己整合的にＮ＋型ンソー・ドレイン７１１Ｂが形成され
、メモリセルとしてのＭＮＯＳ）ランジスタＱＭおよび
スイッチング用ＭＯ８ＦＥＴＱｓが構成さ熟る。また、
第１のダイオード領域４１Ｃは浅いＮ＋型層１９が形成
され前記Ｐ型層１１とでダイオードＤ、が構成される。As a result, the memory cell area 3 has gates TI1. An N+ type drain 711B is formed in a self-aligned manner at &, and an MNOS (MNOS) transistor QM as a memory cell and a MO8FET Qs for switching are completed. Also,
In the first diode region 41C, a shallow N+ type layer 19 is formed, and together with the P type layer 11, a diode D is configured.
更にＷ４２のダイオード領域５には全面ＫＮ＋型層２０
が形成され前記Ｐ型＃１２とでダイオードＤ２が構成さ
れる。Furthermore, a KN+ type layer 20 is formed on the entire surface of the diode region 5 of W42.
is formed, and together with the P type #12, a diode D2 is constructed.
この状態での平面図を第２図ｒＣ示す。第２図のＩＣ−
ＩＣ切断線に沿う断面が第１図（Ｃ１である。A plan view in this state is shown in FIG. 2rC. IC- in Figure 2
A cross section along the IC cutting line is shown in FIG. 1 (C1).
ホトレジスト１７は除いである。The photoresist 17 is excluded.
第１図（Ｃ１および第２図より明らかなように、ダイオ
ードＤ、とり、とでにＰＮ接合の形状および接合近傍で
の不純物の分布が異なる。ダイオードＤ、では、晶諧度
（Ｎ＋型とＰ型）領域同志の接合がＰ＋型領域１１に沿
−）ｆｃ帯状の部分に基板表面ＶＣＸｆＩ−行な平面状
にでき、他ＶｉＭＪ饋度（Ｎ 型）領域と低濃度（Ｐ−
型）領域との接合が、高濃度領礒同志の接合より浅い部
分に、基板表面に平行な平面状にできる。ダイオードＤ
、では、高濃度（Ｎ＋型とＰ型）領域同志の接合がＰ＋
型領域１２の側面を囲む部分にでき、他は高酋度（Ｎ型
）＠域と低濃度（Ｐ−型）ｇｉ域との接合が、菌濃度同
志の接合より深い部分に、基板表面に平行な平面状にで
きる。As is clear from Figure 1 (C1) and Figure 2, the shape of the PN junction and the distribution of impurities near the junction are different between the diode D and the diode D. Junctions between the P-type (P-type) regions are formed along the P+-type region 11 along the -)fc band-like part in a plane along the substrate surface (VCXfI-), and other ViMJ (N-type) regions and low concentration (P-
The junction with the (type) region can be formed in a plane parallel to the substrate surface in a shallower part than the junction between high-concentration regions. Diode D
, the junction between the high concentration (N+ type and P type) regions is P+
The junction between the high-intensity (N-type) @ region and the low-concentration (P-type) gi region is formed deeper than the junction between the two bacterial concentrations, and on the substrate surface. Can be made into parallel planes.
しかる上で、同図の）のように層間絶縁膜とじてのフォ
スフオシリケードガラス（ＰＳＧ）膜２１を形成し、か
つコンタクトホールな形成し７た上でアルミニウム（Ａ
Ｊ）配線層２２を形成することによりＦｒ要の半導体装
置が構成されるととＫなる。Then, as shown in the figure), a phosphosilicate glass (PSG) film 21 is formed as an interlayer insulating film, contact holes are formed, and aluminum (A) is formed.
J) If a semiconductor device requiring Fr is constructed by forming the wiring layer 22, then K is obtained.
なお、図示していないが、Ｎ 型半導体領域２０および
ｐ−！Ｊ領域７に対してもＡ７配線が１ｐ続される。Although not shown, the N type semiconductor region 20 and the p-! 1 p of the A7 wiring is also connected to the J region 7.
以上のように形成された半導体装ｔｇ！は、第３図１の
よりにダイオードＤＩ＋ ダイオードＤ２が夫々個別に
内部昇圧回路２３ｖｃ接続されて定電圧回路１１＋Ｕ？
を構成し、ダイオードＤ、を定電圧ダイオードとした定
電圧回路り、はＭＮＯＳゲート１３に電圧■、を供給し
、ダイオードＤ、を定電圧ダイオードとした定電圧回路
り、Ｆｉモード選択＃１１１ｔ圧Ｖ、を供給するよう構
成さ才する。Semiconductor device tg! formed as described above! According to FIG. 3, diode DI+ and diode D2 are individually connected to the internal booster circuit 23vc to form a constant voltage circuit 11+U?
, a constant voltage circuit with diode D as a constant voltage diode, supplies voltage to the MNOS gate 13, and a constant voltage circuit with diode D as a constant voltage diode, Fi mode selection #111t voltage V, is configured to supply V.
この構成によれば、各定電圧回路Ｌ１．Ｌ２の定電圧ダ
イオードはダイオードＤ１ とダイオードＤ、とで構成
されている−＋め、第４図のグラフから判るように両ダ
イオードＤｌ＊Ｄ！の接合耐圧の相違により、各回路Ｌ
ｌ＊Ｌ２の基準となる電圧も必然的に異なる。すなわち
、ダイオードＤ。According to this configuration, each constant voltage circuit L1. The constant voltage diode L2 is composed of a diode D1 and a diode D. As can be seen from the graph in FIG. 4, both diodes Dl*D! Due to the difference in junction breakdown voltage, each circuit L
The reference voltage of l*L2 is also necessarily different. That is, diode D.
とり、とでは、前述した理由によりＰＮ接合を逆バイア
スＬ、ｆｃときの降伏１ｒ、圧すなわち逆方向の接合耐
圧が異なる。こ第１を第４図に示す。第４図において、
縦軸は前記ＰＮ接合の接合耐圧（Ｖ）を示し、横ｍ１ｔ
Ｐ型不純物セしてのボロンのドーズ量を示す。なお、Ｎ
型領域１９．２０のｆｃ Ｗ＞のＮ型不純物としての
リンのドープ−８ｔＦｉＩ Ｘ １０”（個／ｆｆ１）
で一定としである。For the reason described above, the breakdown voltage 1r when the PN junction is reverse biased L, fc, that is, the junction breakdown voltage in the reverse direction is different. The first example is shown in FIG. In Figure 4,
The vertical axis indicates the junction breakdown voltage (V) of the PN junction, and the horizontal axis m1t
The dose amount of boron including P-type impurity is shown. In addition, N
Doping of phosphorus as N-type impurity in type region 19.20 fc W> - 8tFiI x 10'' (pieces/ff1)
It is assumed that it is constant.
第４図より明らかなように、同一のホロンドープ量に対
してダイオードＤ１の接合耐圧がダイオオードＤ２のそ
れに対して小さい。ダイオードＤＩＩＤ、において、ボ
ロンドープ鴛を変化させても、略一定値だけ、沖合耐圧
が異なる。リンドープ値を変化させれば接合耐圧も変化
するが、ダイオードＤ、の接合耐圧が小さいことは同一
である。なお、リンドープ量を増せは接合耐圧は小さく
なる。As is clear from FIG. 4, the junction breakdown voltage of diode D1 is smaller than that of diode D2 for the same amount of holon doping. In the diode DIID, even if the boron dope is changed, the offshore breakdown voltage differs by a substantially constant value. If the phosphorus doping value is changed, the junction breakdown voltage also changes, but the fact that the junction breakdown voltage of diode D is small is the same. Note that as the amount of phosphorus doped increases, the junction breakdown voltage decreases.
第】図に示す実施例では、ダイオードＤ、の接合耐圧を
約１１ｖ１ダイオードＤ、のそれを約１７Ｖとしている
。このために、Ｎ＋型領領域１９２００ｆｃめのＮ型不
純物と１５１のリンのドープ艮を１ｘ １（Ｉｊ１１個
／ｃｒｒｆとし、Ｐ型領域１１．１２のためのＰ銅不純
物とし、てのボロンのドーフ曾を３×１０目個／ｄとし
ている。これから定電圧回路ＬＩ＋Ｌ２の基準電圧を夫
々ＩＩＶ、１７ＶＫ股定できることになる。In the embodiment shown in the figure, the junction breakdown voltage of diode D is approximately 11V1, and that of diode D is approximately 17V. For this purpose, the N-type impurity for the N+ type region 19200fc and the phosphorus doping for 151 are set to 1x 1 (Ij11 pieces/crrf), the P copper impurity for the P-type region 11.12, and the boron doping for the It is assumed that the number is 3×10/d.From this, the reference voltages of the constant voltage circuit LI+L2 can be determined as IIV and 17VK, respectively.
なお、ダイメートＤＩ＋ ダイオードＤ、の各面積（Ｎ
／茜、Ｐ層）を変化１−ることにより、耐圧を微小変化
することができる。In addition, each area (N
/Akane, P layer), the breakdown voltage can be slightly changed.
（１） 同一プロセスで形ｂＭ ｔ、た８１１ｆ１のダ
イオード（Ｄｌ）と第２の夕゛イオード（Ｄ２ ）を夫
々個別に定電圧ダイオードと１．て構成しているので、
第１のダイオードと第２のダイオードとの接合耐圧の相
違によって異なる定電圧を容易に得ることができる。(1) In the same process, a diode (Dl) and a second diode (D2) of the type bMt and 811f1 were separately converted into a constant voltage diode and 1. Since it is configured as follows,
Different constant voltages can be easily obtained depending on the difference in junction breakdown voltage between the first diode and the second diode.
（２）第１のダイオードと第２のダイオードを同一プロ
セスでかつ同一不純物濃度で形成１２ても異なる耐圧を
得ることができるので、製造工程の簡易化を図ることが
できる。(2) Even if the first diode and the second diode are formed in the same process and with the same impurity concentration, different breakdown voltages can be obtained, so the manufacturing process can be simplified.
＋３１ ０１１のダイオードと第２のダイオードの耐圧
の相違により、同一プロセスで異なる耐圧の定電圧ダイ
オードを得ることができかつ異なる２ｆ！Ｊ類の定電１
圧を得ることができるので、ＥＥＰＲＯＭのような２種
類の電圧を必要とする半導体装置の設計、製造を容易な
ものにできる。Due to the difference in breakdown voltage between the +31 011 diode and the second diode, it is possible to obtain constant voltage diodes with different breakdown voltages in the same process, and also with different 2f! Class J constant voltage 1
Since the voltage can be obtained, it is possible to easily design and manufacture a semiconductor device such as an EEPROM that requires two types of voltage.
以上本発明者によってなさｔまた発明を実施例にもとづ
き具体的に説明したが、本発明は上記実施例に限定さ贋
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。たとえは、ダイオー
ドＤ、やダイオードＤｔのＸＦ−面形状や接合面積、ま
た不純物の種類を変更することにより耐圧を実施例以外
の値に変化させることもできる。東に、ダイオードＤ１
１ ダイオードＤ２を袖々の規格で製造することにより
、３種類以上の定電圧を得ることもできる。Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the breakdown voltage can be changed to a value other than those in the embodiments by changing the shape of the XF-plane, the junction area, or the type of impurity of the diode D or diode Dt. To the east, diode D1
1. Three or more types of constant voltages can be obtained by manufacturing the diode D2 according to various specifications.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるＭＮＯＳ）ランジス
タをメモリセルとするＥＥＰＲＯＭに適用した場合につ
いて説明したが、それに限足されるものではなく、フロ
ーティングゲート型のメモリセルからなるＥＰＲＯＭや
その他の２種類以上の定電圧を必要とする種々の半導体
装置に適用できる。In the above explanation, the invention made by the present inventor was mainly applied to the EEPROM whose memory cells are MNOS (MNOS) transistors, which is the field of application in which the invention was made by the present inventor, but the invention is not limited to this. It can be applied to EPROMs consisting of gate-type memory cells and other various semiconductor devices that require two or more types of constant voltages.
第１図（Ａｌ−（ＤＪは本発明の実施例を製造工程順に
示す断面囚、
第２図はその概略平面図１、
第３図は回路構成図。
第４図は接合耐圧の特性グラフである。
１・・・半導体基板、２・・・フィールド絶縁膜、３・
・・メモリセル領域、４・・・第１のダイオード佃域、
５・・・第２のダイオード領域、６． ７． ８・・・
Ｐ−型ウェル、１１．１２・・・Ｐ＋型層、１８・・・
ソース・ドｖイン領域、１９． ２０−Ｎｆｆ１層、２
ｌ−ＰＥＧ膜、ＱＭ・・・ＭＮＯＳ）ランジスタ、Ｑ８
・・・ＭＯ８ＦＥＴ％Ｄ、・・・第１の降伏電圧を持つ
ダイオード、Ｄ、・・・第２の降伏電圧を持つダイオー
ド。
第１頁の続き
■Ｉｎｔ、Ｃ１，’ 識別記号
Ｈ０１Ｌ ２９／９１
［相］発明者鍋谷 慎二
＠発明者萩原 隆旦
［相］発明者谷１）施工
庁内整理番号
７６３８−５Ｆ
小平市上水本町１４５０１地 株式会社日立製作所武蔵
工場内国分寺市東恋ケ窪１丁目２８幡地 株式会社日立
製作所中央研究所内
国分寺市東恋ケ窪１丁目２８幡地 株式会社日立製作所
中央研究所内Figure 1 (Al-(DJ) is a cross-sectional diagram showing an example of the present invention in the order of manufacturing steps, Figure 2 is a schematic plan view 1, Figure 3 is a circuit configuration diagram. Figure 4 is a characteristic graph of junction breakdown voltage. 1. Semiconductor substrate, 2. Field insulating film, 3.
...Memory cell area, 4...First diode area,
5... second diode region, 6. 7. 8...
P- type well, 11.12...P+ type layer, 18...
Source domain area, 19. 20-Nff1 layer, 2
l-PEG film, QM...MNOS) transistor, Q8
... MO8FET%D, ... diode with first breakdown voltage, D, ... diode with second breakdown voltage. Continuing from page 1 ■ Int, C1,' Identification code H01L 29/91 [Phase] Inventor Shinji Nabetani @ Inventor Ryutan Hagiwara [Phase] Inventor Tani 1) Construction Agency Reference number 7638-5F Kodaira City Josui 14501 Honmachi Hitachi, Ltd. Musashi Factory 1-28 Higashi-Koigakubo, Kokubunji City Hitachi, Ltd. Central Research Laboratory 1-28 Higashi-Koigakubo, Kokubunji City Hitachi, Ltd. Central Research Laboratory
Claims (1)
のダイオードと第２の降伏電圧を持つ第２のダイオード
を夫々個別ＫＱ電圧ダイオードとして構成し、６異なる
接合耐圧によって異なる定電圧を得るように構成したこ
とを特徴とする半導体装置。 ２、前記第１のダイオードと前記第２のダイオードとを
同一プロセスでかつ同一不純物濃度で形成してなる特許
請求の範囲第１項記載の半導体装置。[Claims] 1. A first layer formed on a semiconductor substrate and having an fc first breakdown voltage.
and a second diode having a second breakdown voltage, each of which is configured as an individual KQ voltage diode, and is configured to obtain different constant voltages depending on six different junction breakdown voltages. 2. The semiconductor device according to claim 1, wherein the first diode and the second diode are formed in the same process and with the same impurity concentration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59007215A JPS60152057A (en) | 1984-01-20 | 1984-01-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59007215A JPS60152057A (en) | 1984-01-20 | 1984-01-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60152057A true JPS60152057A (en) | 1985-08-10 |
Family
ID=11659773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59007215A Pending JPS60152057A (en) | 1984-01-20 | 1984-01-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60152057A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0533439A2 (en) * | 1991-09-20 | 1993-03-24 | Hitachi, Ltd. | Constant-voltage diode, power converter using the same and process of producing constant-voltage diode |
| US6769416B2 (en) | 2001-05-11 | 2004-08-03 | Mitsubishi Denki Kabushiki Kaisha | Evaporated fuel processing module |
| JP2007335882A (en) * | 1992-09-21 | 2007-12-27 | Siliconix Inc | BiCDMOS STRUCTURE AND MANUFACTURING METHOD THEREOF |
-
1984
- 1984-01-20 JP JP59007215A patent/JPS60152057A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0533439A2 (en) * | 1991-09-20 | 1993-03-24 | Hitachi, Ltd. | Constant-voltage diode, power converter using the same and process of producing constant-voltage diode |
| EP0533439A3 (en) * | 1991-09-20 | 1994-07-27 | Hitachi Ltd | Constant-voltage diode, power converter using the same and process of producing constant-voltage diode |
| JP2007335882A (en) * | 1992-09-21 | 2007-12-27 | Siliconix Inc | BiCDMOS STRUCTURE AND MANUFACTURING METHOD THEREOF |
| US6769416B2 (en) | 2001-05-11 | 2004-08-03 | Mitsubishi Denki Kabushiki Kaisha | Evaporated fuel processing module |
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