JPS60151692A - Crt display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention This invention provides a method for transferring data from a video memory to a cRTJ:
-C RT that can be displayed while viewing
It's about the display.

(b) Prior Art and Problems First, an example of a configuration diagram of a CRT display is shown in FIG. 1.

In FIG. 1, 1 is a CRT display puller, 2 is a video memory, 3 is a character generator, 4 is a shift resolution, and 5 is a CRT.

The bus 6 transfers the line counter output from the CRT display controller 1 to the controller 3.

The video memory 2 has a video memory address via the bus 7,
Video memory data via bus 8 and a video memory write signal based on signal 1≦ are input.

Then, the video memory 2 outputs the image stored in the video memory 2 to the character generator 3 through the bus IO.

Ki,)・Rough Kuji. , inverter 3 is video memory 2 h)
A character pattern 7 is generated from the video memory data and the light/color/return output via the bus 6, and is sent to the shift resolution screen 4 through the lotus 11.

The shift resolution 4 converts the character butter 7 received as a parallel signal into a serial signal in synchronization with the bit' clock through the signal line 13 and sends it to the CRT 5.

Then, the bright spot on the CRT 5 is made to shine brightly with the logic "IJ" and darkened with the logic "0".

Next, an example of the display on the CRT 5 is shown in FIG.

FIG. 2 shows "0" to "
This shows a state in which the contents up to address 2 are displayed. To display new information on CRT5, press C'
The video memory address from the RT display controller 1 is sequentially increased from "1" to "3", "2" to "4", etc. As a result, the image displayed on the CRT 5 in FIG. 2 moves upward, creating an empty area at the bottom of the screen of the CRT 5. The contents of addresses "3" and "4" of the video memory 2, which are new information, are displayed in this empty area.

Figure 2 shows that the size of the video memory 2 is from address "0" to "7".
This is an example of a case in which 23 words of data up to an address can be stored.

In Figure 2, when "5" to "7" of video memory 2 are displayed on the CRT 5, when the next video memory address comes, "6" is displayed.
It is necessary to display the contents of "8" on the CRT 5.

However, in the example shown in FIG. 2, the capacity of the video memory 2 is only 23 words, so when "6" to "8"
'' address has no video memory and can only display data.

In this situation, the first "0" after address "7"
In order to display address data, conventional measures have been taken such as having a video memory that repeatedly stores the contents of "0" to "7" after address "8" in the video memory 2.

(C) Purpose of the Invention The present invention provides a CRT display that allows the payment information in the video memory 2 to be scrolled and displayed on the CRTS without storing data redundantly in the video memory 2. It is something to do.

(d) Embodiment of the Invention First, a block diagram of an embodiment of the invention is shown in FIG.

FIG. 3 is a diagram showing the relationship between the CRT display controller 1 and the video memory 2 shown in FIG. 1 in more detail.

In FIG. 3, a decoder 14 is connected between the CRT display controller 1 and the video memory 2.

This decoder 14 is included in the video memory 2 and is often not shown in the block diagram of FIG. 1, or is specifically shown for clarity of content.

The video memory address by bus 7 in FIG. 1 consists of m bits. Figure 3 is an example when m=6,
The bus 7 in FIG. 1 is represented by 6-bit signals on signal lines 71 to 76 in FIG.

Since the capacity of the video memory 2 is 23 words, the input of the video memory 2 has 3-bit terminals 21 to 23 as addresses. Signal lines 71 to 73 are connected to these terminals 21 to 23, respectively.
is connected to transmit the video address output from the CRT display controller 1 to the video memory 2.

In addition to this, a selection signal via a signal line 15 is input to a terminal 24 of the video memory 2 .

When the selection signal from the signal line 15 is logic "0", the video memory 2 does not output a signal to the bus 10, and when the selection signal is logic "1", the contents of the video memory 2 specified by the address input are transferred to the bus 10. Output to 10.

The selection signal is the output signal of the decoder 14, and the selection signal is the output signal of the decoder 14.
4 operates by receiving signals from signal lines 75 and 76 as input.

In the embodiment shown in FIG. 3, when the logic values of the signals on the signal lines 75 and 76 are both "0", the decoder 14 outputs the logic value "1".
" is output.

Each signal from signal lines 71 to 76 is 1. Each has a value expressed as a binary code with a weight of 20 to 25.

Next, select the values of the signals from the signal lines 71 to 76,
The state of the video memory address input and bus 10 is shown in FIG.

Note that it is difficult to understand if the video memory address line and video memory address input are displayed in binary code, so in Figure 4 they are 8
Displayed in decimal notation.

In this invention, when the capacity of the video memory 2 is set to 21 words, the (n+1)th bit of the video memory address is not decoded, and the case of n-3 will be explained as an example.

The relationship between each signal on the signal lines 76 to 71 in FIG. 3 and the video memory address is as shown in FIG. 4.

Signal f17 in Figure 4 (3 to 71 are "00" to "07")
Up to the address, each signal on the signal lines 74 to 76 is logical [Oj. Therefore, the output of the decoder 14 receiving the signals from the signal line 75 and the signal line 76 becomes a logic "1", and the selection signal on the signal line 15 becomes a logic "1".

When the logical value of the selection signal becomes "1", the address input of the video memory 2 becomes "enabled", and the address input of the video memory 2 changes from "0" to "
7'' address is output to the bus 10, and the data in the video memory 2 is displayed on the CRT 5.

Signal lines 76 to 71 are from addresses "10" to "17",
The logic value of the signal line 74 = rlJ, the logic value of the signal line 75 = "0", and the logic value of the signal line 76 = 2rOJ.

n+1 bi) l) Since the signal line 74 that corresponds to the eye is not connected anywhere, the address input of the video memory 2 is
As shown in the figure, the address values "0" to "7" are entered manually.

On the other hand, the input of the decoder 14 includes a signal line 75 and a signal line 7.
Since the logic value of these signals is "0", the output of the decoder 14, that is, the logic value of the selection signal becomes "1". Therefore, the contents of the video memory 2 from address "0" to address "7" are output to the bus 10.

The information outputted to the bus 10 has exactly the same contents as in the case where the video memory addresses are "00" to "07" as described above.

If the video memory address is "20" or more, the signal line 75 and the signal li! Since one or both of the logic values of 76 are "1", the selection signal through the signal line 15 is always logic "0", and no signal from the video memory 2 is output to the bus 10.

In this way, according to the configuration shown in FIG. 3, the CRT 5 shown in FIG.
Since data at address "0" is displayed next to address "7" in J:, the contents of the video memory 2 are displayed without being scrolled.

(e) Effects of the Invention According to the present invention, when the video memory stores 2 bits of data, the n+1th bit of the video memory address is not decoded, so there is no overlap in the video memory. CRTJ, without storing data.
The contents of the video memory can be displayed while scrolling.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a CRT display, FIG. 2 is a diagram showing an example of the display on the CRT 5 shown in FIG. 1, FIG. 3 is a block diagram of an embodiment according to the present invention, and FIG. FIG. 3 is a diagram showing the relationship between each signal and the address of the video memory. l...CRT display controller, 2.
...Video memory, 3...Character generator, 4...Shift register, 5...
・CRT16-8...Bus, 9...Signal a, IO...Bus, 11...Bus, 12...
13...Signal line, 14...Decoder, 15
...Signal line, 21-24 ...Terminal, 71
~76...Signal line agent Patent attorney Kinji Komata (Figure 1, Figure 3) 14

Claims (1)

[Claims] 1. A CRT display comprising a CRT display controller that outputs a video memory address, and a video memory that outputs video memory data by manually inputting the video memory address, wherein the video memory is 2r.
1. A CRT display characterized in that the CRT display is configured not to decode n+l pinotolo of the video memory address from the CRT display controller when data of bits fα is being written.