JPS59111739A - Image display apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Portion of the Invention] The present invention is directed to a so-called television monitor device.
An image display device that sequentially imports image information consisting of gradation information for each pixel from a storage circuit or the like for each image, converts the gradation information C into a display image corresponding to a predetermined display gradation, and displays the image. .

[Technical background of the invention and its problems]

When the gradation information of each pixel is converted into display gradation information such as predetermined gradation information or color information and displayed on a television monitor, the original image information (range of the gradation information of the pixel in 2) is Conventionally, a certain portion has been displayed in association with the entire range of gradations such as gradation that can be displayed.

For example, if the gradation values (gradation values) of image information are distributed between 0 and 1026, and the gradation values of image information are distributed between 0 and 1026, and Assuming that there are 64 levels of gradation that can be expressed (displayed) (represented by gradation values 0 to 66), and that parts of the original image information whose gradation values are in the range of 500 to 627 are to be displayed in gradation. For pixels whose image gradation value is 499 or less, the gradation value of the display image is determined by a linear equation.For pixels whose original image gradation value is 500 or more and 627 or less, the gradation value of the display image is determined by a linear equation.

For pixels whose gradation value in the original image is 628 or more, the display gradation value is 6.
It will be displayed as 4°.

FIG. 1 shows a main part configuration of an example of such a conventional image display device, in which a clock signal output from an oscillation circuit 1 is counted by a counting circuit 2, and a television monitor (not shown) is It also generates synchronizing signal SS for CRT scanning for display at C2 and CRT scanning position C.
2. Correspondingly, the address data AD for the original image information storage circuit B, which stores the gradation values of all pixels of the original image in advance, is generated, and the gradation value data GD of each pixel is extracted. The conversion circuit 4 converts the gray level into an analog signal DA, which is sent to the television monitor together with the cathode ray tube scanning signal ss.

'#! FIG. J2 shows an example of a specific configuration of the gray scale conversion circuit 4 in FIG. 1. The gradation value data DD is read out from the memory circuit 41 using the gradation value data CD which is the output of the memory circuit 6 shown in FIG.
The contents of the memory circuit 41, which is converted into an analog signal DA by the A (digital/analog) converter 42 and outputted, are written in advance by a data processing device C2 (not shown). Conventional devices of this kind have the above-mentioned configuration, and since the operation of the grayscale conversion circuit 4, that is, the conversion characteristics are constant within the entire display screen, the display screen is divided into multiple parts to display multiple images on one screen. A problem occurred when displaying C2.

For example, a first image whose pixel gradation values are distributed from 0 to 100 OC and a second image whose pixel gradation values are distributed from 0 to 50 (two distributions) are simultaneously (
2. When displaying (2) If the operation of the gradation conversion circuit 4 is set to match the first image and the pixel gradation value of 1000 is the maximum density, the second image can hardly be displayed in gradation. i2.

The device that eliminates the above-mentioned drawbacks has the configuration shown in FIG.
For example, when dividing the sections as shown in Figure 4, Figure 6.
The discrimination circuit No. 5 discriminates the section and outputs section information, and the section information C2 is controlled to select one of the gradation value sequences prepared for each section as shown in FIG. Therefore, there is a cost disadvantage in that it is necessary to have as many gradation value storage circuits as there are sections.

[Purpose of the invention]

The present invention is based on the above-mentioned circumstances Cf! It was developed based on the idea that multiple images with greatly different ranges of pixel gradation values can be displayed on the same screen with good gradation, and that requires multiple gradation value storage circuits. The purpose of this invention is to provide an image display device that does not.

[First aspect of the invention] In order to achieve the second object, the present invention uses an image display device to display a plurality of images having greatly different ranges of pixel gradation values by determining the maximum effective bit position of the pixel value within a section (from the second It is characterized by outputting grayscale values in accordance with controlled and corrected pixel values 62.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 6, 1 is an excavation circuit that generates a clock signal, and 2 is a counting circuit that divides the clock signal of the oscillation circuit 1. The counting circuit 2 generates a simultaneous signal ss for scanning a cathode ray tube for display on a television monitor (not shown), and also generates address data AD corresponding to the scanning position of the cathode ray tube. 6 is a pixel value storage circuit that stores in advance the gradation values of all pixels of the original image; 5 is a pixel value storage circuit that reads out data corresponding to the address C of each pixel in the pixel value storage circuit 3; the section is determined based on the address data AD; For example, as shown in FIG. 7, this is a partition discrimination circuit that outputs partition information SG based on the top two bits of the X address and Y address. The address data AD from the counting circuit 2 is stored in the pixel value storage circuit 6.
and is input to the partition discrimination circuit 5. The block information SG from the block discrimination circuit 5 is input to a memory circuit 61, which stores the maximum effective bit of the pixel value for each block, and uses the block information SG from the block discrimination circuit 5 as an address. , the maximum valid pit data corresponding to the currently displayed partition is always accessed. Note that this memory circuit 61 can be initialized, that is, all contents can be set to 0, by means not shown.

The output from the pixel value storage circuit 6, that is, each pixel value GD, is input to a control circuit 62 and a shift circuit 64.

This control circuit 62 stores each pixel value GD and the storage circuit 61.
The data OR obtained by calculating the logical sum with the output of is written into the priority determination circuit 66. The priority determination circuit 63 receives the data 0R.
(most significant bit with 1 set) No.
, outputs MS. Output M from priority determination circuit 66
S is input to the shift circuit 64, and this shift circuit 64
is the pixel value CD from the pixel image storage circuit 6 only for the MS.
is shifted to the right and the corrected pixel value MGD is output. The modified pixel value MGD which is the output from the shift circuit 64 is input to the gray value storage circuit 65, and this gray value storage circuit 65 is connected to the M
The gray value DA is output using GD as the address.

Next, the operation of the image display device configured as described above will be described. The operation of this embodiment is illustrated in Figure 7 (2) where an image A with a pixel value distribution of 0 to 100 and an image P with a pixel value distribution of 0 to 500 are displayed on one screen ζ; Let's explain by giving example 62.In addition, the circuit is ', 102,
It is assumed that there are 1 (=2'') tone values, and the range of possible pixel values is 0 to 1026.

In FIG. 6, a clock signal output from an oscillation circuit 1 is counted by a counting circuit 2, and a synchronization signal S for scanning a cathode ray tube for display on a television monitor (not shown) is obtained.
(2) Address data AD for the pixel value storage circuit 6 and section discrimination circuit 5, which store the gradation values of all pixels of the original image in advance in correspondence with the cathode ray tube scanning position, is generated, and the pixel value storage Gradation value data G of each pixel from circuit 6
The partition discrimination circuit 5 to which the address data AD to read D is input discriminates the partition from the address data AD and outputs partition information SG.
Output. Storage circuit 61 (2 is the address of the section information SG, and the maximum effective bit of the pixel value is stored for each section.Next, the storage circuit 61 after scanning the entire screen once from operation C2 of the control circuit 62 The address corresponding to block A and PC is 62 as shown in Figure 8.While scanning block A, the content of 6R data is QQQ1***lk*, so the maximum effective bit number is 6. Similarly - while scanning two sections B, '
? The content of the 5R data is Q1＊＊＊＊＊＊＊＊, so the maximum effective bit number is 8. Therefore, the output MS from the priority determination circuit 63 is 6 while scanning section A, and 6 when section P is being scanned.
8 is output while scanning. The shift circuit 64 shifts the pixel value GB from the pixel storage circuit 6 to the right by the output MS and outputs the corrected pixel value MGB. Therefore, while scanning section A, the pixel value GB shifts 6 bits to the right while scanning section P. In the middle, the pixel value GB is shifted to the right by C28 pits. However, MGD should be considered based on GD shifted 9 bits to the right, and as a result of the above, the DA value output in section A will be 0 to 8.
00(=100*2(9-6)) The value of DA output in section 12 is O~1000(=500*2(''))
becomes.

〔Effect of the invention〕

As described above, in the present invention, regardless of the distribution state C2 of pixel values, images in any section are displayed with gray scale values spanning ten or more ranges of gray scale value sequences. With C2, it is possible to display a plurality of images in one screen with good gradation without changing the gradation value of the original image or having multiple gradation values.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a conventional image display device, FIG. 2 is an example of a specific configuration of the grayscale conversion circuit B in FIG. 1, and FIG. 6 is a diagram of a conventional image display device. FIG. 4 is an explanatory diagram of a divided image for explaining the image display device shown in FIG. 6C, and FIG. FIG. 6 is a diagram illustrating the main part of an embodiment of the image display device according to the present invention (2), and FIG. 7 is a diagram showing the divisions for explaining the image display device according to the present invention. FIG. 8 is an explanatory diagram of the divided images, and is an explanatory diagram showing the contents of the addresses of two windows in section C in the storage circuit of the image display device according to the present invention. 1. Oscillation circuit; 2. ... Counting circuit, 6 ... Pixel value storage circuit, 5 ... Section discrimination circuit, 61 ... Memory circuit, 62 ... Control circuit, 63 ... Priority judgment circuit, 64 ... Shift Circuit, 6... Concentration conversion circuit. Agent: Patent attorney Noriyuki Chika (and 1 other person) No. 7
Figure X Figure 8

Claims (1)

[Claims] a pixel value storage circuit that stores image information consisting of gradation information for each pixel for each pixel; and a section discrimination circuit that determines which section on the display screen each pixel belongs to and outputs section information; A storage circuit that determines the position of the maximum effective bit of the pixel value in the section and stores it in accordance with the section information aII, and the pixel value is controlled by the maximum effective bit position of the section white pixel value. An m31 image display device comprising: a shift circuit that modifies each pixel value output from a storage circuit; and a grayscale 1b storage circuit that outputs a grayscale value according to each modified pixel value.