JPS60150286A - Memory circuit - Google Patents

Abstract

PURPOSE:To sufficiently make the average value and the peak value of a supply current in operation small by decreasing the selection word line electric potential to the intermediate electric potential after the completion of operation. CONSTITUTION:At the time of almost completing a reading out, a word line control signal phix falls, a P channel TRQ301 for driving a word line turns off, and a word line signal Wi goes to the intermediate electric potential determined by P channels TRQ303 and Q304. Because the electric potential of Wi goes to the intermediate electric potential, the function of current of said Q111 decreases, the bit line (BL) electric potential at the selective ''0'' information side continues to fall toward the GND electric potential. On the other hand, concerning the bit line at the non-selectige ''0'' information side, a bit line retaining circuit 303 functions so that the bit line electric potential is maintained almost at a VCC electric potential, thereby a DC current flows via VCC Q305 bit line Q111 Q112 GND. As previously stated, the word line signal Wi which is a gate signal of the Q111, is being an intermediate electric potential, the function of current of the Q111 is considerably reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to memory circuits, and more particularly to asynchronous static memories.

Conventionally, various circuits have been devised to reduce the power supply current during operation of asynchronous static memories that do not require an external clock. First, a typical conventional example will be shown below, and its configuration and operation will be explained.

First, a conventional static memory will be explained with reference to FIG. 1(a).

Address input signal Ai (i-0, 1, 2,...

n) is input to the input buffer 101. In addition, the chip select input signal C8s data input signal DIN and the write enable input signal WE are input to the human buffer 1, respectively.
02 is input. The configurations of input buffers 101 and 102 are shown in FIGS. 1(b) and 1(c), respectively. In the input buffer 101 of FIG. 1(b), the address change detection signal φi is determined by the delay time of the delay circuit 11 when the address input signal Ai changes from low level to high level or from high level to low level. This is a signal that remains at a low level only for a certain period of time. Address input signal Aih Address buffer signal A/i, A/i,
The timing relationship between address change detection signal φi and address change detection signal φi is as shown in FIG.

The clock generator 103 generates an address change detection signal φi (i=0, 1.L...) as shown in FIG. 1(d).

The precharge clock signal φp is generated by ANDing the chip select buffer signal C8/n) and the chip select buffer signal C8/. The precharge clock signal φp is activated when the chip select input signal C8 is at a low level and the address input signal 4i changes, or when the chip select input signal C8
When t is at a high level, memory cell matrix section 10
The bit lines EFL and BL arranged in the bit lines EFL and BL are precharged, that is, the data on the bit lines is reset.

Also, the signal A'i is buffered by the manual buffer 101.

A desired memory cell 109 is selected from A'i by an X address decoder 104 and a Y address decoder 105. DIN control unit 106. The Do+rr control unit 108 controls data writing and reading, respectively. FIG. 1(e) shows the main part of the memory cell matrix section 107. A mesori cell 109 is arranged at each intersection of a plurality of word lines WL and a plurality of bit line pairs BL, BL. Here, the memory cell 109 is a 6-transistor cell having an i0MO8 configuration as shown in FIG. 1(f).Next, the operation of the memory cell matrix section 107 will be explained. Incidentally, the signal waveforms of each part are as shown in FIG. When the memory circuit is selected, that is, when the chip select input signal C8 is at low level.

By switching the address input signal At.

The X address decode signal Xi and the Y address decode signal Yj also switch. On the other hand, as the address input signal At changes, an address change detection signal φl is generated, and thus a precharge clock signal φp is generated. The timing relationship between Xi, Yi, and φp is as follows:
This is the passage shown in FIG.

In FIG. 2, during the period when φp is at low level.

(Xi, Yj are switched) and determined by the address input signal Ai. Only one memory cell address is selected.

- The precharge clock signal φp connects the bit lines BL and B for a certain period including the time when a new memory cell is selected.
Precharge L and reset the state of the bit line.

By using such a precharge clock signal φp, the bit line precharge period is approximately 5 to 1 inch of the operating cycle time, so the average power supply current consumed in the memory cell matrix section 107 is reduced. The value is much lower than that of other conventional methods in which a resistive load is provided at the end of the bit line. This is because in the conventional system in which a resistive load is provided at the end of the bit line, a DC current always flows from the bit line to the memory cell.

However, the non-conventional example also has the following drawbacks from the point of view of the peak value of the power supply current.

That is, as shown in Fig. 2, Xi and Yj are selected,
Even after the read or write operation is complete.

The voltage level of the 1'O''Wg signal side line of the bit lines BL, I'-IL is pulled by the driver transistor Q, 1! of the open memory cell of the transfer gate Q11., and slowly decreases. GNI) potential is lowered to near the potential.Soon, a switch is made to the next address cycle, and a precharge clock signal φp is generated.

All bit lines are charged to Vcc potential. At this time, the peak value of the power supply current reaches a large value probably because one of the bit lines BL and BL is below the GND potential. For example, for 2KX8 bit RAM, Vcc
=5V, the peak value of the power supply current Iccpeak is approximately 100 m' or more. When a RAM with a large power supply peak current is mounted on a board, it is necessary to pay particular attention to pattern design and power supply design, so it is desirable that the power supply peak current is as small as possible.

As described above, the memory circuit configured as in this conventional example has the drawback that the peak value of the power supply current becomes extremely large when precharging the bit line.

An object of the present invention is to provide a memory circuit in which the average value of the power supply current during operation is suppressed to the same level or less as in the conventional example, and the peak value of the power supply current during operation is sufficiently smaller than that in the conventional example.

The memory circuit according to the present invention has memory cells arranged at the intersections of a plurality of bit lines for transmitting data and a plurality of word lines for controlling opening/closing of transfer gates. A word line control circuit that has a function of setting the potential of the word line to a first value lower than the value at the time of the read operation, and a word line control circuit that sets the potential of the unselected bit line to a value at the time of resetting the bit line. and a bit line potential holding circuit that holds the bit line potential at a second value sufficiently close to .

In the memory circuit according to the present invention, the word line control circuit connects the output of the inverter circuit which inputs the address decode signal for word line selection to the gate of the N-channel transistor, and generates a signal generated by a change in the address input signal.
The output of a two-man NAND circuit that receives a clock signal that is at a high level for a certain period of time and the address decode signal for word line selection is connected to the gate of the first P-channel transistor, and the output of the inverter circuit is connected to the gate of the first P-channel transistor. P of
connected to the gate of the channel transistor, GND connected to the gate of the third P-channel transistor, and connected to the drains of the N-channel transistor and the first and second P-channel transistors, and the third P-channel transistor. the sources of the N-channel transistors are connected in common, the common connection point is connected to a word line, the source of the N-channel transistor and the drain-in of the third P-channel transistor are connected to GND, and the first and second P-channel transistors can be configured by connecting their respective sources to Vcc.

In the memory circuit according to the present invention, the bit line potential holding circuit connects the source of the fourth P-channel transistor to vCC and the drain to the bit line, the gate of which is connected to the address decode signal line for bit line selection. Can be configured.

In the present invention, the word line and Vcc (or GND)
In between, a transistor can be provided which is turned ON (or 0FF) during writing and turned 0FF (or ON) during reading. , The first embodiment of the present invention is shown in FIGS. 3(a), (b), (
C) and FIG. 4 will be explained with a lock.

First, referring to FIG. 3(a), the overall structure of the memory of this embodiment is explained. FIG. 3(a) shows the memory cell matrix section 107 of FIG.
01 and further includes a word line control unit 302. Word line control section 3 shown in FIG. 3(b)
02 is a NAND gate 32 which receives the precharge signal φp and its delayed signal via the delay circuit 31, and the output φX of this NAND gate and the X decoder output Xt.
NAND gate 34 whose input is
P-channel transistor Q, controlled by the output of 34 and the inverted signal via inverter 33 of the 10-X decoder output Xi.

1. Q. 3. N-channel transistor Q. 1. Q
3°, and a voltage output circuit formed by. This circuit 302 serves to lower the potential of the selected word line signal Wl from the Vec potential to a required intermediate potential after the read operation is completed. In order to realize this operation, a word line control signal φX, which is a wave phase delay signal of the precharge clock signal φp, is generated. By the φX,
P-channel transistor Q3゜ for word line drive.

After the read operation is completed, it is switched from ON to OFF.

In this embodiment, it is assumed that the delay time of the delay circuit 31 is set so that the word line control signal φX falls based on the photon time of the read operation estimated in advance. Therefore, after the read operation is completed, the word line signal Wi is transferred to the P-channel transistor Q,. 1. Q. towards the potential determined by the current capacity ratio of 4. Note that for unselected word lines, since the X decoder output Xt is at the GND potential, the P channel transistor Qsor y Qsos is OFF and the N channel transistor Q is turned off, regardless of the timing of φX. , is ON, word line signal Wi is also GN
It becomes D potential. That is, the states of unselected word lines are the same as in the conventional example.

Next, the operation of the memory cell matrix section 301 will be explained with reference to FIG. 3(C). In addition, the operating waveform is the 4th waveform.
This is the passage shown in the figure. FIG. 3(C) shows a circuit in which a bit line potential holding circuit 303 is added to the memory cell matrix section 101 of the conventional example shown in FIG. 1(C). First, the bit line potential holding circuit 303 will be explained. For each bit, the circuit 303 outputs Y data output YJ
P-channel transistor Q3゜6 whose opening and closing are controlled by
．． Q. , /. Therefore, for the selected bit line, since the Y decoder output Yj is at vCC potential, 1
The above P-channel transistor Q. ,,Q3゜,/ turns OFF. That is, the state of the selected bit line is the same as in the first embodiment. On the other hand, for the unselected bit line, since the Y decoder output Yj is at the GND potential, the P channel transistor Q. 3. Q. , ' are turned ON. Here, the relationship with the operation of the selected word line described above will be considered. Immediately, the selected word line signal Wi rises to the Vcc potential, information of the memory cell connected to the selected word line begins to appear on the bit line, and one of the bit line pair BL, BL becomes Vcc.
The voltage starts to decrease slowly from the cc potential. Eventually, BL
, BL is amplified by the sense amplifier 110.

The read data is transmitted to the data output system. At the time when the read data is transmitted to the data output system, that is, when the read is almost completed, the word line control signal φ
When X falls, the word line drive P-channel transistor Qaol turns OFF, and the word line signal W
i is a P-channel transistor Qsoa e Qs. towards the intermediate potential determined by 4.

This intermediate potential ensures that the transfer gate (Qlll) of the memory cell 10'9 selected in the write operation is turned on.
The range for N should be designed to be as low as possible.

For example, the P channel transistor Qs is set so that the intermediate potential 13- becomes approximately 3.
The transistor size of os'v Q1104 is determined.

Transfer gate Q of memory cell 109 connected to one selected word line as shown in FIG. , that is, the above W
Since the potential of i moves toward the intermediate potential, the current capability of Q111 decreases, and the selected 'So' information side bit line (BL or B
Although the speed of the level drop of L) becomes smaller, since the above transfer gate Q, 1m is ON, the above 11.
0 The potential of the information side bit line continues to decrease toward the GND potential.

On the other hand, for the unselected 0" information side bit line, the bit line holding circuit 303 operates, so the bit line potential is approximately Vc
Vcc 4Q3°. →Pit line→
A DC current flows through the path Q1ml+Q11f-+GND. The DC current mainly flows through the transfer gate Q11m.
Determined by current capacity. As mentioned above, since the word line signal Wi, which is the gate signal of Q111, is at the intermediate potential, Q11. The current capacity can be kept small. For example, Vυ=S■andW! = 14- of Sv, the above DC current is about 120 μA per line, while Vcc = 5 V 75h Wi = 3
V (7), the above DC current is about 60μA per one
It is. Therefore.

When this embodiment is applied to a 2×8 bits RAM.

Since the total number of bit lines is 128 columns, the sum of the DC currents flowing through all unselected bit lines is approximately 7.2 mA (0
,06mAX 120), conventional (0,12m
AX120=14.4mA) On the other hand, as mentioned above, the selected ゝゝO'' information side bit line drops almost to the GND potential, and in the next address cycle it drops to Vcc.
Precharged to potential. At this time, a peak appears in the power supply current. What is the value of this peak?

Although it depends on the number of selected bit lines, it is clear that it is much smaller than the conventional example. This is because, in the above conventional example, all the selected and unselected 110 information side bit lines drop to approximately the GND potential, and all of them are precharged to the Vcc potential in the next address cycle. For example, if this embodiment is set to 2 x 8 pins) RAM
When applied to , the peak value is less than or equal to 2 Q mA.・.

In addition, when a write operation is performed in this embodiment, the potential after writing at the 111" side point of the memory cell 109 is (Wi) potential) - (VTN), S'0" after writing the side point. The potential is GND potential, and the word line signal Wi
Writing can be performed satisfactorily as long as the potential is not too low. However, VTN is the threshold voltage of an N-channel transistor. In particular, in this embodiment, the memory cell 109 has 0 MO
8 configuration, the potential of the 1" side point is the memory cell 109.
The P-channel transistor Q1□ is pulled up to the Vcc potential several seconds after writing. Note that the operating waveforms are as shown in FIG.

As described above, the fifth embodiment realizes a memory circuit in which the power supply peak current is kept sufficiently small while ensuring the operating margin and average power supply current that are almost the same as those of the conventional example.

Next, five other embodiments of the present invention will be described.

In this embodiment, the word line control unit 302 in the first embodiment is replaced with a word line control unit 501 shown in FIG. 5(a), and the memory cell 10 in the first embodiment is
This is a memory circuit in which 9 is replaced with a memory cell 502 shown in FIG. 5(b). The word line control section 501 of this embodiment is a P-channel transistor Q whose gate is connected to the write enable buffer signal section' in the word line control section 302 of the conventional example. 1 is added between the word line and Vcc. Furthermore, the memory cell 502 of this embodiment includes a resistor 501 and an N-channel transistor Qllll + Qt'
NMO8 memory cell terminal consisting of tt.

As mentioned above, in the write operation of the first embodiment, the potential at the 1'' side point of the memory cell 109 is as follows.

From (potential of Wt) - (VTN) immediately after writing,
After several tens of seconds, P channel transistor Q11. The voltage rises to pVcc potential. However, if the memory cell is an NMOS memory cell 502 as in the non-embodiment, the resistor 501 usually has a high resistance of several gigaohms, so it takes several hundreds of seconds for the 1" side point potential to rise to the Vcc potential after writing. It takes a long time of microseconds.In this way, if the potential of the node 17- on the ``'1'' side of the memory cell remains at an intermediate potential for a long time.

There is a high probability that the memory cell information will be destroyed by electrical noise or α-ray particles, making it more likely to cause problems in actual use.

In this embodiment, in order to eliminate this drawback, the middle N1 position of the selected word line at the time of writing is made higher than that at the time of reading. A P-channel transistor Q whose opening/closing is controlled by a write enable buffer signal section' shown in word line control section 150]. In addition, the intermediate potential of the selected word line during writing is higher than that during reading, thereby preventing information destruction in the memory cell 502 after writing.

As described above, the present invention realizes a Q-like memory circuit in which the average and peak values of the operating power supply current are sufficiently reduced by lowering the selected word line potential to an intermediate potential after a read operation photon. be. In each of the above embodiments, a precharge transistor Qllll is provided at the end of the bit line.
Although this is an example in which Q1□ is provided, even if a resistive load is provided at the end of the bit line, it is possible to obtain a memory with sufficiently small average and peak values of power supply current during operation, which satisfies the spirit of the present invention. A circuit can be realized.

Further, each of the above embodiments is an example in which the present invention is applied to a memory circuit having an optical CMO8 configuration or a peripheral circuit CMO8 configuration.
It is also possible to apply the present invention to an 8-hybrid memory circuit or a memory circuit having a bipolar transistor configuration. It goes without saying that various other application examples that satisfy the gist of the present invention are possible.

[Brief explanation of the drawing]

Figure 1 (a), (b), (C), (d), (e
) and (f) are a block diagram, an address input buffer circuit diagram, an input buffer circuit diagram, a clock generation part circuit diagram, a memory cell matrix part circuit diagram, and a memory cell part circuit diagram, respectively, showing a memory according to a conventional example. Figure 2 is the same <signal waveform diagram showing the read/write operation of the conventional example,
3(a), 3(b), and 3(c) respectively show a program diagram, a partial circuit diagram, a memory cell matrix, and a box part circuit diagram, respectively, showing the first embodiment of the present invention. Signal waveform diagram showing the read @ write operation of the first embodiment of the invention, No. 5
Figures (a) and (b) are a partial circuit diagram and a memory cell circuit diagram, respectively, showing a second embodiment of the present invention. 101.102...Incoming Huffa, 103...
... Clock generation section, 104 ... X address decoder, 105 ... Y address decoder,
106...DIN control section, 107...
Memory cell matrix section. 108...Dour control L 1.09...
...Memory cell, 110...Sense amplifier. 301...Memory cell matrix section, 302
. . . Word line control section, 303 . . . Bit line potential holding circuit. 501... Word line control section, 502...
・Memory cell.斤゛-daΔ力本へ＜C) F, y Figure tf) Atsushi / Drawing

Claims (4)

[Claims] (1) A word line control circuit having a function of setting the potential of the selected word line to a predetermined value lower than the selected voltage after completion of a read operation. 1. A memory circuit comprising: a bit line potential holding circuit that holds the potential of an unselected bit line at a second value sufficiently close to the value at the time of reset snoring of the bit line. (2) The word line control circuit outputs the output of the inverter circuit which receives the word line selection address decode signal as input.
The output of the two-man NAND circuit is inputted to the gate of the channel transistor, and receives the clock signal that is at a high level for a certain period of time caused by changes in the address input signal, and the address decode signal for word line selection. One P-channel transistor is applied to the gate of the inverter circuit, and the output of the inverter circuit is applied to the second P-channel transistor.
a third P-channel transistor, and connects the gate of the third P-channel transistor to the reference voltage; 2. The memory circuit according to claim 1, wherein the sources of the channel transistors are commonly connected, and the common connection point is connected to a word line to form the N-channel transistor. (3) The bit line potential holding circuit is configured by connecting the source of the fourth P-channel transistor to the power supply and voltage, and connecting the drain to the bit line, the gate of which is connected to the address decode signal line for bit line selection. A memory circuit according to claim (1) or (2), characterized in that: (4) Between the word line and the power supply, turn ON during writing.
(or 0FF) and OFF' (or O when reading).
The memory circuit according to claim (1), (2), or (3), characterized in that a transistor is provided.