JPS60149100A - Frame length varying voice synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field J] The present invention relates to a frame length variable speech synthesis device that is capable of changing the frame length of speech to be synthesized, and relates to a speech synthesis device that is capable of changing the frame length of speech to be synthesized, and is suitable for use in audio alarm clocks, audio alarm devices, and audio alarms. It is used for applications such as being incorporated into various electrical appliances such as devices and pine-surge chairs to output voice messages.

[Background technology]

Conventionally, the audio signal is processed using a sampler pulse with a frequency higher than the audio frequency. Feature parameters are extracted, consisting of a pitch parameter (hereinafter abbreviated as P parameter) representing the period, and a spectral parameter (hereinafter abbreviated as parameter) representing the timbre of the sound, that is, spectral distribution, and each feature parameter contributes to the sound quality. The compression parameters are compressed to the number of pits according to the degree of compression and stored in the data storage unit as compression parameters, and the compression parameters sequentially read from the data storage unit access the playback ROM in which each feature parameter has been stored in advance. A speech synthesis device has been developed that reproduces speech by driving a sound source using feature parameters read from the above.By the way, each of these parameters A, P, and K represents the characteristics of the speech. Therefore, they are collectively called feature parameters, but normally audio signals are 10fn- to 3Qm
Since the signal can be regarded as a substantially stationary signal for a short period of time, this period is regarded as one frame, and one set of feature parameters is extracted from one frame, and the data is updated every frame. However, if the frame is not updated when the voice to be synthesized switches between voiced and unvoiced sounds, for example,
There is a problem in that the duration of voiced sounds or the duration of unvoiced sounds is too long or too short, resulting in a decrease in the clarity of the reproduced sound. On the other hand, when the same scale or tone is repeatedly output over a relatively long period of time, such as a melody, updating the frame frequently like when synthesizing speech will cause the playback melody to change. There was a problem in that there was a lack of customers for the media to store the sound data.

Therefore, the present inventor has conventionally filed a patent application filed in 1983. As shown in the patent application No. 127921, by making the frame length variable, it is possible to clearly separate unvoiced sounds and voiced sounds to obtain beautiful reproduced sounds, and when synthesizing melody sounds, A method for storing playback data by increasing the frame length
We have developed a speech synthesizer with variable frame length that can save capacity. However, in such a conventional example, the frame length data added to the beginning of each frame's worth of characteristic parameters that are sequentially input to the serial data input terminal of the speech synthesis LSI is stored inside the speech synthesis LSI. The frame length is made variable by detecting it with a frame detection circuit, and it is not necessarily easy to use as a method for providing frame length data.

[Purpose of the invention]

The present invention was made in view of the momme point as mentioned above,
The object of the present invention is to provide a frame length variable speech synthesis apparatus which is provided with a frame length data input terminal for supplying frame length data, thereby making it easy to supply frame length data.

[Disclosure of the invention]

(Structure) As shown in the "J lock diagram" shown in FIG. In a speech synthesis device having an audio reproduction means (1) that receives each characteristic parameter in a spectrum for each frame and reproduces audio from the characteristic parameter, one frame is divided into a plurality of interpolation intervals, and the characteristics of the current frame are Interpolation is performed by calculating a value obtained by dividing the difference component (a-Cn-1) between parameter a and feature parameter Cn-1 in the previous interpolation interval by the number of interpolations N in one frame, and multiplying this division value by an appropriate integer. An interpolation calculation circuit (2) that calculates the interpolated value cn of the feature parameter for each interpolation section by adding the component to the value of the feature parameter Cn-1 in the previous interpolation section; A timing control circuit (3) that makes the frame length variable by changing the interpolation circuit (N) and the size of the interpolation component in the calculation circuit (2);
) is provided with a frame length data input terminal (4) for inputting frame length data to be given to the terminal. In the first program diagram, the interpolation calculation circuit (2) is 1
Each feature parameter A, P, and frame for each frame is received as the feature parameter a of the current frame, and a difference component (act-t) from the feature parameter Cn-m of the previous frame, which is stored and held separately, is calculated. This difference component (a-C1
-t) is divided by the number of interpolation ports N given by the tie three-seater control circuit (3), and multiplied by an appropriate integer value to become the interpolation component H. As will be explained in detail later, the value of this interpolation component H is the value obtained by dividing the difference component (a, cl-1) by the number of interpolations N at the initial interpolation stage within one frame. However, in the interpolation stage from the latter half to the end within one frame, the value obtained by the above division is doubled or quadrupled and used. This interpolation component H is added to the feature parameter Cn-x of the previous interpolation section to form an interpolation value Cn, which is input to the audio reproduction means (1). The audio reproducing means (1) reproduces audio based on the interpolated feature parameters ASP and K output from the interpolation calculation circuit (2).

(Embodiment) FIG. 2 is a block diagram showing the overall configuration of a frame length variable speech synthesis device according to an embodiment of the present invention. Audio feature parameters are usually 10fnI81+ to 30m5ec
The link register (7) is connected from the data input terminal (5) via the switching circuit (6) at every data update interval (1 frame).
) is input in series. Link register (7
) represents the feature parameters of the voice, but it is not the feature parameters themselves;
Playback ROM (3
)'s address code is Chiru.

Moreover, the address code is suitable for indicating a relative address in the ROM (8) for use. Therefore, in order to generate the English characteristic parameters 11J- from the read data, the first address stored in the index ROM (9) is extracted by the function of the address counter 04, and this first address is sent from the reproduction control circuit 0]). The absolute address is created by adding it to the relative address retrieved from the / register (7), and the playback ROM (8) is created using this absolute address.
) and retrieve the voice characteristic parameters stored in the playback ROM (8). The number 0 in the figure is the addition circuit for calculating the absolute attrition mentioned above, and θ■
(14) Q is the cost of converting serial data to parallel data. The feature parameters output from the playback ROM (8) are input to the interpolation calculation circuit (2) and
Data is typically interpolated 8 times within a frame to ensure that the audio output changes as smoothly as possible. In other words, if the feature parameters change discontinuously at the connection points between each frame when updating data, distortion will occur in the audio signal and the clarity will likely decrease. Usually, one frame is divided into eight equal parts so that the image size varies, and approximately linear interpolation is performed for each section. The P latch is used to latch the pitch parameter (P parameter) related to the fundamental period of the voice, and the same <07) temporarily latches the amplitude parameter related to the amplitude (A parameter) and the parameter related to the spectral distribution (K parameter). This is an AK latch that should be kept latched. AK latch 0
The data in η is a digital filter (18) for speech synthesis.
is transferred to and stored in the AK parameter stack 01 connected to the AK parameter stack 01 connected to the (B) is a voiced sound source that outputs a pulse train with a period determined by the P parameter, and the waveform for the I pulse output from the voiced sound 1ll) is stored in the sound source ROM &]), and is stored in the address counter (I). ) is sequentially incremented, 11i source ROM c! The data in fi is generated in the order of addresses to reproduce the waveform of one pulse. When the data content of the address counter (c) becomes larger than a predetermined value, data is no longer output from the sound source ROM ejυ, and when the value of the address counter (a) matches the value of P latch 0Q, the data is output to the matching circuit). V
The address value 5J (a) is reset by R and is incremented again.

Therefore, a pulse train is reproduced from the sound source ROMEη at a period according to the P parameter. (C) is a silent sound source composed of a self-ejecting sound generator. (to surface sound source)
(c) is connected to the voice synthesis digital filter 08) via a switching circuit (a) controlled by the sound source control circuit (c). The output of the digital filter 08) is converted into an analog signal by the DA converter (5), and the output of the amplifier (
C) is amplified by Sujiichiriki c! This is reproduced as an audio output by a. ζda) is an oscillation circuit containing a crystal resonator. The output of this oscillator circuit (→) is input to the timing control circuit (3) and becomes a signal for synchronizing the D, P, and O clocks, etc., and is sent to each part in the circuit to control the entire circuit. In the circuit shown in Figure 1, the parts other than the amplifier, Sujichirikikan, and Cositroler (N) are composed of a 1-chip LSI, and are used as the voice synthesis IC described above. It is used with controllers.

The speech synthesis apparatus of this embodiment uses partial autocorrelation '1ll (so-called PARCOR coefficient) as a parameter representing the spectral distribution of speech, and is called a PARCOR type speech synthesis apparatus.

In such a PARCOR type speech synthesizer, the third
As shown in the figure, the audio signal 5 is sampled at appropriate intervals by the sample link pulse.

PA that excludes the correlation due to (p-1) sampler values between the linked linprinter values Xi and Xj-1) and extracts only the correlation between Xi and Xj-p.
Speech is synthesized using the RCOR coefficient as a parameter representing the spectral distribution, and the K parameter is used for one frame (5 to 20 ffl-
), the period t.

(approximately 100 μl 1 ec), the sampler of audio No. 18 Vs is performed, and the correlation coefficient of adjacent sampler values ffj+ is set to 1, and between sampler values separated by multiple intervals, the influence of the sampled values sandwiched between them is Minimum of 2
It is determined by linear prediction using multiplicative errors, and the correlation coefficient obtained by subtracting them is set to 2 to 1. The parameters for this are: , K2. Coefficients expressing partial autocorrelation with points close to Xt, such as K, , contain a wealth of information regarding the spectral distribution, but K@,
Since the partial autocorrelation coefficients with points far from However, by allocating a small number of quantization pits to the parameters, the number of pits is reduced and redundancy is reduced. Each A, PSK
The parameters are compressed and stored, with 5 pits for the A parameter, 6 pits for the P parameter, and 7 pits for each coefficient of the K parameter.
．． A frame length data input terminal (4) is provided in the timing control circuit (3) in the circuit of FIG. ing. This frame length data input terminal (4) inputs data regarding the frame length to the timing control circuit (2), and controls the method of interpolation calculation in the interpolation calculation circuit (2). The frame length data input terminal (4) is
Consists of 4 humans, 25fnsec, 20fn-115
--112,5f7=-110-i-17,5m-15
m5ec, and 2.5rnsl! It is possible to input a total of six different frame lengths. When the frame length is 2 omsees, the timing control circuit (3) sends a control signal to the interpolation calculation circuit (2) to perform eight interpolations. Also, the frame length is 25fnse
C1+5fnsee, 12.51--110- decrease, 7.
In the case of 5rn formula and 5m formula, the interpolation calculation circuit (2) performs 10-point interpolation, 6 interpolation intervals, 5 interpolation intervals, and 4 interpolation intervals, respectively.
Interpolation, 3-interpolation, and 2-interpolation are performed, and when the frame length is 2.5f11sL1c, a control signal is sent so as not to perform interpolation.
Taking as an example the case where the number of interpolations is 8 times in one frame in Qm-, the following error occurs: Data is read into the J credit register (7) by interpolating one frame into 8q parts as shown in Figure 3. This is carried out in the first interpolation section (1) of the sections D2, . . ., D6.

Each section D1 to D8 is divided into 25'i'): P
, ” P, is divided into 5 parts v1. A, P, K, o
, K, . . . , 1 are arranged in series in odd-numbered Pl, P:+, P5 . . . , P2, and 1Pz5 is a spare row. Even-numbered P2. P, , P6...
, P2. is the timing for performing interpolation calculations.

Furthermore, each region of KP and ~p2s is divided into 22 equal parts T, ,
T, ..., T22. Of these, T, ~T
, is a control signal section for storing control signals, and the actual data is read and skipped after ] 6. For example, in the case of A parameter, the data is 5 hits, so T6~
Data is read into T1o, and in the case of the P parameter, data is 6 pits, so data is read into T6me JT, , etc. However, the interpolation interval is
, the data input terminal (5) is connected to the link register (
7), and in the interpolation period D2 to D, this data is cyclically circulated in the link register (7) via the switching circuit (6), and therefore is used for address calculation. The same data A, P, K, o, K are always sent to the addition circuit FQ'2) over the entire interpolation period of one frame.

..., K2. It is possible to repeatedly transmit the data in the order of K. Therefore, the interpolation calculation circuit (2) receives the same theta eight times in the same order over the interpolation interval from D1 to Ds.

The principles described above greatly facilitate interpolation calculations. In other words, if the interpolation calculation circuit (2) repeatedly receives the data 8 times, let a be the data, let the data from one frame before be b, and let the interpolated values be C, C2...+CS, then the following equation is obtained. Therefore, linear interpolation can be performed approximately approximately.

D,,C,=b D3 + C3-C7+(a C2) X sD, c
, = c, + (a-c3) x soil D5i Cs = Ch + (a C4) ×-D6i
Ca "Cs 10 (a C5) X-Dt i Cy
= Ca + (a C6) X-I)1; Cs
2C7+(aCy)×-As described above, in any case, as long as the data in the previous interpolation interval is stored using the P latch 0Y and the AK parameter stack 0, the data that is repeatedly sent out can be stored. It is possible to always perform interpolation calculations together with a.

Similarly, when performing 4-point interpolation with a frame length of, for example, IOm-, and when performing 2-point interpolation with a frame length of 5 m (8), linear interpolation can be approximately performed using the following formulas. For the four-point interpolation, HC,=b Dt i C2'' C+ + (a C1) X-D3
i C3” C2+(a C2) X-D, , C,
= C+++ (a-ci) X - jL sum of two-point interpolation D+; Interpolation interval Dn
The unit length of 2.5f7+- remains unchanged, but by changing the data input to the timing control circuit (3) via the frame length input terminal (4), the number of repetitions of interpolation calculation and the number of interpolation calculations can be changed. The calculation method for the frame length can be changed from a maximum of 25m to a minimum of 2.5m.
5fFl l! It can be changed with ec- and +.

5 to 7 are diagrams showing how frame length data is input to the timing control circuit (3). First, the fifth
In the example shown in the figure, C at Kotsuto 0-La (A)
The PU port output is directly input to the frame length data input terminal (4). Here, the frame length data input terminal (4) has four terminals Iin, 0. FL
I, F I-, ), FL3, and the terminal FLOSFL
I is a two-hit signal FRLI that determines the frame length;
The terminal FL2 corresponds to the signal NRM which determines which child's data is used to change the frame length, and the terminal FL3 corresponds to the signal FS for setting the frame length in the same way as the terminals FLQ and FLI. Compatible. Signals FRLI and FRL2 are 00110,01, l I
oSoresohka 20f71sec, lOfn-15ms
It corresponds to each frame length of ec, 2.5--. When the signal NRM is 1, the above four types of frame length determined by the signals FRLI and FRL are selected, and when it is 0, the other four types of frame length determined by the signal FS and the signal 9FRLI are selected. Ru. That is, when the signal FS is 1,
If the signal FRLI is 0, the frame length is +5 fnsec, if it is I, the frame length is 7.5 m-, and when the signal FS is 0, the signal FRL is 0. This is the length of each frame.

In the embodiment shown in FIG. 6, the signal on the data bus of the CPU in the controller (A) is once input to the latch circuit (a+l) via the frame length data input terminal (4),
A signal is input from this latch circuit (3) to the timing control circuit (3).In the present embodiment, the frame length data input terminal (4) and ties 3 and 7 are connected to each other. Since the latch circuit C31) is provided between the control circuit (3), frame length data can be held in the latch circuit (31) during one frame period. In the circuit shown in Figure 6, 2 is the input terminal that receives all the latch clocks from the CPU, and is 3 (3" 3).
is an output terminal connected to the interrupt input of CP TJ.

From this output terminal (33), a frame synchronization signal F R
M is output as a data request signal, and 1
At the start of a frame, post-frame data is received from the CPU.

In the embodiment shown in FIG. 7, the frame length data serially sent from the CPU in the controller (A) is transferred via the switching circuit (35) to the shift register (3).
4). (36) is a D flip-flop for detecting repeat E number, P25
・If the data at the frame length data input terminal (4) is 1 at the timing of the signal FRCK that comes from the T5 clock, the output of Flora-Z-Flora-zu (36) will be 1,
The switching circuit 0[i] is switched to connect the serial output O of the shift register (34) to the serial input I, so that the frame length data in the MfJ frame is repeatedly used. The parallel output AND of the shift register (34) is the signal FL3
~FLO is input to the tie three control circuit (3). In addition, for shift register 0 (1) manual operation T, Dl"P25"Tll~ToriD")
A signal FSFT equivalent to ') is input. This D.I.
' The timing of P25 is a strong timing since each feature parameter is input to A, P, as described above. Therefore, in this embodiment, the frame length data input terminal (4) is used as the data input terminal (4) of the speech synthesis LSI.
5) can also be used. In this case, the frame length data can be regarded as a type of feature parameter.

Section 8 (a) is a block diagram showing a schematic configuration of a frame counter portion in the tie control circuit (3). As shown in the figure, the frame counter consists of four flip-flops (3 to (10)) and a logic circuit section (4 to 4).
1), which receives the 4-bit frame length data input from the terminal FLONFL3 and the signal DCT, and outputs the D1 clock that determines the timing of the frame synchronization signal FRM, and the interpolation component H during interpolation calculation. It outputs signals IPL8, IPL4, and IPL2 that determine the magnitude of. Each flip flora"j (37) ~ (
The signal DCT serving as the data input clock of 2.
It is input every 5-- and each flip is input every time.
Since the status of H to (40) changes, the output state changes for each turn. Signals IPL8, IPL4, I output from the logic circuit section (41)
One of PL2 becomes 1 when performing interpolation calculation, and when signal IPL8 is 1, the interpolation calculation circuit (2) uses the feature parameter a of the current frame.
and the characteristic parameter 9Cn-1 of the 11J interpolation interval (a-C11) multiplied by l/F; (a-C, 1-x) plus 1/4 is the interpolated component H, and when the signal IPL2 is 1, the difference component (a-CH-H) is multiplied by 1/2. is the interpolated component H.

FIG. 8(b) shows a more specific circuit example of the configuration shown in FIG. 8(a) above, in which the logic circuit section 01
) is a trap that specifically shows how it is constructed. When the logic circuit (41) is configured as shown in the figure, the following operation is realized. If the frame length is 20 m, the characteristic parameters of the previous frame are read as they are at DI and D'j, and at D2 to D and the clock, the signal IPL3 becomes 1 and the above-mentioned difference component (a7cn -u) is multiplied by 1/8, and in l)5 to D7 clocks, the signal IPL4 becomes 1 and the difference component (a-Cn-1) becomes 1/4.
Interpolation calculation is performed using the interpolation component multiplied by
-1) is multiplied by 1/2 to perform interpolation calculations. Next, if the frame length is 25fn-,
Signal IPLg is used for D2-D5 and D-clock, signal I PL4 is used for DPI-D9, and signal I is used for DIo clock.
PL2 each becomes 1. Also, the frame length is 15f
In the case of nSeC, D2. D, signal I in RI0TS
PIJ, r) In the clocks from t to D6, the number a IPL4 becomes 1, and when the frame length is 12.5 myec, the signal IPL4 becomes 1 in the clocks from ■) 2 to D1, and the signal IPL2 in the clock in D5, respectively. 1, and when the frame length is 10f11sec, D2. The signal IPL4 becomes 1 when the D clock is set to 0, and the signal IPL2 becomes 1 when the D4 clock is set. Furthermore, the frame length is 7.5m5ec.
In the case of I)2. D, when the clock signal IPL4 becomes 1 and the frame length is 5 msec, D
The signal IPL, ;) becomes 1 in 2 clocks. Further, when the frame length is 25f71, no interpolation calculation is performed.

FIG. 9 shows the frame length of 2.5--15f'! for the embodiments of FIGS. 5 and 6. 1 rainbow, 7.5--15
--110.12.5nt--, and is a diagram showing changes in the signals 1PL2 and IPL4 and changes in the data of the terminals FLO to FL3 in each case. The data of the terminals FLO to FL3 that determine the frame length are updated at the timing when the frame synchronization signal gFRM rises. First, when setting the frame length to 25m5ec, both signal 9FLQ and FLI are set to 1. In this case, one frame ends only with D1 being zero, and no interpolation calculation is performed. Also, when setting the frame length to 5 m5ec, ・signals FLQ, FL
I is set to 1.0. In this case, one frame ends with the D2 clock, and ■) In the first clock, the data of the 1fI frame remaining in the link register (7) is passed through the interpolation calculation circuit (2) as it is,
When D2 is turned on, IPL2 becomes 1 and (a - C1
-1) Perform interpolation calculation using Xl/2 as an interpolation component. Further, when the frame length is set to 7.5fn-, each of the signals FLQ to FL3 is set to 0.1.011.

In this case, one frame ends with D3RI0TSU and D
In luri0tsuk, we use the data of Moe frame,
When D2, D, and R0 are set, the signal IPL4 becomes 1, and (
a'n-1) Perform interpolation calculation using Xl/4 as an interpolation component. Further, when setting the frame length to 10%, the signal FLONFL2 is set to 0.1.1, respectively, and when the frame length is set to 12.5911-%, the signal FLONFL3 is set to 0.1, respectively. .0.0
It is set as follows. In the case of FIJ users, one frame ends with D4 or Otsu, and with D190, the data of the 0 [■ frame is used as is, and with D2, D, and clock, IPL4 becomes 1, D, and with clock, IPL2 becomes 1. (a Cn −1) X l/4 and (
Interpolation calculation is performed using a Cn-1,)Xl/2 as an interpolation component. In the latter case, the frame length is 10tna
Interpolation calculations are performed so that the period during which the signal I P L is 4 or 1 is longer by one D clock than in the former case of ac.

FIGS. 10(a) and 10(b) show changes in each signal in the case of the embodiment in FIG. 7. Figure 10 (a)
) is the case of a repeat signal, and the output FRFF-Q of the D flip-flop (3ri) for detecting a repeat signal is set to O at the timing of the signal FRCK.

In FIG. 10(a), REQ is a request signal, which is a signal prompting the controller (A) to send one pit of a repeat signal and four hits of frame length data. When this request signal is issued, the controller (N) requests that the repeat signal and frame length data be sent as serial data DATA. Among these, the repeat signal is latched to the D flip-flop (3G), and the frame length data is sent as the serial data DATA. It is inputted from input FLSR-1 of shift register G34) with FSFT set to 0, and outputted from parallel output AND as data at terminals FL3 to FLQ. This figure 10 (a
), one frame is 7.5m5ec,
Data 5 of signals FL3 to FLO t'tL I
, 0, 1.0. Next, Fig. 10(b) shows the case with beam repeat, in which the request signal is sent once, data 1 sent at this point is latched into the D flip flop (3 (branch)), and its output FRFF-Q is 1
Then, the request E signal for the next 4 pits will not be sent, and the frame length data of the previous frame will be used for that cut.
will be done. In the case of FIG. 10(b), the frame length of the previous frame is 12.5%, and the signals FL3 to
The FLO data is 0, 0.1.0, respectively.

〔Effect of the invention〕

The present invention is configured as described above, where one frame is a small period in which an audio signal can be considered as an almost stationary aid, and the characteristic parameters of amplitude, fundamental period, and spectrum extracted from each frame are measured for each frame. In a speech synthesis device that reproduces speech from the feature parameters received in the current frame, one frame is divided into a plurality of interpolation sections, and the difference between the feature parameters of the current frame and the feature parameters of the previous interpolation section is calculated. Calculate the value obtained by dividing the component by the number of interpolation points in one frame, and add the interpolation component obtained by multiplying this division value by an appropriate integer to the value of the feature parameter in the previous interpolation interval to calculate the interpolation value of the feature parameter for each interpolation interval. , a timing control circuit that keeps the length of the unit interpolation interval unchanged and varies the frame length by changing the number of interpolation points and the size of the interpolation component in the interpolation calculation circuit, and a tie-three jig control circuit. Since it is equipped with a frame L for inputting frame length data to be given to the input terminal and a length data input terminal, the length of one frame during speech synthesis can be made an integral multiple of the length of the unit interpolation interval in the interpolation calculation circuit. Therefore, it is possible to obtain natural reproduced sound by, for example, making the division between a voiced sound section and an unvoiced sound section clear. In particular, in the present invention, the timing control circuit is Since a frame length data input terminal is provided for inputting frame length data, the frame length data is added to the beginning of each feature parameter for one frame that is sequentially input to the serial data input terminal as in the conventional example. This has the advantage that it is much easier to provide frame length data than detecting the frame length using a frame length detection circuit.

[Brief explanation of the drawing]

FIG. 1 is a so-called claim-compatible diagram showing the structure described in the claims of the present invention, and FIG. 2 is a block diagram showing the overall structure of a speech synthesis binding surface according to an embodiment of the present invention. Figure 3 shows the PARCOR used in this example.
FIG. 4 is an explanatory diagram of the same operation as above. FIGS. 5 to 7 are block diagrams of different embodiments of the present invention. Block diagram of frame length data used in the example, FIG.
) is the detailed circuit diagram of the same as above, and Figure 9 is the same as Figure 5 and Figure 6'+! : An explanatory diagram of the operation of the embodiment, FIG. 10 is an explanatory diagram of the operation of the embodiment shown in FIG. (1) is an audio reproduction means, (2) is a t111 calculation amount calculation (3) is a timing control circuit, and (4) is a frame length data input terminal. Representative Uto Patent Attorney Ishi HJ Cho Nanakari N3 Figure 1000 Figure 4 Figure 1-1□-□□□□□-1 To (20 msec) Figure 5 Figure 6 DI, Pl, Tl B

Claims (1)

[Claims] (1) One frame is a minute period in which the audio signal can be considered to be in a steady state, and the characteristic parameters of amplitude, fundamental period, and spectrum extracted from each frame are received for each frame, and the audio is extracted from the characteristic parameters. In a speech synthesis device that performs regeneration, an l frame is divided into a plurality of interpolation sections, and the difference component between the feature parameters of the current frame and the feature parameters of the previous interpolation section is calculated by 1.
Calculate the value divided by the number of times of interpolation in the frame, and add the interpolation component obtained by multiplying this division value by an appropriate integer to the value of the feature parameter in the previous interpolation interval to calculate the equivalent value of the feature parameter for each interpolation interval. an interpolation calculation circuit,
A timing control circuit that keeps the length of the unit interpolation interval constant and changes the frame length by changing the number of interpolations and the size of the interpolation component in the interpolation calculation circuit, and a timing control circuit that inputs frame length data to be given to the timing control circuit. 1. A speech synthesis device comprising a frame length data input terminal.