JPS60148229A - Analog-digital converting circuit - Google Patents
Analog-digital converting circuitInfo
- Publication number
- JPS60148229A JPS60148229A JP521384A JP521384A JPS60148229A JP S60148229 A JPS60148229 A JP S60148229A JP 521384 A JP521384 A JP 521384A JP 521384 A JP521384 A JP 521384A JP S60148229 A JPS60148229 A JP S60148229A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- analog
- voltage
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/52—Input signal integrated with linear return to datum
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はアナログ入力信号をデジタル信号に変換する
アナログデジタル変換回路、特に二重積分回路を使用し
た二重積分型アナログデジタル変換回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an analog-to-digital conversion circuit for converting an analog input signal to a digital signal, and particularly to a double-integration type analog-to-digital conversion circuit using a double-integration circuit.
従来この種の装置として第1図に示すものがあった。図
において、(l)は共通端子(2)との間にアナログ信
号入力電圧Aが印加される入力端子、(3)は共通端子
(2)との間に入力電圧Aとは逆極性の所定の一定電圧
Bが印加される端子、(4)は端子11+(31を切り
換えるアナログスイッチ、(5)は演算増幅器で構成さ
れる積分器、(6)は積分器(5)の出力電圧Cが所定
電圧レベルDに達することを検出する比較器で、これら
入力端子(1)+2)+31 、アナログスイッチ(4
)l・積分a(5)及び比較器(6)とで、二重積分回
路(7)を構成している。(8)は比較器(6)からの
出力電圧Eのパルス幅をクロックパルスによって計数す
る計数回路、191QIはデジタル信号F出力端子であ
る。第2図は積分器(5)、比較器(6)の出力電圧C
及びEを示す波形図で、T1は第1図のアナログスイッ
チ(4)が端子(1)側に切換えられているアナログ信
号計測期間、T2はアナログスイッチ(4)が端子(3
)側に切換えられているパルス変換期間” alはアナ
ログ入力信号が低い電圧A、の時のアナログ信号計測期
fitl T。A conventional device of this type is shown in FIG. In the figure, (l) is an input terminal to which analog signal input voltage A is applied between common terminal (2), and (3) is a predetermined input terminal with opposite polarity to input voltage A between common terminal (2). (4) is an analog switch that switches terminals 11+(31), (5) is an integrator consisting of an operational amplifier, and (6) is a terminal to which a constant voltage B of integrator (5) is applied. A comparator detects when a predetermined voltage level D is reached, and these input terminals (1) + 2) + 31 and analog switch (4)
)l/integrator a (5) and the comparator (6) constitute a double integration circuit (7). (8) is a counting circuit that counts the pulse width of the output voltage E from the comparator (6) using clock pulses, and 191QI is a digital signal F output terminal. Figure 2 shows the output voltage C of the integrator (5) and comparator (6).
and E, T1 is an analog signal measurement period when the analog switch (4) in FIG. 1 is switched to the terminal (1) side, and T2 is a period when the analog switch (4) is switched to the terminal (3)
) side is the pulse conversion period "al" is the analog signal measurement period fitl T when the analog input signal is at a low voltage A.
における演算増幅器(5)の出力電圧Cの変化を、C1
1は同じ電圧札に対するパルス変換期間T2における電
圧Cの変化e r Ca2はアナログ入力信号が高(、
N電圧A2の時の期間T、における電圧Cの変化’e
e Cb2は電圧A2に対する期間T2における電圧C
の変化をそれぞれ示し、E、は入力信号A、に対する比
較器(6)の出力電圧Ek # E2はA2に対す惠電
圧Eを示している。The change in the output voltage C of the operational amplifier (5) at C1
1 is the change in voltage C during the pulse conversion period T2 for the same voltage tag e r Ca2 is the analog input signal being high (,
Change in voltage C during period T when N voltage A2 'e
e Cb2 is the voltage C in period T2 with respect to voltage A2
E represents the output voltage Ek of the comparator (6) with respect to the input signal A, and E2 represents the voltage E with respect to A2.
次にその動作を説明する。アナログスイッチ(4)の端
子[11側の接点が閉成されると、アナログ信号入力電
圧Aが、スイッチ(4)ヲ介して積分器(5)に入力さ
れる。入力された電圧Aは、第2図のアナログ信号計測
期間T1の間、即ちアナログスイッチ(4)が端子(1
)側に接している間、アナログ入力電圧Aの大きさに比
例した傾斜で下降していく。例えば入力電圧が低いA、
の時はCa1のように、高い電圧A2の時はCa2のよ
うに下降し、T、の終了時には積分器(5)の出力電圧
Cは入力電圧Aに比例した大きさの電圧だけ、電圧レベ
ルDより低下する。次にアナログスイッチ(4)は端子
(3)側に切り換えられ。Next, its operation will be explained. When the contact on the terminal [11 side] of the analog switch (4) is closed, the analog signal input voltage A is input to the integrator (5) via the switch (4). The input voltage A is applied during the analog signal measurement period T1 in FIG.
) side, the voltage decreases at a slope proportional to the magnitude of the analog input voltage A. For example, A with low input voltage,
When the voltage is high, it falls like Ca1, and when the voltage A2 is high, it falls like Ca2, and at the end of T, the output voltage C of the integrator (5) decreases by a voltage proportional to the input voltage A, and the voltage level It is lower than D. Next, the analog switch (4) is switched to the terminal (3) side.
パルス変換期間T2に入り、同時に比較器(6)の動作
を開始させ、正の出力電圧を発生させる。パルス変換期
間T2に入ると、積分器(5)では入力電圧Aとは逆極
性の一定電圧Bが積分され、その出力電圧Cは:入力電
圧がA1の場合も、A2の場合も同じ傾斜でCbl”
b2のように上昇する。この積分器出力電圧C(Cbl
、Cb2)が所定の電圧レベルD1例えばOvに達する
と、比較器(6)はこれを極出し、その出力を0とする
。即ち比較器(6)からは2期間T2における積分時間
に比例したパルス幅W (Wl、W2)ノハルス電圧E
(g E)が得られる。このパルス12
1@Wはアナログ信号入力電圧Aの大きさに比例するこ
とになる。このパルス幅Wを、計数回路(8)において
クロックパルスによって計数し、それをデジタル出力信
号Fとして出力端子+9+ filに出力する。Entering the pulse conversion period T2, the comparator (6) starts operating at the same time to generate a positive output voltage. When entering the pulse conversion period T2, the integrator (5) integrates a constant voltage B with the opposite polarity to the input voltage A, and the output voltage C has the same slope whether the input voltage is A1 or A2. Cbl”
It rises like b2. This integrator output voltage C (Cbl
, Cb2) reaches a predetermined voltage level D1, for example Ov, the comparator (6) polarizes it and makes its output zero. That is, from the comparator (6), the pulse width W (Wl, W2) Nohals voltage E is proportional to the integration time in the two period T2.
(gE) is obtained. This pulse 121@W will be proportional to the magnitude of the analog signal input voltage A. This pulse width W is counted by a clock pulse in a counting circuit (8) and outputted as a digital output signal F to an output terminal +9+ fil.
従来の二重積分型のアナログデジタル変換回路は以上の
ように構成されているので、アナログ信号入力電圧に過
大な電圧や電流が入力した時1回路が破壊され、デジタ
ル出力回路を含む全体の回路に影響を及ぼすという可能
性があり、これを防ぐために絶縁回路を付加する必要が
あり装置全体が高価となる欠点を有していた。Conventional double-integration type analog-to-digital conversion circuits are configured as described above, so when an excessive voltage or current is input to the analog signal input voltage, one circuit is destroyed and the entire circuit including the digital output circuit is destroyed. In order to prevent this, it is necessary to add an insulating circuit, which has the disadvantage that the entire device becomes expensive.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、二重積分回路の出力回路と計数回
路の入力回路とをフォトカプラによって結合させること
によって、安価に絶縁ヲ行なったアナログデジタル変換
回路を提供することを目的としている。This invention was made to eliminate the above-mentioned drawbacks of the conventional circuit, and by coupling the output circuit of the double integration circuit and the input circuit of the counting circuit with a photocoupler, insulation was achieved at low cost. The purpose is to provide analog-to-digital conversion circuits.
以下、この発明の一実施例を図について説明する。第3
図において、(l)ないし0Iは、第1図の同一符号と
同一部分を示し、aカは発光ダイオードf13及びフォ
トトランジスタ+131からなるフォトカプラである。An embodiment of the present invention will be described below with reference to the drawings. Third
In the figure, (l) to 0I indicate the same parts as the same reference numerals in FIG.
即ち構成において、第1図とは、比較器(6)の出力回
路かフォト力1うαυを介して計数回路(8)の入力回
路に結合している点が異なるのみである。従って正常動
作においては、第1図と何等異ならないが、二重積分回
路(7)のアナログ回路と。That is, the configuration differs from that in FIG. 1 only in that the output circuit of the comparator (6) is coupled to the input circuit of the counting circuit (8) via the photopower 1 or αυ. Therefore, in normal operation, it is no different from that in FIG. 1, but with the analog circuit of the double integration circuit (7).
計数回路(8)以下のデジタル回路がフォトカプラaη
によって光絶縁されているので、アナログ回路側に生じ
た異常電圧によってデジタル側に影響を受けることは全
くない。又過大な入力電圧によってアナログ回路が破壊
されたとしても、それがデジタル側に波及されることも
なく、全体回路に及ぼす影響が抑えられる。The digital circuit below the counting circuit (8) is a photocoupler aη
Since it is optically insulated by , the digital side is not affected by any abnormal voltage generated on the analog circuit side. Furthermore, even if the analog circuit is destroyed due to excessive input voltage, the damage will not be transmitted to the digital side, and the influence on the entire circuit can be suppressed.
〔発明の効果〕
以上のように、この発明によれば単にフォトカプラを追
加するのみでアナログ側とデジタル側の光絶縁を行なっ
ているので、安価で簡単な構成にて、過大な入力電圧に
よって高価々デジタル回路の破損を防止できる効果を有
している。[Effects of the Invention] As described above, according to the present invention, optical isolation between the analog side and the digital side is achieved by simply adding a photocoupler, so it is possible to achieve optical isolation between the analog side and the digital side by simply adding a photocoupler. This has the effect of preventing expensive damage to digital circuits.
第1図は、従来の二重積分型アナログデジタル便換回路
金示す回路図、第2図はそれの動作説明図、紀3図はこ
の発明の一実施例を示す回路図である6
図において11+ +21はアナログ入力信号入力端子
。
+31 +21は一定電圧印加端子、(4)はアナログ
スイッチ。
(5)は積分器、(6)は比較器、(7)は(1)〜(
6)で構成され′ る二重積分回路、(8)は計数回路
、+9+fIQはデジタル出力端子、 fillはフォ
トカブラ、0りはそれの発覚ダイオード、Hはフォトト
ランジスタである。
図中同一符号は同−或いは相当部分を示す。
代理人 大 岩 増 雄(ほか2名)
第2図
第3図Fig. 1 is a circuit diagram showing a conventional double integral type analog-to-digital exchange circuit, Fig. 2 is an explanatory diagram of its operation, and Fig. 3 is a circuit diagram showing an embodiment of the present invention. 11+ +21 is an analog input signal input terminal. +31 +21 is a constant voltage application terminal, (4) is an analog switch. (5) is an integrator, (6) is a comparator, and (7) is (1) to (
6) is a double integrating circuit, (8) is a counting circuit, +9+fIQ is a digital output terminal, fill is a photocoupler, 0 is its detection diode, and H is a phototransistor. The same reference numerals in the drawings indicate the same or corresponding parts. Agent Masuo Oiwa (and 2 others) Figure 2 Figure 3
Claims (1)
入力信号とは逆極性の一定電圧を、積分電圧が所定レベ
ルに達する迄積分し、上記アナログ入力信号の大きさに
比例したパルス幅の出力信号を得る二重積分回路と、こ
の回路からの出力信号のパルス幅を計数する計数回路と
を有するアナログデジタル変換回路において、上記二重
積分回路の出力回路と上記計数回路の入力回路とをフォ
トカプラによって結合したことを特徴とするアナログデ
ジタル変換回路。After integrating the analog input signal for a predetermined time, a constant voltage of opposite polarity to this analog input signal is integrated until the integrated voltage reaches a predetermined level, and an output signal with a pulse width proportional to the magnitude of the analog input signal is generated. In an analog-to-digital converter circuit having a double integrating circuit to obtain a pulse width, and a counting circuit to count the pulse width of an output signal from this circuit, the output circuit of the double integrating circuit and the input circuit of the counting circuit are connected by a photocoupler. An analog-to-digital conversion circuit characterized by a combination of
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP521384A JPS60148229A (en) | 1984-01-12 | 1984-01-12 | Analog-digital converting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP521384A JPS60148229A (en) | 1984-01-12 | 1984-01-12 | Analog-digital converting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60148229A true JPS60148229A (en) | 1985-08-05 |
Family
ID=11604911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP521384A Pending JPS60148229A (en) | 1984-01-12 | 1984-01-12 | Analog-digital converting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60148229A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0623329U (en) * | 1992-08-27 | 1994-03-25 | 三菱重工業株式会社 | Isolated A / D conversion circuit |
DE10159607B4 (en) * | 2001-03-09 | 2010-11-18 | Siemens Ag | Analog / digital signal converter device with galvanic isolation in its signal transmission path |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5840941B2 (en) * | 1978-07-10 | 1983-09-08 | ダイセル化学工業株式会社 | Method for producing alkylamines |
-
1984
- 1984-01-12 JP JP521384A patent/JPS60148229A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5840941B2 (en) * | 1978-07-10 | 1983-09-08 | ダイセル化学工業株式会社 | Method for producing alkylamines |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0623329U (en) * | 1992-08-27 | 1994-03-25 | 三菱重工業株式会社 | Isolated A / D conversion circuit |
DE10159607B4 (en) * | 2001-03-09 | 2010-11-18 | Siemens Ag | Analog / digital signal converter device with galvanic isolation in its signal transmission path |
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