JPS60148221A - Output circuit - Google Patents

Abstract

PURPOSE:To prvent a through-current by means of simultaneous drive of output transistors (TRs) by comparing an input signal with a reference voltage different from each other respectively so as to drie push-pull output TRs with a time difference proportional to the voltage difference. CONSTITUTION:A pulse input signal VIN becomes a signal VIN' delayed for the leading and trailing through a time constant circuit 1 and inputted to TRs Q1, Q2 biased with different reference voltages VREF1, VREF2 respectively. The reference voltages have a relation of VREF2>VREF1 and the output push-pull TRs Q2, Q4 are turned off at a point of time with a delay by a period t0 from a point of time t1 when the signal VIN' is decreased from the VREF2. When the signal VIN' is dropped further and reaches a value of the VREF1 or below, the TRQ2 is turned off, the TRQ1 flows a collector current. When the voltage VIN is risen, after the t0 from the point of time t0 of VIN'>VREF1, the TRs Q4, Q2 are turned on at a point of time t4 of VIN'>VREF2, and after the time difference tD from the turning off of the TRQ1, the TRQ2 is turned on and no through-current flows.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a push-pull output circuit, and is particularly suitable for use in supplying drive current to a motor coil.

[Background technology]

A so-called push-pull output circuit is often used in the output stage of audio equipment or the output stage of a motor drive circuit.

Prior to the invention of the present application, the present inventor conducted studies as described below regarding a push-pull output circuit having a circuit configuration as shown in FIG.

That is, the base of the PNP transistor Qs is
The input signal VNII shown in FIG. 2(B) is supplied to the penis of the NPN transistor Q2 by supplying the input signal VNII shown in FIG.
Supply N2. As a result, the collector current of the PNP transistor Qs is as shown in Fig. 2 (C) with respect to the input signal VINI.
As shown in Figure 2, there was a delay in the turn-off time. Also,
The collector current of transistor Q2 is the input signal VIN2.
On the other hand, as shown in FIG. 2(D), there was a delay in the turn-off time. Therefore, during the T's period and the T2 period, the transistors 01. The inventor's studies have revealed that a large current known to those skilled in the art as a through current flows through Q2, and in some cases, the transistors Ql and Q2 are destroyed.

Furthermore, the inventor's studies have revealed that the delay in the turn-off time as described above is caused by the charges accumulated in the bases of the bipolar transistors Ql and Q2.

[Purpose of the invention]

An object of the present invention is to provide a push-pull output circuit that can prevent vertically connected transistors constituting the push-pull output circuit from operating in the on state at the same time. Another object of the present invention is to provide a push-pull output circuit that can reduce the time during which transistors are simultaneously turned on to an extremely short time.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of the invention disclosed in this application is as follows.

That is, input signal VIN' and reference voltage VREFI, V
REF2 and the reference voltages VREFI, VR
Output transistor Q with a time difference proportional to the voltage difference of EF2
This achieves the object of the present invention, which is to drive the output transistors Qt and Qz and prevent the generation of through current due to simultaneous driving of the output transistors Qt+Q2.

[Embodiment 1] A first embodiment of a push-pull output circuit to which the present invention is applied will be described with reference to FIGS. 3 and 4.

An input signal VIN whose level changes in a pulse-like manner as shown in FIG. 4(A) is supplied to the input terminal T. Resistance R*
, Ct constitutes a time constant circuit 1, and the input signal VIN whose fall time and rise time are delayed by the time constant is
'(Figure 4(B)) is obtained.

A bias voltage is supplied to the base of the transistor Q3 by the reference voltage VREFI, and a bias voltage is supplied to the base of the transistor Q4 by the reference voltage VREF2.The voltage levels of the reference voltages VREFI and VREF2 are as shown in FIG. 2(B). As shown in <VREF2>VR
Specified by EFI.

The input signal VIN' gradually decreases to the reference voltage VREF.
There is a delay of approximately 1 μsec from the time t1 when the value has decreased below 2 (
(to period in FIG. 4(D)) and transistor Q2. Q4
is the turn-off. Further, the input signal VIN' gradually decreases and becomes lower than the reference voltage VREFI at the time t2.
, transistor Q31Q1 turns on, and as shown in Fig. 4 (D
) flows through the collector current. Therefore, the time for transistor Q2IQ4 to turn off and transistor Q
The time when 31Q is turned on is the reference electricity V REFI
.

It is determined by the voltage difference of VREF2, and this determination produces a time difference tu as shown in FIG. 4(D).

During this time U, both transistors Ql and Q2 are off, and no through current flows. Then, an output current I out flows through the transistor QI, and an output voltage Vouj is obtained at the terminal T2.

Next, the circuit operation will be described when the voltage level of the input signal VIN rises and the voltage level of the input signal VIN' gradually rises in response.

At time point 13, when VREF1<VIN', transistor Q3. Q1 transitions to turn-off operation, approximately 1μse
It turns off after a delay of about c (to')L/.

Then, when VREF2<VIN', transistor Q4. Q2 is turned on, and a collector current as shown in FIG. 4(D) flows. As a result, transistors Q3-Ql
A one-hour difference 1(,) occurs between the time when Q41Q2 is turned off and the time when transistor Q41Q2 is turned on, and no through current flows.Then, the output current Iout' flows, and the output voltage V
out is obtained.

Therefore, according to the push-pull output circuit shown in the first embodiment, transistor Q1. When Q2 is turned off or turned off, no through current flows, and the transistors Q@ and Q2 are prevented from being destroyed.

Next is the second one. A third example will be explained. In the push-pull output circuit, transistors Q1 and Q2 may be constructed by Darlington circuits. In particular, the Darlington circuit, which corresponds to zero transistors, is a lateral PNP
Transistor and NPN) - Complementary connections may be made using transistors. In this case lateral P
The N-type base layer of an NP transistor is usually formed from an epitaxial layer, and since a large amount of minority carriers exist as accumulated base charges in this base layer, the turn-off time is long. In order to eliminate this drawback, the inventor developed a lateral PNP transistor.

We have developed a push-pull output circuit that connects NPN transistors in a complementary manner and can prevent through current. The complementary connection push-pull output circuits will be described below as second and third embodiments.

[Embodiment 2] A second embodiment of the present invention will be described with reference to FIG. 5. In this case as well, it is assumed that V REFI < V REF2.

The input signal VIN' drops due to the circuit operation.

When VIN'< VREFI, transistor Q3
is turned on, and transistor QIA is also turned on. As a result, an emitter-base base current 1a of the lateral PNP transistor QIA flows from +vcc, and this base current Ill flows to the transistor Q3 via the resistor R2. At the same time, base current is supplied to transistor Q and B via transistors Q and A, and transistor Qma
turns on.

What should be noted here is the operation of transistor Qg.

That is, at the same time when the transistor QIA is turned on, a part of the collector current I^ flows to the transistor QIA via the diode-connected transistor Qs. The amount of current IA is adjusted by selecting the resistance value of resistor R2.

As described above, by flowing the current IA, the base accumulated charge is prevented from being accumulated in the transistor QIA by this amount, and its saturation is reduced, so that the transistor QIA
The turn-off time of A is shortened. As a result, the turn-off time of transistor Qma is shortened, and transistor Q
Since the transistor Q211 is not turned on before Ill is yet turned off, generation of through current is prevented.

[Example-3] A third embodiment of the present invention will be described with reference to FIG.

In this embodiment, capacitor C2 is connected to input signal VIN
' is provided to transmit the level change of ' to the base of transistor QIA. In this embodiment, the transistor Q5 is not provided, and VIN'< VREF
From I to VIN>VREFI, transistor QI
Since A is a lateral PNP transistor, it cannot be turned off immediately. However, in this case, the input signal VIN
Transistor Q is activated by transmitting the change from low level to high level to transistor QIA via speed-up capacitor C2. The base stored charge of is immediately sunk through capacitor C2. As a result, the switching speed of transistor QIA from on to off becomes faster, and transistor Qma is immediately turned off, thereby preventing generation of through current.

[Embodiment 4] A fourth embodiment of the present invention will be described with reference to FIG. 7. The features of this embodiment are capacitor CI, transistor 011
tQ12 is provided.

The circuit operation will be explained below. The input signal VIN' changes in level as shown in FIG. 4(B), and when it goes from a low level to a high level, the transistor Qll is immediately turned on via the speed-up capacitor C1, so that the transistor Q12 is also turned on. As a result, transistor Q1
The base accumulated charge of ＾ is connected to + via transistor Q12.
It is discharged to the Vcc power supply line. At the same time, transistor Q3 is turned off and transistor Q1^ performs a turn-off operation, so that the turn-off time of transistor QIA is accelerated and generation of through current is prevented. Note that since the capacitance of the capacitor C1 is extremely small, it can be easily incorporated into the IC.

〔effect〕

(1) The level change of the input signal is compared with first and second reference voltages having different voltage levels, and the vertically connected first and second output transistors are connected to the first and second output transistors.
Since the output transistors are driven with a time difference proportional to the voltage difference between the reference voltages, the first transistor and the second transistor are not turned on at the same time, and it is possible to prevent destruction of the output transistor due to through current.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof.

For example, a time constant circuit composed of resistors R1 and C* is
If the rising and falling parts of the input signal VIN have a slope shape, they may be removed.

[Application field]

In the above description, the invention has been mainly applied to a push-pull output circuit, which is the background field of application of the invention, but the invention is not limited thereto.

It can also be used as a current switching circuit for motor coils.

The present invention can be used at least when detecting a level change in an input signal to switch the current supplied to a load.

[Brief explanation of drawings]

FIG. 1 shows a circuit diagram of a push-pull output circuit studied prior to the present invention, and FIG. 2 shows a waveform diagram showing the circuit operation of the push-pull output circuit. Figure 3 shows the first push-pull output circuit to which the present invention is applied.
FIG. 4 shows a waveform diagram showing the circuit operation of the push-pull output circuit, and FIG. 5 is a circuit diagram of the push-pull output circuit showing the second embodiment of the present invention. FIG. 6 shows a circuit diagram of a push-pull output circuit according to a third embodiment of the present invention, and FIG. 7 shows a circuit diagram of a push-pull output circuit according to a fourth embodiment of the present invention. . Qm + Q2 + Qa + Qa+ Q5+ Ql
ll Q12°". Transistor, VIN, VIN'...input signal,
VREFI. VREF2-...Reference voltage, R,, R2-...Resistance, C
1゜C2...Capacitor. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. first and second voltage comparators having reference voltages having different first and second voltage levels and comparing the reference voltage and the input signal; and the first and second voltage comparators. and vertically connected output transistors that are alternately driven by a voltage source, and the vertically connected output transistors are alternately driven at a time difference corresponding to a difference between the first and second voltage levels. An output circuit characterized in that the output transistors are prevented from being driven simultaneously.