JPS60148171A - Semiconductor device - Google Patents

Abstract

PURPOSE:To hole the symmetry of the characteristics of diffusion resistors extending over a wide temperature range by annexing an auxiliary wiring body to a wiring body in the vicinity of the resistor and symmetrically applying thermal stress to resistor pairs in a device in which a plurality of the diffusion resistors are formed on the same chip. CONSTITUTION:Ion-implanted resistors 2a-2d are formed on a silicon chip 1 having a face orientation (100) so that the longitudinal directions are directed to (110). The resistors 2a-2d have characteristics of which both the resistors 2a and 2b and both the resistors 2c and 2d are arranged symmetrically. Al wirings 3a-3d are shaped near the resistors 2a-2d in parallel or in a crossing manner. An auxiliary Al wiring 3a' generating thermal stress approximately the same as thermal stress applied to the resistor 2b of the Al wiring 3b disposed in parallel with the resistor 2b is formed, and an Al wiring 3c' is also formed similarly.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a semiconductor device having at least two diffused resistors whose characteristics are required to have symmetry on the same chip.
Specifically, the symmetry of the characteristics of the resistor is maintained by compensating for the thermal stress that the resistor, which requires symmetry of characteristics, receives from the wiring body on the same chip as the ambient temperature changes. Related to semiconductor devices.

[Background of the invention]

As a conventional semiconductor device of this type, for example, INTEGR
AL 5ILI(:!ON, DIAPH几AMS FO
RLOWPRESSURE'MEA8UREMENTS
(08P3, 772°628) 5 This method eliminates the influence of thermal stress on the resistor by arranging the resistor at a constant distance in the radial direction on a circular diaphragm.

Another conventional example is a semiconductor pressure-sensitive device described in Japanese Patent Laid-Open No. 57-68080. This is a semiconductor pressure-sensitive device in which a bridge circuit made of a diffused resistor is formed on a diaphragm part formed on a semiconductor substrate. It is inserted into the connection part of the input terminal or output terminal to perform temperature compensation.

Of the two conventional examples above, the former has the restriction of forming a diffused resistor on a circular semiconductor chip, making it unsuitable for applications other than pressure sensors.The latter also requires a resistor for zero point adjustment to be formed on a semiconductor chip. This is disadvantageous in terms of packaging density.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device that can maintain the symmetry of the characteristics of a resistor over a wide temperature range, has a high packaging density, and is versatile.

[Summary of the invention]

In a semiconductor device having at least two diffused resistors whose characteristics are required to have symmetry on the same chip, the present invention provides a wiring body that runs approximately parallel to a pre-resistor, or a wiring parent to the resistor. The present invention is characterized in that an auxiliary wiring body is attached to the wiring body so that thermal stress applied from the body to the resistor is symmetrical to the at least two resistors.

[Embodiments of the invention]

The influence of aluminum (At) wiring on diffusion resistance will be explained based on our experimental results. In Figure 1,
The semiconductor device used in the experiment is shown.

1 is a 3++m square, +100) silicon (SI) chip with a thickness of 400 μm, and 2a to 2d have a maximum impurity concentration of approximately 5.
Ion (boron) implantation resistance of X10 "crn-", 3a
-3dt'j, an At electrode for connecting the resistor gold bridge and for drawing out the external electrode, and has a thickness of about 2 μm. 4 is an oxide film. Resistance 2a -2d is (110
) direction.

The layout of the resistor and the At wiring is the same as that shown in FIG. 1(a), and the resistors 2b and 2d and the AA wiring 3C and 3d have parallel portions with a distance of 80 μm. On the other hand, the parallel portions of the resistors 2a and 2C and the At wiring are separated by 500 μm or more.

To avoid restraining this chip to the package, wire bonding is performed as shown in FIG. 2, and resistors 2a and 2d are connected.
A constant voltage E b (2,55V) is applied between the connection point 5 of , and the connection point 6 of resistors 2b and 2C, and
The output Vo between the connection point 7 of the resistors 2a and 2b and the connection point 8 of the resistors 2a and 2b was measured while changing the ambient temperature. The measurement results are shown in Figure 3.A hysteresis loop was drawn in the direction of the arrow shown in Figure 9.

When the At wiring thickness was halved to 1 μm, the hysteresis loop opening was reduced by about 40 inches.

The reason for this can be explained as follows. FIG. 5 shows the results of calculating the thermal stress of the two-dimensional model shown in FIG. 4 using the finite element method. The calculation conditions are as follows.

(1) At wiring 3; width sooμm, thickness 2pm, longitudinal elastic modulus 5.3 x 103Kq/rtrm", transverse elastic modulus 3.4 x 10" K9/Wa2, linear expansion coefficient 2.9X10-'/C ;Assumed no surrender.

) Silicon (Si) tip/: Longitudinal elastic modulus, 1.5
X 10'K97grn", transverse elastic modulus 6XlO
”, line j Cedar expansion coefficient a, 4xio-'/c (3) Oxide film (S' (J2) 4: thickness 1 pm, longitudinal elastic modulus 7.3 X 10'' Kg1 period 2, transverse elastic modulus 3.1
×10”Kg/throat 2, linear expansion coefficient 5x, 1o-7/Cz
FIG. 5 shows the relationship between position and stress with the end surface 9 of the A7 wiring 3 as the origin. In the figure, lO is the stress on the center plane of the At wiring 3, and corresponds to the right vertical axis. 11 is an oxide film (SI0
2) Stress on the inner surface of the 1 μm silicon (Si) chip 1 below 4, corresponding to the left vertical axis. Directly below the At wiring 3, negative or compressive stress is acting, and where there is no At wiring 3, positive or tensile stress is acting. Of course -40tl
When changing from l: to 25C, the sign of the stress is reversed. What is important here is that if the A4 wiring 3 does not break down, a tensile stress of about 20 Ky/m2 will occur. Naturally, the At wiring 3 is unraveled in the middle, and no large stress is generated.

“Metals and Alloys” by Kazue Iitaka, Iwanami Zensho (November 1975)
According to 30), the yield point of pure aluminum (At) is 5.6-6.3 K9/K2. So ±6 K
g/m”, then At
Regarding the temperature and thermal stress of the wiring, a hysteresis loop shown in FIG. 6(a) can be drawn.

In the same figure (a), in the area of straight line 12, 22Kq/r
rm” / 95r3 because 12
Tensile stress changes from 0C to 25C by 95C to 22 9/
Fight 2 occurs, therefore -6YCq/ta at 120C
The temperature at which the temperature decreases from the state of yielding under compression of n' and yielding at a tensile stress of +6Kg/1121+2 is 70C. In this way we draw a hysteresis loop with a yielding region 14.15 and an elastic region 12.13.

Corresponding to the hysteresis pool of the At wiring 3, the thermal stress due to the At wiring on the surface of the silicon chip 1 also draws a hysteresis loop. 80 μm from the end surface 9 of the At wiring 3 in FIG.
The stress in the separated part of the gauge resistor 2 (position g in Fig. 5) is due to the breakdown of the At wiring 3, as shown in Fig. 6(b).
It becomes as shown in . In the figure, the gradient in the region 12' is 0.043 Kg/lrm2/95C. This is because, in Fig. 5, the stress at the resistance position g is 0.043
This is because it is Kg/m2 (when changing from 120C to 25C). Furthermore, the At wiring 3 is 120C
Breakdown occurs when the temperature changes from
Therefore, since it is considered that the stress is balanced between positive and negative, the stress inside the silicon chip 1 is approximately ±
Yielding occurred at 0.01 Kg/m'', 14'.

Draw hysteresis loops of 13' and 15'. In reality, the breakdown of At wiring is ±6Kg/M as just thought! Figure 6 (a).

12 (12') and 14 (14') and 13 (13') and 15 (15') in (b) are continuously connected by curves.

Now, let us roughly estimate the hysteresis of the bridge output shown in FIG. 2 when the hysteresis shown in FIG. 6(b) occurs.

The bridge output with respect to the drive voltage with a hysteresis stress Δσ of 0.02 Kg/rm” is expressed by the following equation.

Here, GF is about 100 in gauge factor (surface impurity concentration 5
×IQ1g1. resistance direction <110>), Y is the longitudinal elastic modulus of Si.

Substitute the numerical value into the above formula f ij', V , / E b I
d 7 Xl0-'. On the other hand, the hysteresis shown in Fig. 3 is 8 x 10"5, and the two are in agreement. In this way, we can understand that the cause of the hysteresis shown in Fig. 3 is the wiring near the resistor. This was clarified through experiments and analysis.

Therefore, if the shape of the wiring that passes near or above the resistor that requires symmetry is arranged symmetrically with respect to each resistor, the two resistances will change uniformly and the symmetry will be maintained. Can be kept well. This is the basic concept of the present invention.

An embodiment of a semiconductor device according to the present invention is shown in FIGS.

3(a) is a top view, and FIG. 1(b) is an AA@ side view.

This embodiment is an example applied to a pressure sensor. Components corresponding to those in FIG. 1 are given the same reference numerals.

The functions of the semiconductor device shown in FIG. 7 are as follows.

That is, when pressure is applied from the top surface of the chip 1, the thinly processed diaphragm 16 deforms, and stress is generated on the surface of the diaphragm 16, causing resistance elements 2a and 2C to deform.
The resistance value of 2b and 2d decreases while the resistance value of 2b and 2d increases. For example, if a Wheatstone bridge configuration is formed using At wirings 3a, 3b, 3C, and 3d as shown in the figure, an output proportional to pressure can be obtained.

Generally, (100) is used as the plane orientation of the chip. This is because the diaphragm 16 can be easily formed by anisotropic etching, and at the same time, it will be easier to attach additional circuits such as amplifiers to the periphery of the chip using an IC process in the future. To obtain the maximum output, the longitudinal direction of the resistors 2a to 2d should be <110>. 4 when there is no pressure
The characteristics of the individual resistors must be the same. Due to the layout, it may be necessary to provide an At wiring in parallel near the resistor 2b or i2d as shown in the figure. On the other hand, even if it is not necessary to lay out the kl wiring in parallel near the resistor 2a or 2C, if the lt wiring 3a' and 3c/ are not provided, hysteresis will occur at the zero point due to temperature cycles for the reason mentioned above. occurs. Therefore, in this embodiment, the hysteresis of the sensor output is eliminated by providing the A, 6 wirings 3a' and 3c/. In the case of this embodiment, it is necessary that the resistors 2a and 2b and the resistors 2C and 2d have symmetrical characteristics.

Therefore, an auxiliary At wiring 3a' is provided which generates a thermal stress equal to the thermal stress exerted on the resistor 2b by the A4 wiring 3b placed parallel to the resistor 2b, and the At wiring 3c is similarly placed.
/ If also provided, four resistors 2a, 2b, 2c, 2
An equal amount of hysteresis occurs in d, and as a bridge output, it is almost compensated. The point is that the action of the At wirings 3a' and 3C is to generate thermal stress equal to the thermal stress exerted by the At wirings 3b and 3d on the resistors 2b and 2d, so as shown in the figure, the At wirings 3a' ( There is no guarantee that 3G') and 3a (3C) are connected. Further, the arrangement location may be reversed or may be arranged on both sides.

According to this embodiment, it is not necessary to separate the At wiring sufficiently from the resistor, and the mounting density of the resistor can be increased. At
It has the advantage of being able to be produced using the same process as the wiring process.

FIG. 8 shows another embodiment. (a) shows an H differential amplification stage. The emitters 21 and 24 of the input transistors Q1 and Q2 are commonly connected, and the collectors 19 and 22 are connected to the power supply 0.1 through load resistors 17 and 18, respectively. It is connected to the. What is important in this circuit is that the characteristics of resistors 17 and 18 must be sufficiently symmetrical. This is because the imbalance in the characteristics of the two resistors 17 and 18 directly affects the offset. Same figure (b)
is an example of the layout shown in FIG. This connects the At wiring 26 coming out from the base 23 of transistor Q2 to resistor 1.
This is an example when it is necessary to pass through the neighborhood of 8. On the other hand, when the At wiring 25 coming out from the transistor Q1 is passed vertically as shown in the figure, the resistor 18 and the A7 wiring 26
There is no symmetry between the positional relationship between the resistor 17 and the At wiring 25.

Therefore, the auxiliary At wiring 27 corresponds to the A4 wiring 26.
By arranging the temperature hysteresis of the resistor is 2
transistors Q1. Hysteresis no longer appears between collectors 19 and 22 of Q2.

Another embodiment of the invention is shown in FIG. Figure 7(a) is A
The structure of a part of the resistance ladder used in the /D converter and the D/A converter is shown.
9.30 is the resistance ladder and wiring 31 to obtain the reference voltage
, 32 and 33 are wirings for outputting the reference voltage. Same figure (
An example of the layout is shown in b). In the same figure, when the wiring 34 has to cross over the resistor 30, the auxiliary At wiring 35.35' is also placed over the other resistors 28.29.
By arranging the resistor array, the symmetry of the characteristics of the resistor string can be maintained and hysteresis can be eliminated.

〔Effect of the invention〕

According to the present invention, it is possible to maintain the symmetry of the characteristics of a resistor over a wide temperature range, and it is also possible to realize a semiconductor device with high packaging density and versatility.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a semiconductor device for explaining the basic concept of the present invention, FIG. 1(a) is a plan view thereof, and FIG. 1(b) is a sectional view taken along line A-A in FIG. , FIG. 2 is a measurement circuit diagram of the semiconductor device shown in FIG. 1, and FIG. 3 is a diagram showing the measurement results of temperature characteristics by the measurement circuit shown in FIG. 2.
Figure 4 is a diagram showing the semiconductor device in Figure 1 as a two-dimensional model, and Figure 5 is a diagram showing the thermal stress on the inner surface of the silicon chip calculated using the finite element method using the two-dimensional model shown in Figure 4. FIG. 6 is a diagram showing the hysteresis characteristics of thermal stress, FIG. 7 is a diagram showing the configuration of an embodiment of a semiconductor device according to the present invention, and FIG. 6A is a plan view thereof. (b) is a sectional view taken along line A-A in FIG. 8(a), FIG. 8 shows another embodiment of the semiconductor device according to the present invention, FIG. ) is a diagram showing the mounted state, FIG. 9 shows still another embodiment of the semiconductor device according to the present invention, FIG. 9(a) is its circuit diagram, and FIG. 9(b) is a diagram showing its mounted state. It is. 1... Semiconductor chip, 2a-2b... Diffused resistor,
3 a~3 d-・At wiring, 27, 35.35 no.
・Supplementary No. 10 2b (b) C No. Z [2] 30 1 cliff (・C) 40 Chi 512] No. 60 0 (b) '7th entrance (82 (b) ' 2nd δ entrance (Ku 2nd 912] (Kun (b) "3q Continuation of page 1 [phase] Inventor Ryo Kobayashi - Inside Hitachi Wheelworks

Claims (1)

[Claims] 1. In a semiconductor device having at least two diffused resistors whose characteristics are required to have symmetry on the same chip, from a wiring body that runs approximately parallel to the resistor or a wiring body that intersects with the resistor. A semiconductor device characterized in that an auxiliary wiring body is attached to the wiring body so that thermal stress does not reach the resistor and is symmetrical to the at least two resistors.