JPS60148158A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS60148158A
JPS60148158A JP59003766A JP376684A JPS60148158A JP S60148158 A JPS60148158 A JP S60148158A JP 59003766 A JP59003766 A JP 59003766A JP 376684 A JP376684 A JP 376684A JP S60148158 A JPS60148158 A JP S60148158A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
semiconductor chip
circuit board
semiconductor chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59003766A
Other languages
Japanese (ja)
Inventor
Fumiyoshi Matsumura
松村　文好
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59003766A priority Critical patent/JPS60148158A/en
Publication of JPS60148158A publication Critical patent/JPS60148158A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

PURPOSE:To prevent the induction of noises from an adjacent chip by covering the periphery of a semiconductor chip with a metallic cap fitted to a land for shielding. CONSTITUTION:A conductor land 4 is mounted around a semiconductor chip 3 of semiconductor chips 2 and 3 loaded on the upper surface of a circuit substrate 1 while a metallic cap 5 covering the semiconductor chip is set up by utilizing the land 4. Accordingly, the induction of noises from the adjacent chip 2 can be prevented.

Description

【発明の詳細な説明】 イ、産業上の利用分野 不発ＢＡは、回路基板に集積回路素子などの半導体チッ
プの複数が搭載されてなる混成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application BA relates to a hybrid integrated circuit in which a plurality of semiconductor chips such as integrated circuit elements are mounted on a circuit board.

口、従来技術 従来、集積回路素子、または個別のトランジスタ集子な
どの形成された半導体チップの複数個を回路基板に共に
搭載した混成集積回路における誘導ノイズ対策として、
チップ同志の間隔を広くとるのが一般的であった。すな
わち、第１図に示すように、回路基板ｌに半導体チップ
２と３が一緒に搭載されている場合、これらの間のノイ
ズ誘導を避けるためには、チップ２と３との間の距離を
大きくしなければならず、そのため、半導体チップの実
装密層は低くなシ、大きな回路基板を要するという欠点
があった。BACKGROUND OF THE INVENTION Conventionally, as a countermeasure against induced noise in a hybrid integrated circuit in which a plurality of semiconductor chips such as integrated circuit elements or individual transistor clusters are mounted together on a circuit board,
It was common to leave a wide gap between the chips. That is, as shown in FIG. 1, when semiconductor chips 2 and 3 are mounted together on a circuit board l, in order to avoid noise induction between them, the distance between chips 2 and 3 must be Therefore, the mounting density of the semiconductor chip is low and a large circuit board is required.

７１　発明の目的 本発明の目的は、回路基板に搭載した行数の半導体チッ
プの間が近接していても、お互いのノイズ誘導などが防
止された混成集積回路１を提供することにある。71 OBJECTS OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit 1 in which mutual noise induction is prevented even if the semiconductor chips mounted on a circuit board are close to each other.

二０発明の構成 本発明によれは、回路基板に搭載した複数の半導体チッ
プのうち少くとも一個の半導体チップの周囲に、この半
壽付チップが受ける誘導ノイズからしやへいするための
導体ランドか訃′けられた混成集積回路が得られる。20. Structure of the Invention According to the present invention, a conductor land is provided around at least one semiconductor chip among a plurality of semiconductor chips mounted on a circuit board for shielding the semi-conductor chip from induced noise. A failed hybrid integrated circuit is obtained.

ホ、実施例 つぎに本発明を実施例によシ説明する。E, Example Next, the present invention will be explained using examples.

第２図（ａ）は本発明の一実施例の断面図、同図（ｂ）
は一部切シ欠いた平面図である。第２図ｊ　（２）、Φ
）において、回路基板ｌの上面に搭載した半導体チップ
２と３のうち、テップ３の周囲には、導体ランド４が設
けられ、この導体ランド４を利用して、半導体チップ３
を被う金属キャップ５が取付けられ、導体ランド４は接
地端子６に引き出されている。FIG. 2(a) is a sectional view of an embodiment of the present invention, and FIG. 2(b) is a sectional view of an embodiment of the present invention.
is a partially cutaway plan view. Figure 2j (2), Φ
), a conductor land 4 is provided around the tip 3 of the semiconductor chips 2 and 3 mounted on the upper surface of the circuit board l, and the conductor land 4 is used to connect the semiconductor chip 3.
A metal cap 5 is attached to cover the conductor land 4 and the conductor land 4 is led out to a ground terminal 6.

へ　発明の効果 上記のとおり、回路基板に搭載した検数の半導体チップ
のうち、特に外部ノイズを出し易い半導体チップ３は、
接地したキャップによＪＨｌｉわれているので、隣シ合
う半導体チップ２との間の彫離を近付けても、半導体テ
ップ２へのノイズ誘樽は防止される。Effects of the Invention As mentioned above, among the semiconductor chips mounted on the circuit board, the semiconductor chip 3, which is particularly prone to emitting external noise,
Since it is grounded by the grounded cap, noise is prevented from being introduced to the semiconductor chip 2 even if the separation between adjacent semiconductor chips 2 is brought closer.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の混成集私回路の断面図、無２図（ａ）お
よび同図の）は本発明の一実施例の断面図と一部切シ欠
いた平面囚である。 １・・・・・・回路基板、２，３・・・・・・半導体チ
ップ、４・・・・・・し中へい用導体２ンド、５・・・
・・・キャップ、６・・・・・・接地端子。FIG. 1 is a sectional view of a conventional hybrid integrated private circuit, and FIG. 1...Circuit board, 2,3...Semiconductor chip, 4...Inner conductor 2nd, 5...
...Cap, 6...Ground terminal.

Claims (1)

【特許請求の範囲】[Claims] 回路基板に複数の半導体チップを搭載してなる混成集積
回路において、前記半導体チップのうちの少くとも一つ
の半導体チップの周囲に、この牛清体チップをし中へい
するための導体ランドが設けられていることを特徴とす
る混成集積回路。In a hybrid integrated circuit formed by mounting a plurality of semiconductor chips on a circuit board, a conductive land is provided around at least one of the semiconductor chips for inserting the body chip into the circuit board. A hybrid integrated circuit characterized by:
JP59003766A 1984-01-12 1984-01-12 Hybrid integrated circuit Pending JPS60148158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59003766A JPS60148158A (en) 1984-01-12 1984-01-12 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59003766A JPS60148158A (en) 1984-01-12 1984-01-12 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS60148158A true JPS60148158A (en) 1985-08-05

Family

ID=11566287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59003766A Pending JPS60148158A (en) 1984-01-12 1984-01-12 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS60148158A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400949A (en) * 1991-09-19 1995-03-28 Nokia Mobile Phones Ltd. Circuit board assembly

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400949A (en) * 1991-09-19 1995-03-28 Nokia Mobile Phones Ltd. Circuit board assembly
US5442521A (en) * 1991-09-19 1995-08-15 Nokia Mobile Phones Ltd. Circuit board assembly

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