JPS60147123A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60147123A
JPS60147123A JP187784A JP187784A JPS60147123A JP S60147123 A JPS60147123 A JP S60147123A JP 187784 A JP187784 A JP 187784A JP 187784 A JP187784 A JP 187784A JP S60147123 A JPS60147123 A JP S60147123A
Authority
JP
Japan
Prior art keywords
silicon
oxide film
silicon wafer
gas
vacuum chamber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP187784A
Other languages
Japanese (ja)
Inventor
Masayoshi Sasaki
佐々木 正義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP187784A priority Critical patent/JPS60147123A/en
Publication of JPS60147123A publication Critical patent/JPS60147123A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Abstract

PURPOSE:To obtain clean surface on wafers by a method wherein a semiconductor substrate, having an oxide film on the chemically washed surface, is heat- treated in a vacuum atmosphere of specific partial pressure of gas of silicon steam or silicon compound gas, and the oxide film is evaporated. CONSTITUTION:When the washing process using a bunch of chemical solutions is finished, a silicon wafer 21 is set in a vacuum chamber. After the vacuum chamber has been evacuated to the vaccum state of 1X10<-5>Pa or below, it is heated up to the temperature range of 600 deg.C-900 deg.C, and silicon steam of gas partial pressure of 8X10<-5>-1X10<-7>Pa is introduced therein. The SiO2 film 22 formed by chemical washing is turned into volatile gas of SiO type by the reaction with silicon steam. The oxide film 22 on the surface of the silicon wafer 21 is evaporated, and it is finally removed. As a result, a clean surface is obtained on the silicon wafer 21. Besides, the time required for performance of the above-mentioned procedures is 2-30min or thereabout.

Description

【発明の詳細な説明】 (技術分野) この発明は半導体装置の製造方法、詳しくは。[Detailed description of the invention] (Technical field) The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device.

半導体表面、特にシリコン表面を清浄にするための方法
に関するものである。
The present invention relates to a method for cleaning semiconductor surfaces, particularly silicon surfaces.

(従来技術) 従来、シリコンなどの単結晶基板上に結晶をエピタキシ
ャル成長させるには、CVD(化学気相成長法)が用い
られてい友が、この方法で結晶性の良いエピタキシャル
層を得るには、900℃程度以上の高温でシランなどの
ガスを分解させ、エピタキシャル成長させる必要があつ
几。
(Prior Art) Conventionally, CVD (chemical vapor deposition) has been used to epitaxially grow crystals on a single crystal substrate such as silicon, but to obtain an epitaxial layer with good crystallinity using this method, It is necessary to decompose gases such as silane at high temperatures of around 900 degrees Celsius or higher for epitaxial growth.

これに対して最近、分子線エピタキシャル法や固相エピ
タキシャル法など、比較的低温(600℃程度)でエピ
タキシャル成長を行う技術が注目されるようになってき
ている。このような方法でエピタキシャル成長を行うた
めには、基板の結晶の表面の清浄度が充分に良いことが
必要になる。
In contrast, recently, techniques for performing epitaxial growth at relatively low temperatures (about 600° C.), such as molecular beam epitaxial method and solid phase epitaxial method, have been attracting attention. In order to perform epitaxial growth using such a method, it is necessary that the surface of the crystal of the substrate be sufficiently clean.

従来、基板表面の良好な清浄度を得る方法としてスパッ
タクリーニング法が行われてい友。これは、基板表面に
付層した不純物を、アルゴンイオンなどをぶつけること
により取り去るものであるが、500℃程度のスパッタ
後に7エールをしても、スパ°ツタによる結晶のダメー
ジが残ってしまうという問題があつ几。また、スパッタ
クリーニング法に代ってh I X 10−” Pa程
度の真空中で1000℃以上の高温まで基板を加熱し、
表面の不純物を蒸発させる方法も行われて−るが、これ
は。
Conventionally, sputter cleaning has been used as a method to obtain good cleanliness of the substrate surface. This method removes impurities deposited on the surface of the substrate by bombarding them with argon ions, etc. However, even after sputtering at around 500 degrees Celsius, damage to the crystals due to spatter remains. There's a problem. Alternatively, instead of the sputter cleaning method, the substrate is heated to a high temperature of 1000° C. or higher in a vacuum of about 10-” Pa,
There is also a method of evaporating surface impurities, but this is not the case.

低温での工、ビタキシャル成長という点からみると。From the point of view of low-temperature processing and bitaxial growth.

基板を一度、高温にしてしまうので1分子線エピタキシ
ャル法の特徴を殺してしまう部分があう几。
Since the substrate is heated to a high temperature once, this method destroys the characteristics of the single-molecule beam epitaxial method.

(発明の目的) この発明は上記の点に鑑みなされたもので、その目的は
、900℃以下の低温で、かつ基板にダメージを与える
ことなく表面の清浄化を実現できる半導体装置の製造方
法を提供することにある。
(Objective of the Invention) This invention was made in view of the above points, and its object is to provide a method for manufacturing a semiconductor device that can realize surface cleaning at a low temperature of 900° C. or lower and without damaging the substrate. It is about providing.

(発明の概要) この発明の要点は、薬品洗浄で表面に酸化膜を形成した
半導体基板を、シリコン蒸気あるいはシリコン化合物ガ
スのガス分圧がBxlo−’〜1x10−’Paの真空
中で加熱処理して前記酸化膜を蒸発させることにより、
清浄な表面を得ることにある。
(Summary of the Invention) The main point of this invention is to heat a semiconductor substrate on which an oxide film has been formed on the surface by chemical cleaning in a vacuum at a gas partial pressure of silicon vapor or silicon compound gas of Bxlo-' to 1x10-'Pa. By evaporating the oxide film by
The goal is to obtain a clean surface.

(実施例) 以下この発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.

第1図および第2図はこの発明の一実施例を示し、第1
図は工程の説明図、第2図は一部の各工程におけるシリ
コンウエノAの断面図である。
FIG. 1 and FIG. 2 show one embodiment of the present invention.
The figure is an explanatory diagram of the steps, and FIG. 2 is a sectional view of the silicon wafer A in some of the steps.

第1図の工程1に示すように、この発明の一実施例では
、まず、硫酸(H,SO4)と過酸化水素(Hz O!
 )の3対1の混合液を約100℃に加熱し、その中に
半導体基板としてのシリコンウエノ・を約5分間浸潤(
ディラグ)させることにより、シリコンウェハ表面の油
脂など有機物や、重金属など無機物を除去する。次に、
シリコンウエノ・を第1図の工程2で示すように5分間
、純水洗浄(純水す/ス)シタ後、第1図の工程3で示
すように5チのフッ化水素酸(HF)液に2分間浸潤(
ディラグ)させ、シリコンウエノ・表面に硫酸・過酸化
水素洗浄で形成された酸化膜を除去する。
As shown in Step 1 of FIG. 1, in one embodiment of the present invention, sulfuric acid (H, SO4) and hydrogen peroxide (Hz O!
) is heated to about 100°C, and silicon urethane as a semiconductor substrate is infiltrated into it for about 5 minutes (
This process removes organic substances such as oil and fats and inorganic substances such as heavy metals from the surface of the silicon wafer. next,
After washing the silicone urethane with pure water for 5 minutes as shown in step 2 in Figure 1, it was washed with 5 liters of hydrofluoric acid (HF) as shown in step 3 in Figure 1. Soak in the liquid for 2 minutes (
De-rag) to remove the oxide film formed on the surface of the silicone by cleaning with sulfuric acid and hydrogen peroxide.

しかる後、シリコンウエノ・を第1図の工程4で示すよ
うに5分間、純水洗浄(純水リンス)する。
Thereafter, the silicon wafer is washed with pure water (rinsed with pure water) for 5 minutes as shown in step 4 of FIG.

なお、これらの工程は、一般に広く行われている洗浄方
法である。
Note that these steps are generally widely used cleaning methods.

しかる後、第1図の工程5で示すように、塩酸(HCJ
 )と水(H,0)と過酸化水素(Hoot )の31
対3対1の混合液を約80℃に加熱した薬品中にシリコ
ンウエノ)を約5分間浸潤(ディラグ)させ、次いで第
1図の工程6および7で示すようにシリコンウェハを1
0分間、水洗い(純水リンス)シ。
After that, as shown in step 5 of FIG. 1, hydrochloric acid (HCJ
), water (H,0), and hydrogen peroxide (Hoot ), 31
Silicon wafers are infiltrated (de-raged) for about 5 minutes in a 3:1 mixture of chemicals heated to about 80°C, and then silicon wafers are soaked (de-lag) for about 5 minutes as shown in steps 6 and 7 in FIG.
Rinse with water (pure water) for 0 minutes.

乾燥させる。ここで、塩酸−水・過酸化水素混合液は、
シリコンウェハ表面の重金属などの無機的な汚れを除去
するだけでなく、シリコンウェハを空気中にさらした場
合にシリコンウェハ表面にガスの吸着を防ぐ酸化膜(S
in、)を約2OA厚に形成する。この酸化膜が形成さ
れたシリコンウェハを第2図(b)に、また、酸化膜が
形成される前のシリコンウェハを第2図(aJに示す。
dry. Here, the hydrochloric acid-water/hydrogen peroxide mixture is
In addition to removing inorganic contaminants such as heavy metals from the silicon wafer surface, the oxide film (S
in,) is formed to a thickness of about 2OA. A silicon wafer with this oxide film formed thereon is shown in FIG. 2(b), and a silicon wafer before the oxide film is formed is shown in FIG. 2(aJ).

これらの図において、21はシリコンウェハ、22は酸
化膜である。なお、以後の説明では、シリコンウェハに
符号21を、また酸化膜に符号22を付して説明を行う
ことにする。
In these figures, 21 is a silicon wafer and 22 is an oxide film. In the following description, the silicon wafer will be denoted by 21, and the oxide film will be denoted by 22.

以上のようにして一連の薬品による洗浄を終えたならば
、次に、シリコンウェハ21を第1図の工程8で示すよ
うに真空チャンバ内にセットする。
After completing the series of chemical cleaning operations as described above, the silicon wafer 21 is then set in a vacuum chamber as shown in step 8 in FIG.

そして、第1図の工程9で示すように、真空チャンバ内
をI X 10−’Pa以下の真空1例えばlXl0−
’Pa程度の真空まで排気した後、第1図の工程10で
示すようにシリコンウェハ21を600’0〜900℃
に加熱する。さらに、第1図の工程11で示すように、
ガス分圧が8 X 10−” −I X 10−’Pa
Then, as shown in step 9 in FIG.
After evacuating to a vacuum of about 'Pa, the silicon wafer 21 is heated at 600'0 to 900°C as shown in step 10 of FIG.
Heat to. Furthermore, as shown in step 11 of FIG.
Gas partial pressure is 8 X 10-"-I X 10-'Pa
.

例えばI X 10−’Pa程度のシリコン蒸抵を真空
チャンバ内に導入する。
For example, a silicon vapor resistance of about I x 10-'Pa is introduced into the vacuum chamber.

シリコン蒸気を真空チャンバ内に導入すると、前記シリ
コンウェハ21表面に薬品洗浄で形成された酸化膜(S
iOx ) 22は、そのシリコン蒸気と反応してSi
Oの形の揮発性ガスとなる。したがって、シリコンウェ
ハ21表面の酸化膜22は第2図(cJに示すように蒸
発し、最終的には第2図(d)に示すように除去される
。これKよジ、シリコンウェハ21は清浄な表面が得ら
れる。なお、これに要する時間は2分から30分程度で
ある。また、真空チャンバ内に導入する前記シリコン蒸
気は、シリコンを加熱、蒸発させることにより得ら21
゜る。
When silicon vapor is introduced into the vacuum chamber, an oxide film (S) formed on the surface of the silicon wafer 21 by chemical cleaning is removed.
iOx ) 22 reacts with the silicon vapor to form Si
It becomes a volatile gas in the form of O. Therefore, the oxide film 22 on the surface of the silicon wafer 21 evaporates as shown in FIG. 2 (cJ), and is finally removed as shown in FIG. 2 (d). A clean surface can be obtained.The time required for this is about 2 to 30 minutes.In addition, the silicon vapor introduced into the vacuum chamber is obtained by heating and evaporating silicon.
゜ru.

しかる後、必要ならば真空チャンバ内のシリコン蒸気を
排気した上で、第1図の工程12で示すように、同一チ
ャンバ内でそのまま連続してシリコンあるいはスピネル
(Alt、Os MyO)などをクリコンウェハ21上
に分子線エピタキシャル成長させる。この時、チャンバ
内の真空度をI X 10−’Pa以下とし、シリコン
ウェハ21の温度を500〜800℃に保てば、先の酸
化膜22の除去工程(クリー二ング工程)で清浄化され
たシリコンウェハ21表面上に、エピタキシャル成長を
妨ケる不純物原子が存在しないので、良好なエピタキシ
ャル層が得られる。このエピタキシャル層ヲ形成した後
のシリコンウェハ21を第2図(eJに示し。
After that, if necessary, after evacuating the silicon vapor in the vacuum chamber, as shown in step 12 of FIG. Molecular beam epitaxial growth is performed on 21. At this time, if the degree of vacuum in the chamber is set to I x 10-'Pa or less and the temperature of the silicon wafer 21 is maintained at 500 to 800°C, the oxide film 22 can be cleaned in the previous oxide film 22 removal process (cleaning process). Since there are no impurity atoms that interfere with epitaxial growth on the surface of the silicon wafer 21, a good epitaxial layer can be obtained. The silicon wafer 21 after forming this epitaxial layer is shown in FIG. 2 (eJ).

図中23はエピタキシャル層である。In the figure, 23 is an epitaxial layer.

以上のよりな一実施例においては、第1図の工程5〜7
で形成された酸化膜22がシリコンウェハ21表面を不
活性化させるため、このシリコンウェハ21を乾燥後、
真空チャンバ内に入れるまでの間に1このシリコンウェ
ハ21の表面に、炭化水素化合物などが吸着されるのを
防ぐことができる。また、この酸化膜22を単なる熱処
理だけで蒸発させるには900℃以上の温度が必要であ
るが、上記一実施例でμ熱処理中にシリコン蒸気にさら
すことにより揮発性のSiOを形成するようにしたので
、よ)低温である600〜900℃で酸化膜22を除去
することが可能になる。よって、この方法によれば、9
00℃以下の低温で、かつシリコンウェハ21にダメー
ジを与えることなく表面の清浄化を実現できる。
In the above embodiment, steps 5 to 7 in FIG.
In order for the oxide film 22 formed to inactivate the surface of the silicon wafer 21, after drying the silicon wafer 21,
It is possible to prevent hydrocarbon compounds and the like from being adsorbed onto the surface of the silicon wafer 21 before it is placed in a vacuum chamber. Further, in order to evaporate this oxide film 22 by mere heat treatment, a temperature of 900° C. or higher is required, but in the above embodiment, volatile SiO is formed by exposing it to silicon vapor during μ heat treatment. Therefore, it becomes possible to remove the oxide film 22 at a low temperature of 600 to 900°C. Therefore, according to this method, 9
The surface of the silicon wafer 21 can be cleaned at a low temperature of 00° C. or lower and without damaging the silicon wafer 21.

′上記一実施例では、シリコンウェハ21表面の酸化膜
(Sin、)22を600〜900℃の低温で除去する
ため、熱処理中にシリコン蒸気を真空チャンバ内に導入
したが、そのシリコン蒸気に代えてシリコン化合物ガス
を真空チャンバ内に導入してもよい。すなわち、ガス分
圧がI X 10−’Pa程度のジクロルシラン、トリ
クロルシラン、シランなどのシリコン化合物ガスを真空
チャンバ内に導入すると、そのシリコン化合物ガスが分
解して、シリコンウェハ表面の酸化膜(Sinり上にシ
リコンが積もる。そして、そのシリコンと酸化膜(S 
i 02) ”が反応して、酸化膜(Sin、)がSi
Oの形の揮発性ガスとなる。したがって、この場合も%
 600〜900℃の低温でシリコンウェハ表面の酸化
膜は蒸発し、最終的には除去され、これにより清浄なシ
リコンウェハ表面を得ることができる。
'In the above embodiment, silicon vapor was introduced into the vacuum chamber during the heat treatment in order to remove the oxide film (Sin) 22 on the surface of the silicon wafer 21 at a low temperature of 600 to 900°C. The silicon compound gas may also be introduced into the vacuum chamber. That is, when a silicon compound gas such as dichlorosilane, trichlorosilane, or silane with a gas partial pressure of about I x 10-'Pa is introduced into a vacuum chamber, the silicon compound gas decomposes and forms an oxide film (Sin) on the surface of the silicon wafer. Silicon is deposited on top of the silicon.Then, the silicon and oxide film (S
i 02)” reacts, and the oxide film (Sin, ) changes to Si.
It becomes a volatile gas in the form of O. So in this case too %
The oxide film on the silicon wafer surface is evaporated at a low temperature of 600 to 900°C and is finally removed, thereby making it possible to obtain a clean silicon wafer surface.

(発明の効果) 以上詳述したようにこの発明の方法によれば、薬品洗浄
で表面に酸化膜を形成した半導体基板をシリコン蒸気あ
るいはシリコン化合物ガスのガス分圧が8 X 10−
’〜lXl0−’Paの真空中で加熱処理して前記酸化
膜を蒸発させることにより清浄な表面を得るようKした
ので、900℃以下の低温で、かつ基板にダメージを与
えることなく表面の清浄化を実現できる。この発明の方
法は、各種結晶材料のエピタキシャル成長や清浄表面利
用技術に利用することができる。
(Effects of the Invention) As detailed above, according to the method of the present invention, a semiconductor substrate on which an oxide film has been formed on the surface by chemical cleaning is treated with a gas partial pressure of silicon vapor or silicon compound gas of 8 x 10-
Since the oxide film was evaporated by heat treatment in a vacuum of ~lXl0-'Pa to obtain a clean surface, the surface could be cleaned at a low temperature of 900°C or less without damaging the substrate. can be realized. The method of the present invention can be used for epitaxial growth of various crystalline materials and techniques for utilizing clean surfaces.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図はこの発明の半導体装置の製造方法
の一実施例を示し、第1図は工程の説明図、第2図は一
部の各工程jCおけるシリコンウェハの断面図である。 21・−・シリコンクエバ、22・・−酸化膜。 第1図 第2図 手続補正書 昭和59年7月16日 特許庁長官志賀 学 殿 1、事件の表示 昭和59年特 許 願第 1877 号2、発明の名、
称 半導体装置の製造方法 3、補正をする者 事件との関係 特 許 出願人 (029)沖電気工業株式会社 5、補正命令の日付 昭和 年 月 日 (自発)6、
補正の対象 明細書の発明の詳細な説明の欄 7、補正の内容 7、 補正の内容 1)明細書2頁14行「500℃程度のスパッタ後に」
を「スパッタ後に500℃程度の」と訂正する。
1 and 2 show an embodiment of the method for manufacturing a semiconductor device of the present invention, FIG. 1 is an explanatory diagram of the steps, and FIG. 2 is a cross-sectional view of a silicon wafer in a part of each step jC. . 21.--Silicon cube, 22.--Oxide film. Figure 1 Figure 2 Procedural amendment July 16, 1980 Manabu Shiga, Commissioner of the Patent Office 1. Indication of the case Patent Application No. 1877 of 1987 2. Name of the invention.
3. Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 5 Date of amendment order Showa Month, Day (Spontaneous) 6.
Column 7 of the detailed description of the invention in the specification subject to amendment, Contents of amendment 7, Contents of amendment 1) Page 2 of the specification, line 14 “After sputtering at about 500°C”
is corrected to "approximately 500°C after sputtering".

Claims (1)

【特許請求の範囲】[Claims] 半導体基板を酸化性薬品中に浸潤させた後、純水洗浄を
行い乾燥させる工程と、その後、前記半導体基板を、・
真空度I X 10−’Pa以下でありかつシリコン蒸
気あるいはシリコン化合物ガスのガス分圧7>E 8 
X 10−’ 〜I X 10−’PaOPa中テロo
o℃から900℃の温度で2分から30分間加熱する工
程とを具備してなる半導体装置の製造方法。
After soaking the semiconductor substrate in an oxidizing chemical, cleaning with pure water and drying the semiconductor substrate;
Vacuum degree I
X 10-' ~ I X 10-' PaOPa medium terrorism o
A method for manufacturing a semiconductor device, comprising a step of heating at a temperature of 0° C. to 900° C. for 2 minutes to 30 minutes.
JP187784A 1984-01-11 1984-01-11 Manufacture of semiconductor device Pending JPS60147123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP187784A JPS60147123A (en) 1984-01-11 1984-01-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP187784A JPS60147123A (en) 1984-01-11 1984-01-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60147123A true JPS60147123A (en) 1985-08-03

Family

ID=11513785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP187784A Pending JPS60147123A (en) 1984-01-11 1984-01-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60147123A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63249332A (en) * 1987-04-06 1988-10-17 Toshiba Corp Manufacture of semiconductor device
CN102339751A (en) * 2010-07-21 2012-02-01 中国科学院微电子研究所 Method for improving later process of gallium nitride field-effect transistor
CN102354663A (en) * 2011-11-08 2012-02-15 浚鑫科技股份有限公司 Method for etching silicon chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63249332A (en) * 1987-04-06 1988-10-17 Toshiba Corp Manufacture of semiconductor device
CN102339751A (en) * 2010-07-21 2012-02-01 中国科学院微电子研究所 Method for improving later process of gallium nitride field-effect transistor
CN102354663A (en) * 2011-11-08 2012-02-15 浚鑫科技股份有限公司 Method for etching silicon chip

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