JPS60146544A - Synchronism supervisory device - Google Patents

Abstract

PURPOSE:To attain synchronism supervision with improved S/N by detecting the difference between the maximum value and the 2nd larger value in the outputs of a multi-value error correction decoder and deciding it as the deterioration of S/N when the difference is smaller than the preset threshold value. CONSTITUTION:An antenna 21 receives a signal subject to frequency hopping FH, a mixer 22 is applied with inverse-spread by using a local signal fL generated from an FH synthesizer 23 driven by a spread core generator 24 so as to generate a multi-value FSK signal based on an error correction code. Frequency components f1, f2... are extracted by a filter bank 25, detected (24) and inputted to an analog register 27. Then the signal is added (28), the maximum value Vmax is detected (29), and further the 2nd maximum value Vmax2 is detected (41). The difference between the Vmax and the Vmax2 is obtained by a synchronism supervising device 42, the result is compared with a prescribed threshold value, and when the difference is small, it is decided as the deterioration of S/N. Thus, the synchronism supervision is attained by using a signal with improved S/N.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a synchronization monitoring device that monitors the synchronization state of spreading codes in a frequency hopping CFH (combined frequency hopping) device of a spread spectrum communication system.

In general, spectrum 2m diffusion has various advantages such as resistance to interference, resistance to fading, and ability to communicate secretly. However, in recent years, its application to mobile areas has become popular.

The biggest problem with this spread spectrum communication system is that when trying to use a frequency band for multiple pages, it is less efficient in frequency use than time division multiplexing or frequency division. Therefore, it is desirable to improve frequency usage efficiency by improving noise and interference resistance using error correction codes in the confidential spread spectrum communication system.
ing. One such method is to use rubbing (i(
A possible method is a combination of the F') method and a multilevel error correction code.

Since the FH formula can be regarded as irregularly multi-value frequency shift keying (FSK), it is easy to use multi-value error correction codes. Such multi-level error correction codes include Reed, Nromon codes,
OCC (One-Coincidence Code),
PH-Coset code etc. τ can be used.

(Prior Art) FIGS. 1(a) and 1(b) show block diagrams of a conventional transmitting system 2 and receiving system using multilevel error correction codes. First, in the transmission system, serial data inputted from the data input terminal 11 is processed by the multi-level error correction encoder 12 with N bits as one word (for example, 47 8.16
value) into a code word consisting of M symbols. By driving the frequency hopping (HF) synthesizer 15 according to this code word and the addition of
It can be sent from 6.

Next, in the receiving system 2 of FIG. 1(b), this receiver is implemented using a matched filter for the error p correction code on the transmitting side. First, FJg was received by antenna 21.
5. Local signal f driven by spreading code generator 24 and generated from frequency hopping (HF) synthesizer 23
When the signal is despread by the mixer 22, a multilevel FSK signal including an error correction code is obtained. Therefore, each frequency component is extracted by a bandpass filter bank 25, detected by a detector 26, and stored in an analog register circuit 27 having a length of M symbols. Since there are 2 possible transmission patterns according to the N bits of the transmission information, 1 shift for M symbols is extracted from each register and added in the Calo arithmetic circuit 28 corresponding to this zNkD pattern. do. If this is done for all 2N patterns, a matched filter for all transmission patterns can be realized, and the maximum value from The data pattern detected by the detector 29 and corresponding to the addition result becomes output information and is output from the data output terminal 33.

Synchronization between the transmitting system and the receiving system is performed by a synchronization control circuit 32, which has a configuration in which the despread F8 signal is passed through a bandpass filter 30 and a detector 31. Controlled by a signal. This synchronization control circuit 32 performs a correlation operation with the received signal when out of synchronization, searches for the synchronized phase of the transmitting system spreading code and the receiving system spreading code,
During synchronization, this synchronized state is maintained.

Generally, in the case of mobile communications, the signal level of the received signal fluctuates drastically due to fading etc.
Although the signal-to-noise ratio (signal-to-noise ratio) also changes in accordance with this variation, it is necessary to accurately determine the synchronous or asynchronous state of the receiving system. Conventionally, this type of synchronization judgment was performed by monitoring the 8/N level of the output signal of the detector 31;
The S/N of the signal is not very high, and the S/N after detection can hardly be improved by a reduction filter, so synchronization judgment using this detection output signal is susceptible to noise and cannot be used accurately. The problem was that it was difficult.

(Objective of the Invention) The object of the present invention is to solve such problems and to perform accurate synchronization determination by using the superior NFC noise resistance and interference resistance properties of the multilevel error correction code. The present invention aims to provide a synchronization monitor It.

(Structure of the invention) The uninvented synchronization monitor uses spectrum spread communication VC2.
The received signals from the filters of each frequency band are assembled and added together to correspond to all 100 transmission patterns of 1 word and N bits. a first level detector for detecting; a second level detector for detecting the second largest reveille addition output from among the previous six summation outputs; 1. and a synchronization monitor that compares the difference between each output of the level detector with a preset threshold value n, and determines that the difference output is smaller than this threshold value as deterioration to @b/. be done.

(Example) The present invention will now be explained in detail with reference to the drawings.

Figure 2 is a block diagram of the receiving system of the uninvented embodiment.
Here, as a specific example, 6 bits 7 nonvol 8 values PN-C
This shows a case where an oset error 9 correction code is used. The non-embodiment includes a second maximum value detector 41 that calculates the second maximum value with respect to the first maximum value detector 29 of the conventional receiving system; The present invention is characterized in that it is provided with a synchronization monitor 42 that compares the level difference between the twelfth and second maximum values with a predetermined threshold.

Next, a specific example will be explained.

FIG. 3 is a block diagram showing a specific example of a transmission system corresponding to FIG. 2. The serial take l-1, which is input from the data input terminal 11, is input to the shift register 121 of the multilevel error correction encoder 12 at the timing of the data clock TD, and the M sequence is input every 6 bits (2 words). Generator 1
23 and register 122. Three bits of this 6-bit data are used as the initial value of the M-sequence generator 123 driven by the chip clock, and the remaining 9
The bits are stored in a register 122 and sent to the M-sequence generator 12 by an Ex-0 processing circuit 124 at every step clock.
Exclusive OR with each register value of 1.3 is taken. Ru. According to this circuit, the period length of the M-sequence code is 7 (=2'-1)
7 symbols of 8 S case P N -Co5et error 9
A correction code word is generated.1. Ru.

This 81 direct PN-Coset code is generated by the spreading code generator 1
3 caused by 1. The adder 14 adds the spreading code and the added code to the frequency hopping synthesizer 15. This spreading code generator 1
3 is composed of a multi-stage shift register 131 and an Ex-OR circuit 132. Wow. Also, each timing 1
H@ is supplied from the reference signal generator 17.

FIG. 4 shows a block diagram from the receiving system detector 26 to the input end of the maximum value analyzer 290 in FIG. 2. After performing despreading, the signal is split into 8 (2T) waves by a bandpass filter bank 25, and the signal at F8 is further sent to a detector 26 for 1. 1. Detection 1. Ru. This 1, r detection, fc base No. 37115 is an analog shift register circuit 2
7 is input.

This analog shift register circuit 27 encodes error correction codes of 8 values and 7 symbols, respectively. (1 word of No. 8 can be stored. Detection data n.

Each baseband signal is divided into eight sample holders 27.
1 for each sample per chip clock.
The hold signal is inputted via a filter amplifier 272 to a seven-stage analog shift register 273 such as a charge-coupled device (CCD).

The respective outputs of these analog shift registers 273 are input to the adder circuit 28 in units of one word, when seven symbols of the error 9 correction code are taken as one word.

This addition circuit 28 is composed of 64 adders 281 and 64 sample holders 282. PN-Cose generated from the multilevel correction encoder 12 on the transmitting side
Since there are 64 possible erroneous 9 correction code words based on 6 bits of information, one shift for 7 symbols is extracted from each register output corresponding to these 64 patterns, and 6
Input n to four adders 281. These 64 types of addition output correspond to fc64 sample holders 28
Sample and hold is performed every 11.1 words input to 2.

This sample-and-hold pin, and the 64 output signals are 1
In order to detect the maximum value and the large 11 on the second foot within one word time, a detector 29 that measures the maximum value and a detector 41 that measures the second most crowded shift are used. Input each 1. Ru.

FIGS. 5 and 6 show block 12, which is the part of the receiving system that detects the second largest value, and its timing chart. Here, sample holder 2 facing 641
82 output signal is switched by the analog switch 291, and then sequentially sent to the constrictor 292 to be compared with 1g.
input as the number νS]1, stored in the sample holder 293, and the sample size1ii1. It is compared with VT. As a result of this comparison of the rising pressure, when the condition of V3) VT is established and P rises, the sample from the controller 292 is
A sample signal 11 is output to the holder 293, and its No. 18 Vs is sampled and held. This Bumple φ holder 293 has an initial value of OV in bold.
, resulting in 64 sample hold 2
81, the maximum value y, max is the sample holder 29
It will be stored in 3.

The second maximum value is then determined by the second maximum value detector 42 using the maximum value n.

First, in the subtracter 411, +j/pull holder 293
Stored in 1. 1. is obtained by sequentially switching the analog switch 291 from the 1st shift Vmax. The comparator 41
2 as a compared signal. This reduction x<ti (V
max -V S is compared with the threshold value VT2 previously stored in the sample holder 413. As a result of this voltage comparison, when the multiplication condition of (Vmax-Vs) (Vd2) holds true, the comparator 412 outputs the AND gate 4.
A sample 1 word is outputted to the sample holder 413 and the sandal holder 415 via n.

Ru. Since a sufficiently large signal is held in the sample holder 413 as an initial value, the signal from the instep of the 64 sample holders 282 is
s) is stored in the sample holder 413 n2, and the sample signal Vs at this time is stored in the sample holder 415 n. Note that the AND gate 414 has Vmax
-Vs = OV signal is sampled and held in the sample holder 413.1. This is to prohibit the use of The fact that the signal (Vmax-Vs) is the minimum means that the signal Vs is between Vmax and '!'! ! This means that the value is large in the second check.

In this way, the maximum one-direction Vmax and the largest one-direction Vmax2 in the second bud are input to the subtractor 421 n5,
You can claim the difference value (Vmax - Vmax 2 ) between Kon, et al. This difference Il@, (Vmax −Vmax 2
) is a few words -, ? In this case, an integrator 422 performs a time integration operation to reduce the time to 5 to 10 words. This integral output is input to the comparator 423 and compared with the smooth dampness fl, fcL and threshold ridge pressure VTH. Ru. When this integrated output becomes smaller than the threshold value VTR, it is determined that the S/N of the e- signal has deteriorated, and an output is provided to the synchronization monitoring output terminal 43.

Note that the analog switch 291 is switched by a 6-bit cyclic counter 296 having a cycle of 64. The data signal is sent to the comparator 292
A sample signal is output from cyclic Φ every n,
The 6-hit output of counter 296 is stored in register 294. The n, 6-bit data stored in this register 294 is transferred word by word to the shift register 295, and is output as temporary data from the data output terminal 33 in accordance with the data clock. Ru.

The comparator 297 has a large value Vm at the second bud.
To avoid Vmax2 = Vmax when finishing ax2, register 2 stores the contents of the cyclic counter 296 when Vmax is obtained.
The 6-bit output of the cyclic counter 294 is compared with the 6-bit output of the cyclic counter 296, and when they match,
The Sunami signal of the sample signal of the comparator 412 is output to the AND gate 414 . In addition, and gate 29
8 is set by a circuit that prohibits a maximum of one direct detection pulse from the comparator 292 because the contents of the register 294 do not change when the large value max2 is set to the second:Il\th.

This prohibition signal uses the MSB output of the counter 299 having a period of 128 (=64×2).

As mentioned above, the invention has been explained with reference to one embodiment, but for example, it is possible to use an A/D converter instead of an analog shift register and replace it with a digital shift register. , and also the maximum value detection 2 and the second
It is also possible to implement the detection system using a digital circuit such as a single-shift detection microprocessor with a large number of scanning lines.

(Effect of the invention) As explained above, the invention decodes data by monitoring the difference between the maximum value of the output of the multi-level error p old decoder and the large value in the second scan. Since this is done by detecting the maximum value level, monitoring the difference from a large value in the second bud is equivalent to monitoring the data error rate.

Furthermore, in order to utilize the output of the matched filter, 8/N
Synchronous monitoring using signals set at 1° is possible.

[Brief explanation of drawings]

Figures 1 (a) and (b) show conventional spread spectrum, I
[! A block diagram of a transmission system and reception system using a multi-level error correction code in the i-fold multivalue system, FIG. 2 is a block diagram of a reception system of a spread spectrum communication system including an uninvented embodiment,
Fig. 3 is a block diagram showing an example of the feed 1B-thread corresponding to Fig. 2, Fig. 4 is a detailed block diagram from the receiving system detector to the input end of the maximum value detector in Fig. 2, and Fig. The figure is a detailed block diagram of the maximum 1 shift 2 and second maximum value detector portions of the receiving system of FIG. 2, and FIG. 6 is a timing chart showing the operation of FIG. 5. In the figure, 11...Data input terminal, 12...Multi-level error 9 correction encoder, 13.24...Spreading code generator, 14゜281... ...Adder, 15.23・
...i (F synthesizer, 16.21...
・Antenna, 17... Base ring signal generator, 22...
・・・・i-xa, 25・・・・band filter bank, 26. 31・・・・・detector, 27・・・analog shift register circuit, 28・・・・・addition Circuit, 29...Maximum value detector, 30...Band filter, 32...Synchronization control circuit, 33...
...Data output terminal, 41...Second maximum value detector, 42...Synchronization monitor, 43...
・Synchronization monitoring output terminal, 121, 131, 295...
...Shift register, 122,294...Register, 123...M sequence generator, 124,13
2...EX-0 ordinary circuit, 271, 282, 29
3,413゜415・・・Sample holder, 27
2...Buffer 'yyy', 273...
・Analog shift register, 291... Analog switch, 292, 297, 412° 423...
... Comparator, 296 ... Two click kakunta, 298,415 ... And gate,
299...Counter, 411.421...
...It is a reducer, 422...It is an integrator. Me1 old

Claims (1)

[Claims] Addition of maximum value from I:P of 2N summation outputs obtained by combining and adding received signals from filters of each frequency band to each other so as to correspond to all transmission patterns of 1 word and N bits in spectral spread communication. A first level detector detects the output, and a second level detector detects the addition output of the second highest level from among the addition outputs.
, and a synchronization monitor that compares the difference between the outputs of the level detectors with a set value and determines that the S/N has deteriorated when the difference output is smaller than this threshold value. Monitoring equipment.