JPS60146354A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS60146354A
JPS60146354A JP204384A JP204384A JPS60146354A JP S60146354 A JPS60146354 A JP S60146354A JP 204384 A JP204384 A JP 204384A JP 204384 A JP204384 A JP 204384A JP S60146354 A JPS60146354 A JP S60146354A
Authority
JP
Japan
Prior art keywords
computer
interface
area
control data
change
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP204384A
Other languages
Japanese (ja)
Inventor
Hideaki Kondo
秀明 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP204384A priority Critical patent/JPS60146354A/en
Publication of JPS60146354A publication Critical patent/JPS60146354A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To increase the operating speed regardless of the reading cycle of the control data by providing a priority area to a main memory of a computer to inform an electric center to a computer interface. CONSTITUTION:A computer interface 3 reads out a priority area 7 and checks the change of a priority bit. When this change is detected, the control data 5 is read out and transferred to a master station TC2. At the same time, the interface 3 reads out the data 5 successively in a comparatively slow fixed cycle and transfers it to the station TC2. The area 7 has a bit inversion for each change of operation by a computer 4 regardless of the interface 3. While the interface 3 always reads out the area 7 and detects a change of operation. Then the interface 3 checks an electric center with an operation request and reads out the control data of the requested electric center.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、・1#報処理方式、特に計算機と遠方監視制
御装置ii(以下TCと呼ぶ)との間の計、8機からT
Cへの制御データの受け渡しのための1n報処理方式に
関するもので必る0 〔発明の技術的背景〕 従来、計算機からTOへの制御データの受け渡しは、計
算機インターフェース装′JL(以下CPIFと呼ぶ)
においてサイクリックに全1気所の制御データを順次計
算機の主メモリから読み出す方式であったO 第1図は従来の系統制御システムにおける計算機システ
ムを示す。1は被制御所(以下子局と言う)TC12は
制御所(以下親局と言う)TC,3は計算機インターフ
ェース、4は計算機、5は計算機の主メモリの制御デー
タエリア、6は計算機の主メモリの子局TCからの表示
データエリアを示す。
Detailed Description of the Invention [Technical Field of the Invention] The present invention provides a 1# information processing method, in particular, a total of 8 to
[Technical Background of the Invention] Conventionally, control data is passed from a computer to a TO using a computer interface device 'JL' (hereinafter referred to as CPIF). )
Figure 1 shows a computer system in a conventional system control system. 1 is a controlled station (hereinafter referred to as a slave station) TC12 is a control center (hereinafter referred to as a master station) TC, 3 is a computer interface, 4 is a computer, 5 is a control data area of the main memory of the computer, 6 is the main station of the computer The display data area from the slave station TC in the memory is shown.

従って、計算機インターフェース3が主メモリの計算機
データエリア5から制御データ全貌み出すために、全電
気所の制御データをサイクIJ 、りに順次読み出して
親局2のTCへ受渡す方式である。
Therefore, in order for the computer interface 3 to extract all of the control data from the computer data area 5 of the main memory, the control data of all electrical stations is sequentially read out in cycle IJ and delivered to the TC of the master station 2.

〔背景技術の問題点〕[Problems with background technology]

王妃した従来方式は最大読み出し1サイクルの待ち時間
が存在するばかシでなく、操作したい4気所の操作対象
にデータを送るために時間がかかる。また、電気所が多
くなると制御データの読み出し周期を速くしないと全電
気所に対して平均的に制御データを受け渡すことができ
ない。しかしながら周期を速くするには限度がある。
The conventional method used does not have a waiting time of one read cycle at the maximum, but it takes time to send data to the four operation targets that you want to operate. Furthermore, when the number of electrical stations increases, the control data cannot be delivered evenly to all electrical stations unless the reading cycle of the control data is made faster. However, there is a limit to how fast the cycle can be made.

〔発明の目的〕[Purpose of the invention]

本発明は、上記問題点′fc屏決することを目的として
なされたものであり、計算機がある電気所を操作する時
、その電気所を計算機インターフェースに知らせること
によシスピードアップをはかった情報処理方式を提供す
ることを目的としている。
The present invention has been made with the aim of solving the above-mentioned problem, and is an information processing system that speeds up the system by notifying the computer interface of the electric station when the computer operates the electric station where the computer is located. The purpose is to provide a method.

〔発明の概要〕[Summary of the invention]

本発明は、計算機がある電気所を操作する時にその電気
所を計算機インターフェースに知らせるエリア(以下優
先エリアと呼ぶ)を計算機の主メモリに用意し、計算機
インターフェースは、常時この優先エリアを監視し、変
化があったら該当電気所の制御データをTCに受け渡し
を行ない、また選択計測など複数電気所の制御データの
読み出しとして比較的遅い定周期に順次全1気所の′!
Jl+御データ全データしてTCVc受は渡そうとする
ものである。
The present invention provides an area (hereinafter referred to as a priority area) in the main memory of the computer that informs the computer interface of the electric station when the computer operates the electric station, and the computer interface constantly monitors this priority area. When there is a change, the control data of the relevant electric station is transferred to the TC, and the control data of multiple electric stations, such as selective measurement, is read out sequentially at a relatively slow regular cycle.
Jl + all data and TCVc receiver are intended to be transferred.

〔発明の実施例〕[Embodiments of the invention]

以下図面全参照して実施例を説明する。42図は本発明
による情報伝送方式の一実施例ブロック図である。第2
図において、1は子局TC,2は親局TC,3は計算機
インターフェース、4は計算機、5は計算機の主メモリ
の制御データエリア、6は計算機の主メモリの子局TC
からの表示データエリア、7は優先エリアを示す。
Embodiments will be described below with reference to all the drawings. FIG. 42 is a block diagram of an embodiment of the information transmission system according to the present invention. Second
In the figure, 1 is the slave station TC, 2 is the master station TC, 3 is the computer interface, 4 is the computer, 5 is the control data area of the main memory of the computer, and 6 is the slave station TC of the main memory of the computer.
7 indicates the priority area.

第3図は、優先エリアの構成であり、ビット単位に電気
所番号が割シ付けられる。第4図はある電気所における
操作と優先エリアの該当電気所のビットの変化のタイム
チャートを示す。Aは魚選コ択、無制御、Bは選択、無
11tlJ御、Cは選択、1UIJ 1il。
FIG. 3 shows the configuration of the priority area, in which electrical station numbers are assigned in bit units. FIG. 4 shows a time chart of operations at a certain electrical station and changes in bits of the corresponding electrical station in the priority area. A is fish selection, no control, B is selection, no control, C is selection, 1UIJ 1il.

Dは操作における優先ビットの変化を示す。なお、ビッ
トの変化は反転t−繰シ返す。第2図の計算機インター
フェース3は、第2図の優先エリア7を読み出し、第4
図の慶先ビットの変化をチェ、りする@この時変化があ
った場合は、第2図の計算機インターフェース3は、第
2図の制御データ5を読み出し、第2図の親局TC2V
C受は渡す。また、第2図の計算機インターフェースは
、比較的遅い定周期に第2図の制御データ5t−順次読
み出し第2図の親局TC2に受け渡す@ そして優先エリア7は計算機4によシ計算機インターフ
ェース3とは無関係に操作の変化があるたびにピッ)t
−反転する。また、計算機インターフェース3は、この
優先エリア7を常時読み出して変化を検出し、゛操作要
求の電気所をチェックして要求された電気所の制御デー
タを読み出す。
D indicates the change of priority bits in the operation. Note that the change in bits is repeated by inversion t. The computer interface 3 in FIG. 2 reads out the priority area 7 in FIG.
Check the change in the destination bit in the figure.@If there is a change at this time, the computer interface 3 in FIG. 2 reads the control data 5 in FIG.
Pass the C receiver. In addition, the computer interface shown in FIG. 2 sequentially reads out the control data 5t shown in FIG. 2 at a relatively slow regular period and delivers it to the master station TC2 shown in FIG. A beep every time there is a change in operation regardless of
- Invert. In addition, the computer interface 3 constantly reads this priority area 7 to detect changes, checks the electrical station for which the operation is requested, and reads out control data for the requested electrical station.

上記した優先エリアの使い方としては、電気所番号をセ
ットする方法と電気所番号をリスト登録する方法などが
あるが、前者は、計算機が優先エリアに電気所番号をセ
ットし、計算機インターフェースで0リセツトする方法
であり、以下の処理はビットの処理と同様である。この
方法は2〜3電気所の優先である。また、後者は計算機
が優先エリアに電気所番号tリストに登録し、計算機イ
ンターフェースでリストから′電気所番号を取υ出す方
法であり、以下の処理はビットの処理と同様である・こ
の方法は、複数電気所の優先でるる。
There are two ways to use the priority area described above, such as setting the electric station number and registering the electric station number in a list.In the former, the computer sets the electric station number in the priority area and resets it to 0 using the computer interface. The following processing is the same as the bit processing. This method is preferred for 2-3 electric stations. In addition, the latter is a method in which the computer registers the electric station number t list in the priority area and extracts the electric station number from the list using the computer interface.The following processing is the same as the bit processing. , Priority delivery for multiple electrical stations.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明によれば優先エリアをもつこ
とにより、制御データの読み出し周期が操作のスピード
と対応していたものが、読み出し周期に関係なく操作の
スピードアップができる。
As explained above, according to the present invention, by having a priority area, it is possible to speed up the operation regardless of the read cycle, even if the read cycle of control data corresponds to the speed of the operation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の系統制御システムにおける計算機システ
ム図、第2図は本発明による情報伝送方式を説明するた
めの一実施例ブロック図、第3図は優先エリアの構成図
、第4図は優先エリアのビット変化のタイムチャートで
ある。 1・・・子局TC,2・・・親/il TC。 3・・・計算機インターフェース、 4・・・計算機、 5・・・計算機の主メモリの制御データエリア、6・・
・計算機の主メモリの子局TCからのデータエリア、7
・・・優先エリア、 A・・・無選択・無11ilJ御
、B・・・選択・無制御、C・・・選択・制御、D・・
・匿先エリアのビットの変化。 (7317)代理人 弁理士 則 近 憲 佑(ほか1
名) 第3図 第4図
Fig. 1 is a computer system diagram in a conventional system control system, Fig. 2 is a block diagram of an embodiment for explaining the information transmission method according to the present invention, Fig. 3 is a configuration diagram of a priority area, and Fig. 4 is a priority area diagram. It is a time chart of bit change of an area. 1...Slave station TC, 2...Parent/il TC. 3... Computer interface, 4... Computer, 5... Control data area of main memory of computer, 6...
・Data area from the slave station TC in the main memory of the computer, 7
...priority area, A...no selection/no control, B...selection/no control, C...selection/control, D...
・Changes in the bits of the hidden area. (7317) Agent Patent Attorney Noriyuki Chika (and 1 others)
Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 電子計算機で処理したメモリ内の情報lDMA方式によ
って読出して複数の遠方監視制御装置へ伝送する情報処
理方式において、電子計算機のメモリ内に情報を格納す
る主メモリエリアとその情報ME先的に処理する指示t
Sたえる優先エリアとをもうけ、1riJ記優先エリア
の指示に従い指示された・l#報を優先的に読み出して
谷遠方監視制御装置へ伝送することt特徴とする情報処
理方式。
In an information processing method in which information in memory processed by a computer is read out using the DMA method and transmitted to multiple remote monitoring and control devices, there is a main memory area in which information is stored in the memory of the computer and the information is processed first. Instructions
The information processing method is characterized in that it has a priority area where the priority area is maintained, and preferentially reads and transmits the designated ・l# information according to the instructions of the priority area and transmits it to a remote monitoring and control device.
JP204384A 1984-01-11 1984-01-11 Information processing system Pending JPS60146354A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP204384A JPS60146354A (en) 1984-01-11 1984-01-11 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP204384A JPS60146354A (en) 1984-01-11 1984-01-11 Information processing system

Publications (1)

Publication Number Publication Date
JPS60146354A true JPS60146354A (en) 1985-08-02

Family

ID=11518294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP204384A Pending JPS60146354A (en) 1984-01-11 1984-01-11 Information processing system

Country Status (1)

Country Link
JP (1) JPS60146354A (en)

Similar Documents

Publication Publication Date Title
EP0194462B1 (en) System bus means for inter-processor communication
JPH03214343A (en) Information processing system and data processing method
JPS60146354A (en) Information processing system
JPH0675887A (en) Polling interval determining system
JP3399776B2 (en) Computer and method for transferring peripheral device control data in computer
JP2984594B2 (en) Multi-cluster information processing system
JPH01185755A (en) System for obtaining bus
JPH02219157A (en) Bus arbiter in computer system
JP3050131B2 (en) Arbitration method
JPH03252847A (en) System bus arbitrating system
JPH036766A (en) Multi-address communication system in multi-processor
JPS6059465A (en) Constitution of terminal device
JPS63206850A (en) Data processing system
JP2000293454A (en) Equipment and method for data communication, and recording medium
JPH0247953A (en) Data transfer system
JPS5944651B2 (en) data transfer device
JPH08101810A (en) Bus control method
JPH0346052A (en) Inter-processor communication method
JPH02156749A (en) Access system for local area network
JPH0343853A (en) Data transfer device
JPH03144757A (en) Packet communication system in network system
JPS629458A (en) Multi-cpu system bus
JPH01100651A (en) Data processing system
JPS6282843A (en) Communication control equipment
JPS63216161A (en) Data transfer system