JPS60146000A - Evaluation of crystal of silicon wafer and preparation of silicon ingot - Google Patents

Evaluation of crystal of silicon wafer and preparation of silicon ingot

Info

Publication number
JPS60146000A
JPS60146000A JP24770583A JP24770583A JPS60146000A JP S60146000 A JPS60146000 A JP S60146000A JP 24770583 A JP24770583 A JP 24770583A JP 24770583 A JP24770583 A JP 24770583A JP S60146000 A JPS60146000 A JP S60146000A
Authority
JP
Japan
Prior art keywords
silicon
silicon wafer
breakdown voltage
single crystal
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24770583A
Other languages
Japanese (ja)
Other versions
JPH0234920B2 (en
Inventor
Masamichi Yoshida
正道 吉田
Kunihiko Wada
邦彦 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP24770583A priority Critical patent/JPS60146000A/en
Publication of JPS60146000A publication Critical patent/JPS60146000A/en
Publication of JPH0234920B2 publication Critical patent/JPH0234920B2/ja
Granted legal-status Critical Current

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Classifications

    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00Single-crystal growth by pulling from a melt, e.g. Czochralski method

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To prepare the desired ingot by judging easily propriety of use, by forming an oxidized film on a silicon wafer made by single crystal pulling method, measuring pressure resistance of the oxidized film. CONSTITUTION:An oxidized film is formed by thermal oxidation on a silicon wafer obtained from a silicon ingot by single crystal pulling method. Pressure resistance of this oxidized film is measured, and in order to make the measured pressure resistance >= a certain value of pressure-resistant value of the highest frequency in terms of relationship between pressure resistance and frequency of a large number of measured results, a raw material of silicon polycrystal having higher purity, a crucible, a heater, an atmospheric gas are used. Further, single crystal, speed of rotation, and temperature profile of heating and cooling are properly controlled, so that a silicon ingot corresponding to use purpose of VLSI, etc. is prepared.

Description

【発明の詳細な説明】 (7)発明の技術分野 本発明は、単結晶引上げ法(以下CZ法という)によっ
て作られたシリコン結晶(すなわち、シリコンウェハ結
晶)の評価方法に関するものであシ、マた、C2法によ
るシリコンインゴットの製造方法に関するものである4
゜ (イ)従来技術 近年、LSIから超LSIへとシリコンデバイスは発展
しておシ、高集積艮でかつ高精度のシリコンデバイスを
高い歩留シで製造するためには、月利結晶を高品質化す
ると同時に、結晶中の小細1物および欠陥を把握し、そ
れぞれ制御することか必要となってきている。これに伴
い結晶評価技術も発展してきている。例えは、電子材料
、1981年2月号(Vol、 20. A 2 )、
(株〕工業調査会発行、において「革新する側斜・プロ
セス評価J、に述f」の特集が組まれておシ、シリコン
結晶δ・1・価技術が紹介されている。
Detailed Description of the Invention (7) Technical Field of the Invention The present invention relates to a method for evaluating silicon crystals (i.e., silicon wafer crystals) produced by a single crystal pulling method (hereinafter referred to as CZ method). 4, which relates to a method for manufacturing silicon ingots using the C2 method.
(a) Prior art In recent years, silicon devices have evolved from LSI to ultra-LSI, and in order to manufacture highly integrated and high-precision silicon devices at a high yield, it is necessary to increase the monthly yield of crystals. At the same time as improving quality, it is becoming necessary to understand and control small particles and defects in crystals. Along with this, crystal evaluation technology has also been developed. For example, Electronic Materials, February 1981 issue (Vol. 20. A 2),
Published by Kogyo Kenkyukai Co., Ltd., there is a special feature titled ``Innovative side slope/process evaluation J,'' in which silicon crystal δ-1-valence technology is introduced.

(つ)発明の目的 本発明者らは、シリコンウェハ上の熱酸化脱の耐圧(絶
縁破壊電圧)を測定することによってシリコン結晶の評
価を行なうことができることを見出した。特に、熱酸化
膜の耐圧はシリコン結晶中に含有される重金属不純物(
例えば、Al、Na。
(1) Purpose of the Invention The present inventors have discovered that silicon crystals can be evaluated by measuring the withstand voltage (dielectric breakdown voltage) of thermal oxidation desorption on a silicon wafer. In particular, the breakdown voltage of a thermal oxide film is affected by heavy metal impurities (
For example, Al, Na.

Fe 、Cr +Ni 、Cu )等に影響されるので
、耐圧の測定から不純物けを推定することが本発明の目
的である。従来これら金属不純物を直接分析することは
放射化分析等で可能であるが時間と費用がかかシ、その
シリコンウェハを所定用途に用いることのできる結晶で
あるか否かを即時に判定することは困難であった。そこ
でシリコンウェハの所定用途での使用可否判定を容易に
できるようにするのが本発明の別の目的である。
It is an object of the present invention to estimate impurity emissions from the measurement of breakdown voltage. Conventionally, it has been possible to directly analyze these metal impurities using activation analysis, etc., but it is time-consuming and costly, and it is difficult to immediately determine whether or not the silicon wafer is a crystal that can be used for a specified purpose. was difficult. Another object of the present invention is to facilitate the determination of whether a silicon wafer can be used for a given purpose.

さらに、超LSI用に使用できるシリコンウェハとなる
C2法によるシリコンインゴットを製造する方法を提供
することも本発明の目的である。
Furthermore, it is another object of the present invention to provide a method for manufacturing a silicon ingot by the C2 method, which becomes a silicon wafer that can be used for VLSI.

に)発明の構成 上述の目的が、単結晶引上げ(CZ)法によって作られ
たシリコンインゴットから得られたシリコンウェハに熱
酸化による酸化膜を形成し、この酸化膜の耐圧(絶縁破
壊省1圧)を測定することによってシリコンウェハの結
晶を評価する方法を提供するととによって辻′成される
B) Structure of the Invention The above-mentioned object is to form an oxide film by thermal oxidation on a silicon wafer obtained from a silicon ingot made by the single crystal pulling (CZ) method, ) provides a method for evaluating silicon wafer crystals by measuring .

シリコンウェハの熱酸化は2回行なうのが好ましく、1
回目の熱酸化で形成した酸化膜を除去することによって
表面の影響を無くし、2回目の熱酸化による酸化膜にバ
ルク結晶の性質を反映さゼてその酸化膜の耐圧を測定す
るわけである。
It is preferable to thermally oxidize the silicon wafer twice, and once
By removing the oxide film formed by the second thermal oxidation, the influence of the surface is eliminated, and the properties of the bulk crystal are reflected in the oxide film formed by the second thermal oxidation, and the breakdown voltage of that oxide film is measured.

甘だ、本発明は、CZ法によるシリコンインゴットから
得られたシリコンウェハ上に形成した熱酸化膜の耐圧が
そのウェハでの多数の測定結果の耐圧と頻度との関係で
最高頻度の耐圧値である以上となるように、よシ高純度
のシリコン多結晶原料、ルツボ、ヒータおよびx UL
++気ガスを使用し、単結晶およびルツボの回転速度お
よび加熱冷却の温度プロフィルを適切に制御してシリコ
ンインゴットを製造する方法を提供することである、3
(3)発明の実施例 以下、本発明を実加態様例によってよりff’しく説明
する。
Too bad, the present invention is based on the fact that the withstand voltage of a thermal oxide film formed on a silicon wafer obtained from a silicon ingot by the CZ method is the most frequent withstand voltage value in relation to the withstand voltage and frequency of a large number of measurement results on that wafer. In order to meet the above requirements, we provide high-purity silicon polycrystalline raw materials, crucibles, heaters, and x UL
++An object of the present invention is to provide a method for manufacturing a silicon ingot by appropriately controlling the rotational speed of a single crystal and a crucible and the temperature profile of heating and cooling using gas.
(3) Examples of the Invention The present invention will now be explained in more detail with reference to additional embodiments.

酸化膜の耐圧測定が、例えば、次のように行なわれる。For example, the measurement of the breakdown voltage of the oxide film is performed as follows.

通常のCZ法によって作られた単結晶シリコンインゴッ
トをスライングし、て多数枚のシリコンウェハとし、各
ウェハをラッピング、ペリリング、ポリッシングしてシ
リコンウェハ製品にする。このシリコンウェハを加熱酸
化炉にて、例えは、1100℃、ウエト(98℃)、6
0分の条件で加湿酸化して600 nm厚の二酸化珪素
(Sin、)膜を形成する。この5i02膜をエツチン
グ゛によって除去する。次に、シリコンウェハを′p+
度加熱加熱酸化炉、例えば、1100℃、ドライ (塩
酸付加)、20分の条件で乾燥壌散酸化して5Qnm厚
のS+O,脛を形成する。このS i02膜上にアルミ
ニウム蒸着膜を形成し、ホトエツチング法にて多数の電
極パター/にする。このようにして形成した電極のそれ
ぞれに電圧(例えば、ラング電圧)を印加して絶縁?i
、@試験を行なって、当該電極の下にある5i02膜の
耐圧を測定する。
A single-crystal silicon ingot made by the usual CZ method is sliced into a number of silicon wafers, and each wafer is wrapped, perilled, and polished to produce a silicon wafer product. This silicon wafer is heated in a heating oxidation furnace, for example, at 1100°C, wet (98°C),
A 600 nm thick silicon dioxide (Sin) film is formed by humidified oxidation for 0 minutes. This 5i02 film is removed by etching. Next, the silicon wafer is
The material is dried and oxidized in a heated oxidation furnace, for example, at 1100° C., dry (hydrochloric acid added), for 20 minutes to form a 5 Q nm thick S+O. An aluminum evaporated film is formed on this Si02 film, and a large number of electrode patterns are formed by photo-etching. Is it possible to apply a voltage (for example, Lang voltage) to each of the electrodes formed in this way to insulate them? i
, @test to measure the breakdown voltage of the 5i02 film under the electrode.

シリコンインゴットのTOP側から得たシリコンウェハ
(A)およびTAIt[l+から得たシリコンウェハ(
B)の酸化膜(Sin、膜)の耐圧を前述したようにし
て測定すると、第1図に示す結果がaられる。第1図の
横軸に酸化膜耐圧(V)をとり、縦軸にその耐圧での頻
度に5・をとると、TOP側シリコンウェハは実線Aで
示され一方T A I L (jullシリコンウェハ
は破線Bで示される。図から明らかなようにTOP側ウ
ェハ(A)の頻度ピークがTAIL狽11ウェハ(B)
の場′合より高電圧側にある。
Silicon wafer obtained from the TOP side of the silicon ingot (A) and silicon wafer obtained from TAIt[l+
When the breakdown voltage of the oxide film (Sin film) of B) was measured as described above, the results shown in FIG. 1 were obtained. If we take the oxide film breakdown voltage (V) on the horizontal axis of Fig. 1 and the frequency at that breakdown voltage (5. is indicated by a broken line B. As is clear from the figure, the frequency peak of the TOP side wafer (A) is the same as that of the TAIL 11 wafer (B).
It is on the higher voltage side than in the case of .

それだけTOP側ウェハの耐圧が優わているわけである
。このことから、シリコンインゴットのTAIL側の最
も下から適当枚数(例えは、1〔幻毎にシリコンウェハ
を抜き取ってその酸化膜耐圧測定を行ない、第1図のよ
うなグラフにして耐IElj性能を判定し、ある所定レ
ベルの結果か措jられたならば、そのシリコンウェハよ
pTOP側にあるものは所定用途(例えは、超LSI用
)に使用できる。
The breakdown voltage of the TOP side wafer is that much superior. From this, we can extract a suitable number of silicon wafers from the bottom of the TAIL side of the silicon ingot (for example, one by one) and measure the oxide film withstand voltage. If the result is determined and the result is at a certain predetermined level, the silicon wafer on the pTOP side can be used for a predetermined purpose (for example, for VLSI).

シリコンウェハの熱酸化膜の耐F+、け、シリコン結晶
中に含1れる金属不純物(例えは、Cu HA ’ T
Na +Fe 、Cr 、Nt 1等)によって影響を
受けることが下記実験からも明らかである。
The F+ resistance of the thermal oxidation film of silicon wafers, metal impurities contained in silicon crystals (for example, Cu HA' T
It is also clear from the following experiment that the composition is affected by the following: (Na + Fe, Cr, Nt 1, etc.).

実験例 P型(100)シリコンウェハ(100m)を用意して
、これをドライ酸素(o2)雰11’l気中にて#’l
酸化して50nm厚さのS iOz膜を形成する。この
Sin、膜を通して金属不純物(銅)をイオン注入法に
よってシリコンウェハ内に導入する。このイオン注入を
加速電圧100KeVにてドーズ景をl X 10”c
m−2,5X 10′4z−およびl X J O”c
m−2+と変えて行なう。次に、Sin、膜をエツチン
グ除去してから、再度ドライ酸素(o2)雰囲気中にて
熱酸化して50nm厚さの810.膜を形成する。
Experimental Example A P-type (100) silicon wafer (100 m) was prepared and heated in a dry oxygen (O2) atmosphere of 11'l.
Oxidize to form a 50 nm thick SiOz film. A metal impurity (copper) is introduced into the silicon wafer through this Sin film by ion implantation. This ion implantation was performed at an accelerating voltage of 100 KeV, and the dose profile was 1 x 10"c.
m-2,5X 10'4z- and l X J O"c
Perform this instead of m-2+. Next, after removing the Sin film by etching, it was thermally oxidized again in a dry oxygen (O2) atmosphere to a 50 nm thick 810. Forms a film.

このS joy膜上にアルミニウム電極を形成して絶縁
破壊試験を行ガってStO,膜の耐圧を測定する。
An aluminum electrode is formed on this Sjoy film and a dielectric breakdown test is performed to measure the StO and withstand voltage of the film.

このようにして銅不純物に関しては第2図に示す結果が
得られる。シリコン結晶中の銅不純物が多いほど酸化膜
耐圧の良品率が低下する(すなわち、耐圧の低いものが
多い)ことがわかる。
In this way, the results shown in FIG. 2 regarding copper impurities are obtained. It can be seen that the higher the amount of copper impurities in the silicon crystal, the lower the percentage of non-defective oxide films with breakdown voltage (that is, the number of silicon crystals with low breakdown voltage) decreases.

以上のことからシリコンウェハの酸化膜の耐圧が高いは
どその結晶は金属不純物の含有月が少ないわけであり、
結晶の良否、すなわち、所定用徐に使用可能の結晶性を
有するかどうかの判定が耐圧の測定からできる。
From the above, the silicon wafer's oxide film has a high breakdown voltage, and its crystals contain fewer metal impurities.
The quality of the crystal, that is, whether it has crystallinity that can be used for a given purpose can be determined by measuring the withstand pressure.

さらに、酸化膜耐圧を向上させるために、すガわち、各
シリコンウェハでの耐圧と頻度との関係で最高頻度の耐
圧値をある値(例えば、9MV/+n)以上にするため
に、シリコンインゴットの製造において、よシ高純度の
シリコン多結晶原料、ノドツボ、ヒータおよび雰囲坏ガ
スを使用し、引上ける単結晶およびルツボの回転速度お
よび加熱冷却の温度プロフィルを適切に制御すればよい
、(7)発明の効果 上述したようにシリコンウェハ・の熱酸化膜の耐圧を測
定することによって容易にそのウェハが所定用途(超L
SIのi造用)に使用できる結晶であるかを判定するこ
とが可能になる。
Furthermore, in order to improve the oxide film breakdown voltage, in other words, in order to make the most frequent breakdown voltage value equal to or higher than a certain value (for example, 9MV/+n) in relation to the breakdown voltage and frequency of each silicon wafer, silicon In the production of ingots, it is sufficient to use a highly purified silicon polycrystalline raw material, a nodotsu pot, a heater, and a gas atmosphere, and to appropriately control the rotational speed of the single crystal to be pulled and the crucible, as well as the temperature profile of heating and cooling. , (7) Effects of the invention As mentioned above, by measuring the breakdown voltage of the thermal oxide film of a silicon wafer, the wafer can be easily used for a specified purpose (ultra-L).
It becomes possible to determine whether the crystal can be used for SI manufacturing.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、シリコンウェハの熱酸化膜の耐n−5と頻度
数との関係を示す線図であシ、 第2しIは、シリコンウェハ中の銅不純物ちと酸化膜耐
圧良品率との関係を示す線図である。 特許出願人 富士通株式会社 特許出願代理人 弁理士 青 木 朗 弁理士 西 舘 和 之 弁理士内田幸男 弁理士 山 口 昭 之 8151図 第2図 銅イオン注入量
Figure 1 is a diagram showing the relationship between the resistance n-5 of the thermal oxide film of a silicon wafer and the frequency number, and Figure 2 shows the relationship between the copper impurity level in the silicon wafer and the oxide film breakdown voltage non-defective rate. It is a line diagram showing a relationship. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Patent attorney Akira Yamaguchi 8151 Figure 2 Copper ion implantation amount

Claims (1)

【特許請求の範囲】 1、単結晶引上げ法によって作られたシリコンインゴッ
トから得られたシリコンウェハに熱酸化による酸化膜を
形成し、この酸化膜の耐圧を測定することによってシリ
コンウェハ・の結晶を評価する方法。 2、単結晶引上げ法によるシリコンインゴットから得ら
れたシリコンウェハ上に形成した熱酸化膜の耐圧がその
ウェハでの多数の測定結果の耐圧と頻度との関係で最高
頻度の耐圧値でちる値以上となるように、よυ高純度の
シリコン多結晶原料、ルツボ、ヒータおよび雰囲気ガス
を使用し、単結晶およびルツボの回転速度および加熱冷
却の温度プロフィルを適切に制御してシリコンインゴッ
トを製造する方法。
[Claims] 1. The crystal of the silicon wafer is obtained by forming an oxide film by thermal oxidation on a silicon wafer obtained from a silicon ingot made by the single crystal pulling method, and measuring the breakdown voltage of this oxide film. How to evaluate. 2. The breakdown voltage of the thermal oxide film formed on a silicon wafer obtained from a silicon ingot by the single crystal pulling method is greater than or equal to the highest frequency breakdown voltage value based on the relationship between the breakdown voltage and frequency of numerous measurements on that wafer. A method of manufacturing silicon ingots using high-purity silicon polycrystalline raw materials, a crucible, a heater, and atmospheric gas, and by appropriately controlling the rotational speed of the single crystal and crucible and the temperature profile of heating and cooling, so that .
JP24770583A 1983-12-29 1983-12-29 Evaluation of crystal of silicon wafer and preparation of silicon ingot Granted JPS60146000A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24770583A JPS60146000A (en) 1983-12-29 1983-12-29 Evaluation of crystal of silicon wafer and preparation of silicon ingot

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24770583A JPS60146000A (en) 1983-12-29 1983-12-29 Evaluation of crystal of silicon wafer and preparation of silicon ingot

Publications (2)

Publication Number Publication Date
JPS60146000A true JPS60146000A (en) 1985-08-01
JPH0234920B2 JPH0234920B2 (en) 1990-08-07

Family

ID=17167429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24770583A Granted JPS60146000A (en) 1983-12-29 1983-12-29 Evaluation of crystal of silicon wafer and preparation of silicon ingot

Country Status (1)

Country Link
JP (1) JPS60146000A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0487302A2 (en) * 1990-11-22 1992-05-27 Shin-Etsu Handotai Company Limited Method for testing electrical properties of silicon single crystal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5871636A (en) * 1981-10-23 1983-04-28 Toshiba Corp Evaluating method for semiconductor wafer surface cleanliness

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5871636A (en) * 1981-10-23 1983-04-28 Toshiba Corp Evaluating method for semiconductor wafer surface cleanliness

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0487302A2 (en) * 1990-11-22 1992-05-27 Shin-Etsu Handotai Company Limited Method for testing electrical properties of silicon single crystal
US5534112A (en) * 1990-11-22 1996-07-09 Shin-Etsu Handotai Co., Ltd. Method for testing electrical properties of silicon single crystal
US5688319A (en) * 1990-11-22 1997-11-18 Shin-Etsu Handotai Co., Ltd. Method for testing electrical properties of silicon single crystal

Also Published As

Publication number Publication date
JPH0234920B2 (en) 1990-08-07

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