JPS6014591A - Time switch - Google Patents

Abstract

PURPOSE:To attain direct writing of serial bit in memory without requiring a multiple converter and a separation converter by using a general purpose random access memory and using a controlling circuit consisting of a microprocessor etc. and some logic. CONSTITUTION:Date are converted between codecs CODEC-0, CODEC-1 by using RAM-0 as a medium. In the next period, data are exchanged between codecs CODEC-1, CODEC-0 in the same sequence by using RAM-1 as a medium. As writing and reading are made alternately for data memories RAM-0, RAM-1 at every period, data exchanged in delaying by just one period are inputted continuously to codecs CODEC-0, 1. Thus, the function of time switch can be realized by using a general purpose random access memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a time switch for exchanging input and output audio data of a codec in a time division switch.

[Background of the invention]

First, the conventional technology will be explained according to the drawings.

FIG. 1 is a block diagram of a time-division communication channel system using an example of a conventional time switch, and FIG. 2 is a flowchart of data exchange.

The output audio digital data of the codecs CODECU-LE that perform encoding and decoding are multiplexed in a fixed order in a multiplex converter MPX, and then temporarily stored in the memory in the switch T for one hour.

The accumulated audio data is sent to the separate converter DMP in a different order from the input order by external address control.
Sent to X.

By the way, such a time switch T is quite large and complicated, and requires special parts (for example, a non-general-purpose LSI).
etc.).

In the separate converter DMPX, codecs C0DECO~I
Separate the data corresponding to L and send it to each codec C0DE.
Input against Co-π.

For example, the data exchange between the CODEC CO., 10 and the CODEC C0DECo.
The data Do outputted from
Data D1 output from ODE C1 is sent to coach C
Sent to 0DECo. By exchanging voice data between the codecs in this way, it is possible to make calls between compatible analog lines.

However, in this conventional example, the multiplex converter M
p.sub.X, a separate converter MPX must be provided, and a time switch T, which cannot be constructed from general-purpose parts, is required, resulting in a considerable amount of hardware. It has been difficult to economically realize the provision of such hardware, especially in the case of a kamimatata device that handles only a few tens of rice grains.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and eliminate the need for multiple converters.

Another object of the present invention is to provide an economical time switch that can be constructed from general-purpose parts.

[Summary of the invention]

The configuration of the time switch according to the present invention is such that the data on the input highway, in which the digital output terminals of each codec are connected in full duplex manner, is written into one of a pair of data memories according to the write address designation. The data written in the other of the pair of data memories is read out on the output way that allows data to be supplied to the input terminal in full duplex mode according to the address specification, and the above writing and reading are kept constant. The data exchange unit alternately performs data exchange in cycles, and the address data given for reading the data memory is stored at ℃, and based on this, the part related to the time slot of the read address specification to the data exchange unit is stored. an address control section that performs designation, and generates each gate signal and synchronization signal for each of the above sections by counting the basic clock; and designation of a part related to data bits in the read address designation for the data exchange section; It also includes a counting section for specifying a fill-in address.

Note that this will be supplemented and explained below.

First, two rank access memories are prepared as data memory for the capacity of a pair of ingress and egress highways.
Set one random access memory in write mode and sequentially write data from multiple coaches, set the other random access memory in read mode, read data at the specified address, and send the output data to the corresponding coach. . This is repeated alternately every frame cycle.In other words, in the next cycle, the random access memory that has been in write mode is changed to read mode, and the data written in the previous frame cycle is transferred to the read mode. At the same time, the random access memory, which has been in read mode, is changed to write mode, and the data from the codec is written in the same manner as described above.

In this way, by alternately writing data into the two random access memories every frame period and switching to the read mode, the time switch function can be realized using only the memory function.

Therefore, by using a general-purpose random access memory without requiring a multiplex/separate conversion function, it is possible to realize an economical time switch with equivalent functions compared to the conventional example.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of one embodiment of the time switch according to the present invention, FIG. 4 is a various time chart thereof, and FIG. 5 is a flow diagram of the same data reading/writing.

Here, 1 is a line interface section, which is provided corresponding to, for example, analog lines 0 to 31, and consists of codecs C0I) EC-0 to EC-51 and their associated circuits; , an output highway 2B, and 3 is a data exchange unit related to a time switch.

Data memory RAM-0, 1, write data switching circuit 5F-o, read data switching circuit #6SF-
1 - consists of flip-flops 5R-0, 1 and address selectors 5EL-0, 1; 4 is an address control section, which includes address memories RAM-A, B;
and address information selector 5EL-A, B, address specification flick frontor 'FF0O~05, 10~1
5 and other related circuits, 5 is a counting section, 6 is a clock section, and 7 is a control section.

Note that the clock section 6 may be necessary for this time switch, but in many cases, it is common to the entire time division father exchanger and other clocks are required, so it is recommended that they be used. Good too.

Furthermore, the control unit 7 may be implemented in the same manner as the main time switch, for example by using a micro converter, and the desired function may be realized by using the central system of the 1-time division exchange and some functions of the 4J iron station. You can also do it.

Which of these matters is adopted essentially impedes the implementation of the present invention (but all are included in the technical idea of the present invention).

The operation of this time switch will be explained step by step based on FIGS. 6, 4, and 5. (1) Codec digital data input/output sequence First, the digital Input/output data Din, D,, Ll from input/output terminals and each quadruple clock based on 2.048 Mb/s (hereinafter, the basic one is referred to as 2M□ or 2A1.
So σ) tM and BM of 2x and 4x speed Q
cormorant. ).

Phase relationship between synchronization No. 46 5YNCO and 31? %4 diagram (α)
.

Even if it looks like fb+, let it be σ). Moreover, the cycle of each synchronization is about 125 μs, and within this cycle, 488rL# data f3bit is transferred to each coach C0D.
The input and output values for EC-○ to EC-31 are also σ].

Note that this 8-bit data is referred to as a time slot (hereinafter referred to as a time slot).

1" to treat it as TS).

This is the section after the data exchange section 6 has switched to the 1st road 5r-01C for the input highway 2A.

Data is periodically transferred to the data memory RAM for each 52 TS.
0 or sent to RAM-1 as input data. Its period is 125 μJ (1 frame cycle),
Each codec C0I)EC-.

This means that the output data I) OLLt of ~31 are sequentially sent to the data memory RAM-0 or RAM-1 at an interval of 125 μs.

That is, Figure 4 + AI is coached C0j) EC-0
The phase relationship between synchronizing signals 5YNCO~61 sent to ~31 is shown. The output data of is constant j
If the data overlaps in the organ sequence, it is sent to the data memory RAM-〇 or RAM-1.

(Input sequence to data memory RAM-0, t and AM-1 of each coach C0DEC-o to digital output terminal I of 61) Output data from o and t to data memory RAM-1
Gate signal G determines whether to send it to either 0 or RAM-1.
Determined by As shown in Fig. 4 σ), the gate signal G repeats 'E'c high level and lL' (low level) every cycle (32 TS minutes), so each codec C0
The output data of DEC-0 to DEC-31 is sent to data memory RAM-0 (gate signal G='H') in a certain cycle, and is sent to data memory RAM-1 (gate signal G='H') in the first cycle.
L”).

The write sequence in the data memories RAM-0 and RAM-IK is shown in FIG. This shows an embedded sequence.

If the data memory RAM-0 is in the write mode, the gate signal G-"B" is present.

The data of each coach C0DEC"0 to 31 enters the data input terminal Dt of the data memory RAM-00. At this time, the chip select terminal C5 of the data memory RAM-Q is connected as shown in FIG. 4 iC1. clock 2M,
Approximately 1227L, r for each data bit.
Become an enabler. In addition, the clock 2M, , 2M2
is generated and distributed by the clock generation circuit CLK of the clock section B. Since the enable signal FEZ is obtained by taking the logical sum condition of the 4U number of 2M2+AM from the logic unit 6 and the gate signal G, the enable signal FEZ is as shown in FIG. 4 iC1 while the gate signal G='H'. Approximately 60n for each data bit
The data memory RAM-0Y is write-enabled by s, and the data bits are stored in the data memory RAM-0.

In addition to writing each data bit into data RAM-0, the address signals AO to A9 are changed in phase with the data bits as a writing address designation.

That is, the address signals AO to A3, which are the part related to data bits in the write (- or read) address designation, are supplied from the counter CNT-o of the counting section 5, and are 8 data bits = 1 TS - about 6.9 μS. The address signals A4 to A9 change periodically, and the sequence is shown in FIG. 4 (di).
132 signals supplied from NT-1 and specifying each TS.
TS changes periodically at intervals of about 125 μs, and the sequence is shown in FIG. 4 111.

Due to the change in address signal AO-A9, data memory R
AM-0 includes rso's Cheetana 0,1-7 and TSL's datana 0,1-7. ..., and 1'S5A's Cheetana 0, 1 to 7. Data is written in this order. In this way, all data for 32 TS is written within one frame period at the same time.

The aforementioned gate signal G changes from H° to L''.

Therefore, the data memory RAM-0 has a coach C0.
Data from DEC-0 to DEC-31 is not pulled in, but data from codecs C0DEC-o to 31 is loaded into data memory RAM-1. On the other hand, the data memory RAM-0 has the above-mentioned write enable signal WEI at °H.
Therefore, it becomes -read mode. Data memory R
Similarly, for AM-1, when the gate signal is G-'L', the write mode is set, and when 40="H", the read mode is set.

(3) Convolution and read sequence of address memories RAM-A and RAM-B (5-1) Convolution data from the control unit 7 First, from the control unit 7 to the address memory RA of the address control unit 4
M-A can carry address data 2 and addressing specifications sent to RAM-B.

Address memories RAM-A and RAM-B.

Both address data and address specification (consist of S bit.
The output data from ~31 is stored in the data memory RAM-0-f or R with fixed addresses assigned to each.
Survived by AM-1.

Time slot TSO ~ 3141 Kochitsuku C0DE
It corresponds to C-0 to C-61, but also corresponds to the bit combination of data memory RAM=O and write address A4 to A9 of RAM-1 as the TS-related part of address specification for writing and reading. are doing. That is, TSO is A4, =A5 :A6 =A7 =A8
=A9 = 0- T S 1 is A4 == 1, A
5 =A6 =A7 =A8 =A9 = 0. ...
, and TS5A is A4=A5=A6=A7=A8=
1, A9=0.

The correspondence relationship between the bit combinations of the above SSO to TS31 and address bits A4 to A9 is stored in the control unit 7. - For example, Kochitsuk CODEC-0, C0DE
When exchanging data between C-1, the controller 7 sends the address terminal J4 of the address memory RAM-A or RAM-B.
AO to AA5 and data terminal Dino -Din5 (
Do ~I)s) Data pi)D to the address as shown below.

~D5 shall be planted.

7)'L/S: J4AO= #1=AA2
=AA3iAA4. =AA5-〇 (same as above) ヲ(3-2) Write sequence of address memories RAM-, 4, RAM-B Address memories RAM-A and RAM-B are controlled by the control unit 7
written from the data memory RAM-0 case or RAM
-1 is read out when in read mode.

Regarding the address memory RAM-, 4, the control unit 7
The writing may be performed if (No.N A3/G is lL)
This is the case of l. In other words, this is the case when gate signal G is °H" or °L" and address bit A3 is °L'. When the gate number G is °H', (as mentioned in 3-2), the data memory RAM-D is in the write mode, and the data memory RAM-00 address terminals A4 to
Address memory RAM-A connected to A9 via selector 5EL-0 is also in write mode.

When gate number G is °L°, data memory RAM
-0 is the read mode, but the address bit signal A
3,91μ3, which is one cycle of 6 (Fig. 4 fdl diagnosis)
The address memory RAM-A is in the write mode except during the period 48871J when A5='H', so that writing from the control unit 7 can be performed at any timing over almost the entire time.

Further, when the signals A3 and G signals are °E'', the signals A3 and G are sent to the control unit 7 so that the control unit 7 does not perform an invalid write-in. Address terminals AAO to AAO of the address memory RAM-A Selector 5EL-A connected to A/45
When signal A6・G is l Ll, CA) 9JJJ,
That is, the address designation from the control section 7 is taken in, and when the signal A3.G is .degree.H.degree., the address signal from the one on the (B) side, that is, the counter CNT-1 is taken in.

Regarding address memory RAM-H, by simply changing the signals A3 and G to signals A3 and G, the address memory RAM-H
- Same as case A.

In this way, the control unit 7 can perform, for example, the above (3-1).
data as shown in the example of il+, (Ill) can be written to both address memories RAM-A and RAM-H.

(3-5) Address memory RAM-A, RAM'-B
First, the case of address memory RAM-A will be described. In address memory RAM-A, signal A3-G
or IBL, the light switch signal V/E or °H”
and becomes the read mode, and the select signal C
When the voltage reaches 5°L', the data output terminal of address memory RAM-A is activated. , LtO~5, data is output. The data output from the address memory RAM-A at the falling edge of the signal A3 is stored in the free lag flop FF0ONFF05.

Regarding the address memory RAM-H, similarly, in the case of the signal A3.G or R', data is outputted and stored in the free lag flops FF10 to FF15 at the falling edge of @A3.

(4) Data memory RAM-0, RAM-10 read sequence (4-1) Address specification when reading data memory RAM-[1, RAM-1 First, the read sequence of data memory RAM-〇 will be explained based on 151JK. .

As mentioned above, in the data memory RAM-00 read mode, the address memory RAM-A receives the signal A.
6. When G is 'H', the data written from the control unit 7 is read out and the flip-flops FF0O to FFO5 are read out.
is accumulated at the falling edge of signal A3. This is at the same time as the data memory I) RAM-0 has just finished reading the data of TS31 (time A in Figure 5).

After the data memory RAM-00 write sequence,
The explanation will be given again starting from the beginning of the read sequence.

When the data memory RAM-0 is in the heave-out sequence, the gate signal is G-'L''.

The CB side of the selector 5EL-o connected to the address terminals A4 to A9 of the data memory RAM-00, that is, the output of the flip-flop FF 00 P-05, is taken into the data memory RAM-QVc as an address bit.

(4-2) Data memory RA/-0, RAM"1 read sequence timer: '-f C0Db'C-0, C0DEC-
As an example, if data is to be exchanged between two devices, the data (■
), σ1 is assumed to be included.

The meaning of data + Il is that, for example, data corresponding to address VcTs1 of address memory RAM-A corresponding to TS31 is written in address memory l) RAM-, 4, and the meaning of data hit is equivalent to rsa. The data corresponding to TSo is written to the address of the address memory RAM-A in the address memory RAM-AK. That is, as shown in Figure 5, at time A
address memory RAM −A (7,) T
The data of S1 Aisho is T in data memory RAM-0.
The meaning of the above fIl indicates that the data is equivalent to SO, and similarly, the address memory RA at time B
The data corresponding to the TSO of M-, 4 is stored in the data memory RAM-
The meaning of the above is to indicate that the data corresponds to TS1 of 0.

In data memory RAM-0, when the address of TSl is given when reading the first 8-bit data, the data at the address of TSl that was previously committed is stored in the first F3bi.
The data is sent from the data memory RAM-0 to the coach truck 01ll (output highway 2B) as data. Next Q b
If you give the TSO address when reading it data, the data at the 7'SO address written in the previous IC will be stored in the data memory RAM as the next 8-bit data.
- From 〇 Kochitsuku 9Allf, Deno Iway 2B)
sent to.

FIG. 4 (yl indicates the sequence of data output from the data memory RAM-0, Z)0,
4, DIA, D2A, D5A,...
Output data from data memory RAM-0, DoB,
DlB.

D2B, D3B, . . . are data after being punched out by the clock 2M by the flip-flop 5R-0 of the data exchange unit 3, DO, Dl, D2, D
3.

. . . is data after being punched out by clocks 2M and K in the first-stage Frisobufu 5R-1, and these data are directly sent to each codec C°01)EC-o~
31 digital input terminal DL71. Enter.

The first 8 btt data output from the data memory RAM-0 are input to the codec C0DEC-0 according to the AND condition with the gate signal GO (see fA+ in Figure 3), and similarly the 9th order 13 btt data is Gate/signal G1 (
It is input to the codec C0DEC-1 according to the AND condition with FIG. i.e. codec CQ
Data output from DEC-0 is stored in data memory RAM
- After being once absorbed into 0, Kochitsuku C'0DEC-
The data output from the coach C0DEC-1 is once loaded into the data memory RAM-0 and then output to the codec C0DEC-o.

As described above, data is converted between coaches C0DEC-0 and C0DEC-1 using data memory RAM'-0 as a medium. In the next cycle (125 μ3), the odor sensor uses the data memory RAM-1 as a medium in the same sequence to connect the controller C0DEC-1, C0I) EC-o to T f
- Data memory RA is exchanged every 1 cycle.
Note that M-o and RAM-1 are read and written alternately, C0DEC-0 and 1.
For jC, the data exchanged after exactly one cycle is continuously input.

In this way, the function of a time switch can be realized using a general-purpose random access memory, but the data exchange conditions between each codec C0DEC-0 to C0DEC-31, ie, coach c.

Connection pattern between DEC-N and CODEC-M (N to M
, N, M==0.1,2. . . , 31) is both arbitrary and busy, and it is clear that it is possible to establish a connection between Kochikku C0DEC-N and CC01) EC- by receiving a selection signal in the same way as a general exchange. be.

Note that in the above embodiment, the address memory RAM-A
, B are provided corresponding to the data memory RAM-υ, 1, but this is for the convenience of explanation and to facilitate understanding, and it is not intended in the present invention to provide only one independently and switch between them. does not interfere. In other words, the address memory is not necessary when writing to the data memory RAM-0, RAM-1 because the address specification (part related to the time slot) 7al- can be performed when reading the data memory RAM-0, 1. ,
It is possible to make the necessary preparations during that time.

Furthermore, although this embodiment shows the exchange of 62 lines, the present invention is not limited to this.

If high-speed random access memory is used, data exchange over about 60 lines, which is about twice that amount, can easily be performed. From this, especially in the case of small capacity lines such as private branch exchanges,
It becomes an extremely effective special switch.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a time switch can be constructed using a general-purpose random access memory, a control circuit consisting of a microprocessor, etc., and some logic. This eliminates the need for a multiplex converter and one separate converter, and allows the serial bits to be written directly to memory, resulting in an extremely inexpensive time switch. A remarkable effect can be obtained in economicalization of capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a time-division communication system using an example of a conventional time switch, a flowchart of its data exchange, and FIG. 3 is a block diagram of an embodiment of a time switch according to the invention. %Figure 4 shows the various time charts - Figure 5 shows the
It is a flowchart of the same data read/write. 1... Line interface section 2... Highway 3... Data exchange section 4... Address converter) 0-ru section 5... Counting section 6... Clocking section 7 - Control section

Claims (1)

[Claims] t Write the data on the input highway in which the digital output terminals of each coach are connected in full duplex to one of the pair of data memories in accordance with the write miatres designation;
The data written in the other of the pair of data memories is read out according to the read address specification, and the data written in the other of the pair of data memories is read out onto the output highway which is arranged so that data can be supplied in full duplex to the digital input terminal of each of the codecs. The data exchange section is pressurized to perform writing and reading alternately at a constant cycle, and the address data given for reading from the data memory is stored τ, and based on this, the data exchange section is read out. By counting the basic clock and the address control section that specifies the time slot related part of the address specification,
A time switch comprising a counting section that generates each gate signal and synchronization signal for each of the above sections, and also specifies a part related to data bits in the read address specification for the data exchange section, and also specifies a write address. 2. In the item described in claim 1. The data exchange unit is a time switch configured using a general-purpose random access memory as its data memory.