JPS60145726A - Logic circuit - Google Patents

Abstract

PURPOSE:To set freely the number of input terminals and the number of output terminals by selecting wiring among terminals used as input or output terminals, internal logic circuits, and selecting parts connected to buffer circuits provided between them by selecting circuits. CONSTITUTION:A device consists of plural bit lines 3, word lines 11 and 12 used as input or output lines, buffer circuits 8 and 9 performing inverter operations, terminals 30 used as input or output terminals, selecting parts 10 each of which has the terminal 30 as an input of output terminal and consists of 4 diodes 20, 21, 22, and 23, and selecting circuits which determine to select terminals 30 as input or output terminals. If the terminal 30 is used as the input terminal, fuses 21 and 23 are cut. In this case, buffer circuits 8 and 9 are used as input circuits. If the terminal 30 is used as the output terminal, fuses 20 and 22 are cut. In this case, buffer circuits 8 and 9 are operated as an output circuit and a feedback circuit respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (11) Technical Field of the Invention The present invention relates to a logic circuit, and more particularly to a circuit such as a programmable logic array circuit which has a plurality of input terminals and output terminals and whose internal logic is programmable.

(2) Prior Art and Problems In a circuit with programmable internal logic such as a PLA, if the internal logic of the circuit is programmed, a desired output signal can be obtained using a plurality of input signals.

As shown in FIG. 1, the PLA consists of a two-stage array section consisting of a plurality of word lines 1.2 and a plurality of bit lines 3 intersecting with the word lines 1. There is a word line 2 as an output line.

Generally, in the previous stage, a word line 11 of the same logic as the input signal applied to the input terminal 5 is connected by a buffer in the input circuit 4, or a word line 12 of the opposite logic to the word line 11 is connected to a diode or the like by an inverter of the input circuit 4. By connecting to the pinto line through
A logical AND signal consisting of the logical value of is generated on the bit line 3. In the latter stage, by connecting the bit line 3 to the word line 2 as an output line through a diode, etc., the signal of the logical sum of the logical values of the connected bit line 3 is transmitted to the word line 2.
is output to. In other words, a signal obtained from a sum-of-products logical expression composed of the same or opposite logic as the input signal is generated on the word line 2 as an output line. A signal is output from this word line 2 through an output circuit 6.

In this circuit, the input terminals used for signal input and the output terminals used for signal output are determined at the time of manufacture. If more output terminals are required than the specified number of output terminals, the circuit cannot be used, and the only way is to always use input terminals and output terminals that each satisfy the required number.

(3) Purpose of the Invention The purpose of the present invention is to solve the above-mentioned problems and to select a buffer circuit provided between a terminal used as an input terminal or an output terminal and an internal logic circuit to function as an in-cover sofa or an out-cover sofa. One object of the present invention is to provide a logic circuit that allows a user to determine a terminal as an input terminal or an output terminal.

(4) Configuration of the Invention A terminal used as an input terminal or an output terminal, an internal logic circuit, a buffer circuit provided between the terminal and the internal logic circuit and serving as an in-cover sofa or an out-cover sofa, and the terminal a selection unit connected to the internal logic circuit and the input side and output side of the buffer circuit; - connected to the selection unit, selecting and determining the selection unit so that the buffer circuit becomes an input cover sofa or an output cover sofa; This is achieved by providing a selection circuit with this function.

(5) Embodiment of the invention FIG. 2 is a circuit diagram for explaining an embodiment of the invention. A PLA that allows you to determine which terminal is used as an input terminal or output terminal while referring to this diagram.
The circuit will be explained.・As shown in the figure, this circuit includes a plurality of bit lines 3, word lines 11 and 12 used as input lines or output lines, a buffer circuit 8°9 that performs inverter operation, and an input terminal or output terminal used as an output terminal. terminal 3
0 and four diodes 20, 21, 22, and 33 with terminal 30 as an input terminal or an output terminal.
．． and a selection circuit (not shown) that partially disconnects the diode of the selection section 1o and selects and determines whether the terminal 30 is an input terminal or an output terminal.

If terminal 30 is used as an input terminal, use fuses 21 and 23.
cut. At this time, buffer circuits 8 and 9 that perform inverter operation operate as input circuits.

In addition, when terminal 30 is used as an output terminal, fuse 2
Cut 0.22. At this time, the buffer circuit 8 operates as an output circuit, and the buffer circuit 9 operates as a feed buffer circuit and a buffer circuit for filtering. This feed hack buffer circuit uses the output signal obtained from the output circuit as an input signal. This is a buffer circuit.

FIG. 3 is a circuit diagram for explaining a selection circuit that selects and determines the selection section 10. In the figure, 4o is a selection circuit, 50 is a power supply voltage (Vcc) connecting line, and 51 is a grounding line.

For example, a method of cutting the fuses 21, 2.3 of the selection section 10 to use the terminal 30 as an input terminal will be described below. First, make it possible to cut the fuse (04 child 60
Low level of TL level (approximately 0 to 0.8v),
When both signal terminals 61 and 62 for selecting a fuse are set to low level, transistors Q6 and Ql''
I is off, Ql and Ql4. turns on.

Next, when a fuse cutting current flows from terminal 63, this current flows through transistor Q14. Diode DZ.

Since the current flows through the fuse 21 and the transistor Qr7, the fuse 21 is cut off.

Further, in the above description, when both signal terminals 61 and 62 are set to a high level (approximately 2 to 5 V), the fuse 23 is disconnected. In this way, which of the four diodes 20, 21, 22.23 of the selection section 10 is cut is determined by the signal level applied to the signal terminal 61.62.
The relationship between the signal level added to 1.62 and the fuse to be cut is shown in the table below. In the table, the signal level applied to the signal terminal 61 is S1, and the signal level applied to the signal terminal 62 is S2.
The TTL level is set to below level, and the high level of the TTL level is set to I].

When this fuse is cut, particularly when the fuse 20 or 21 is cut, the fuse cutting current flows into the output stage transistor of the buffer circuit 8 which performs an inverter operation, and there is a possibility that the transistor may be destroyed. Therefore, the output signal line of the buffer circuit 8 is set to a high impedance state when the fuse is cut. This buffer circuit 8
is shown in Figure 4. In the figure, 50 is a power supply voltage (Vcc) line.

51 is a ground line, 71 is an input signal line, and 72 is an output signal line.

In this FIG. 4, the terminal 70 is connected to a TTL level low
When the level is set, transistors Qzz and Q2B are turned off, and the output signal line 72 becomes a high impedance state. Further, by keeping the terminal 70 at a high level of TTL level, this sofa circuit operates as an inverter.

As described above, in the PLA circuit shown in FIG.
buffer circuit 8.9.
can be used as an input circuit or an output circuit and a feed hack buffer circuit, and the terminal 30 can be used as an input terminal or an output terminal. In other words, the user of this PLA circuit can freely set the number of input terminals and the number of output terminals, and the usable range of one circuit is widened.

In this embodiment, a PLA circuit has been described, but the present invention is not limited to a PLA circuit, but includes an internal logic circuit having wiring that can be used for input/output, an input cover sofa, an output buffer, an input terminal or an output. Any logic circuit may be used as long as it has a terminal that can be used as a terminal. Furthermore, the selection section is not limited to one consisting of a diode;
Any wire that can be disconnected or connected by disconnecting or short-circuiting may be used.

(6) Effects of the Invention According to the present invention, a terminal used as an input terminal or an output terminal, an internal logic circuit, and a selection unit connected to a large cover sofa or a large cover sofa provided between them or a large cover circuit serving as an output buffer. By wiring selectively using a selection circuit, a terminal can be determined as an input terminal or an output terminal, so the number of input terminals and output terminals can be set freely, instead of the conventional number of input terminals and output terminals determined at the time of manufacturing. Compared to when there is
It becomes a logic circuit that can be used in a wide range of applications. Further, since one buffer circuit is used as an input buffer sofa or an output buffer sofa, it is more rational than preparing two buffers, an input buffer and an output buffer.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram for explaining a conventional PLA circuit, FIG. 2 is a circuit diagram for explaining a PLA circuit according to the present invention, and FIG. 3 is a circuit diagram for explaining the operation of a selection circuit according to the present invention. 4 are buffer circuit diagrams of the in-cover sofa or the out-cover sofa of the present invention. In the figure, 1 is a word line as an input line, 2 is a word line as an output line, 3 is a bit line, 4 is an input circuit, 5 is an input terminal, 6 is an output circuit, and 7 is an output terminal. 8.9 is a buffer circuit, 10 is a selection section, 11.12 is a word line, 20.21, 22.23 are fuses, 30 is a terminal used as an input terminal or an output terminal, 4 is a selection circuit, 50 is a power supply Voltage (Vcc) line, 51 is a grounding line, 60 is a signal terminal that allows the fuse to be cut, 61, 62 is a signal terminal that determines which fuse to cut, 63 is a terminal that flows the fuse cutting current, 70 is a buffer circuit 71 is an input signal terminal, and 72 is an output signal terminal.

Claims (1)

[Claims] A terminal used as an input terminal or an output terminal, an internal logic circuit, a buffer circuit provided between the terminal and the internal logic circuit and serving as an input or output buffer, the terminal, the internal logic circuit, and the buffer circuit. A selection section connected to an input side and an output side of a buffer circuit, and a selection circuit connected to the selection section and having a function of selecting and determining the selection section so that the buffer circuit becomes an input cover sofa or an output cover sofa. A logic circuit characterized by: