JPS60145630A - Manufacture of submounting member - Google Patents
Manufacture of submounting memberInfo
- Publication number
- JPS60145630A JPS60145630A JP162184A JP162184A JPS60145630A JP S60145630 A JPS60145630 A JP S60145630A JP 162184 A JP162184 A JP 162184A JP 162184 A JP162184 A JP 162184A JP S60145630 A JPS60145630 A JP S60145630A
- Authority
- JP
- Japan
- Prior art keywords
- submounting
- submount member
- submount
- bonded
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
イ、産業上の利用分野
本発明は、半導体素子を直接パッケージの半導体素子マ
ウント部に取付ける代わ、？に％半導体素子と素子マク
ント部の間に介在させて、放熱特性の向上、あるいは、
熱歪の緩和などを図るために用いる、サブマウント部材
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention provides an alternative to directly attaching a semiconductor element to a semiconductor element mounting portion of a package. % between the semiconductor element and the element part to improve heat dissipation characteristics, or
The present invention relates to a method of manufacturing a submount member used to alleviate thermal strain.
口、従来技術
従来の半導体素子をサブマウント部材に取り付ける方法
の１つは、サブマウント部材本体ケ加熱し、その上に融
着材片をのせて溶かし、そこに半導体素子をのせてから
冷やして固定する方法である。この方法では、融着材か
サブマウント部材本体表面で一様に廷びず、半導体素子
を載せたとき、融着が不均一になるため熱抵抗が大きく
なるという欠点や、融着材が半導体素子端面にはい上か
り、リーク不良を起こしやすいという欠点があった。Conventional technology One of the conventional methods for attaching a semiconductor element to a submount member is to heat the submount member itself, place a piece of adhesive material on top of it, melt it, place the semiconductor element there, and then cool it down. This is a method of fixing it. With this method, the fusing material does not spread uniformly on the surface of the submount member main body, and when a semiconductor element is mounted, the fusing becomes uneven, resulting in high thermal resistance. It has the disadvantage that it crawls onto the end face and tends to cause leakage defects.
これらの欠点を改善するため、融着材を蒸着によって均
一にサブマウント部材本体に付け、そのサブマウント部
材に半導体素子を載せて加熱し、融着するという方法が
行なわれている。融着材としては始めＩｎが使用されて
いた。これは加熱して融着するため、ｒｄｉ漸後冷やし
たときに歪が加わるが％ Ｉｎはやわらかいため、半導
体素子とサブマウント部材の間のＩｎが歪を吸収し、半
等体水子に加わる歪を小さくするというオリ点があるた
めである。In order to improve these drawbacks, a method has been used in which a fusing material is uniformly applied to the submount member main body by vapor deposition, a semiconductor element is placed on the submount member, and the semiconductor element is heated and fusing is performed. Initially, In was used as the fusion material. Since this is heated and fused, strain is added when it is cooled after RDI, but % In is soft, so the In between the semiconductor element and the submount member absorbs the strain, and it is added to the semi-isomorphic water element. This is because the objective is to reduce distortion.
しかし、Ｉｎは融点が低く、機械的強度も低いため、も
っと機械的強度の高いａｎ 、 ＡｕＳ ｎ 、 Ｐｂ
８ｎ 。However, since In has a low melting point and low mechanical strength, it can be used with an, AuS n, and Pb, which have higher mechanical strength.
8n.
Ｐｂ８ｎＡｇ など全融着材として使用し、サブマウン
ト部材にはダイヤモンド、Ｓｉなど、熱膨張糸数が半轡
体素子に近い材料を使うことによって歪を小さくすると
いう方法が行なわれている。特に。A method has been used in which distortion is reduced by using Pb8nAg as a total bonding material and using a material such as diamond or Si for the submount member, which has a thermal expansion thread count close to that of the half-body element. especially.
ＡｕＳｎ 、Ｐｂ８ｎＡｇなどの共晶合金は、機械的強
度が高く、よく使われている。ところが、ＡｕＳ口。Eutectic alloys such as AuSn and Pb8nAg have high mechanical strength and are often used. However, the AuS mouth.
ＰｂＳｎＡｇ など共晶合金を蒸着する際に問題点があ
る。蒸着では蒸着ソースを抵抗加熱（ヒータ）や電子線
を当てることによって加熱して飛ばすが、このとき、ヒ
ータや蒸着ソースからの輻射熱が被蒸着物であるサブマ
ウント部材本体へ伝わる。There are problems when depositing eutectic alloys such as PbSnAg. In vapor deposition, the vapor deposition source is heated and blown away by resistive heating (heater) or electron beam application, and at this time, radiant heat from the heater and vapor deposition source is transmitted to the submount member body, which is the object to be vaporized.
蒸Ｎは圧力がｌＸｌ０ Ｔｏｒｒ以下の真を中で行なわ
れるため、サブマウント部材から蒸着基板への熱伝害が
悪く、この輻射熱によってサブマウント部材本体が加熱
され、長時間蒸着を続けるとサブマウント部材本体に付
いた蒸眉拐料が溶けてしまう。ここで、蒸着材料として
ＡｕＳ口、Ｐｂ８ｎＡｇなどの合金の融層材を使用する
と、サブマウント部材本体に付い７ｃ融屑材か浴すサプ
マウント都口本体や１表面に付りた金りと反応して、融
層伺の組成が変化してしまう。そのため１合金の）鶴沼
拐紫蒸着するときは、サブマウント部刊本体に一度や１
いた１担層材゛が浴けないように％少し融着材を蒸着し
たら、サブマウント部材本体が冷えるまで待ち、それか
らまた＃漸するということを繰り返して蒸着しなけれは
ならない。特に融屑拐とし７て便うためには、２μｍ以
上の厚さが性交であり、これを前記のような方法で少し
ずつ付りると％蒸着に数時間以上の長い時間か必要でお
る。また、融着材が付いている部分はリード物のボンデ
ィングができないので、サブマウント部材の表聞＆’ｊ
リード線をボンティングする必要がるる楊＠′、融Ｎ
伺をサブマウント部材の表口に選択的ンこ付りなりれは
ならない。そのため、蒸着の際はサフマッント郁材本＄
＋奮肌則的に並べ、その上にマスフケ合わせ′を癌漕す
るという作業が必硬でめる。′また、蒸着で１″１．、
融７ｆ材料が必要ないｎｌへもフ団んでし１うため、本
機に必要な知よす叡十倍から数白倍の融着材料が必要で
ある。Since evaporation of nitrogen is carried out under pressure of less than l The steaming agent attached to the main body of the component will melt. Here, if a melt layer material of an alloy such as AuS or Pb8nAg is used as a vapor deposition material, the melted waste material attached to the submount member body will react with the metal attached to the submount body and the surface of the submount member. As a result, the composition of the melt layer changes. Therefore, when depositing Tsurunuma (alloy 1), it is necessary to deposit it once or once on the submount body.
After depositing a small amount of the fusion material so as not to expose the carrier material, it is necessary to wait until the main body of the submount member cools down, and then repeat the process again. In particular, in order to be useful as a melting debris, a thickness of 2 μm or more is required, and if this is applied little by little using the method described above, it will take a long time of several hours or more for evaporation. . Also, since it is not possible to bond the lead material to the part where the adhesive is attached, it is necessary to
It is necessary to bond the lead wires.
The cover must not be selectively attached to the front surface of the submount member. Therefore, during vapor deposition, use
＋It is very difficult to arrange the dandruff in an orderly manner, and then add the mass dandruff mixture on top of it. 'Also, 1"1. by vapor deposition.
Since the fused 7f material is also included in the NL, which does not require it, the amount of fused material required for this machine is ten to several times greater than that required for this machine.
ハ１発明の目的
本発明の目的は、蒸着法によるような、長時間を要し、
かつ、融着材の使用量も、実際に被着される量よりも数
十ないし数白−倍多く費消するという欠点を解決し、所
望の形を有し、均一厚さに融着材が被着されたサブマウ
ント部材の製造方法を提供するにある。C1 Purpose of the Invention The purpose of the present invention is to reduce
In addition, it solves the disadvantage that the amount of adhesive used is several tens to several times more than the amount actually applied, and the adhesive can be used in a desired shape and with a uniform thickness. The present invention provides a method of manufacturing a submount member.
二０発明の構成
本発明によれば、融層材を所望の形および厚さに構成し
ておき、これをサブマウント部材本体に加熱圧着して被
着するサブマウント部材の製造方法が得られる。20 Structure of the Invention According to the present invention, there is provided a method for manufacturing a submount member, in which a fusing layer material is formed into a desired shape and thickness, and the material is heat-pressed and attached to the main body of the submount member. .
ホ、実施例 つぎに本発明を実施例により説明する。E, Example Next, the present invention will be explained by examples.
第１図は本発明の一実施例方法にょｐ製造したサブマウ
ント部材の余［ａ図である。第り図において、シリコン
ウェーハ１（ｌａは細片）の表面及び裏ｍＫＴｉ−Ｐｔ
［ｇ２及Ｕ３’に付け、 それがら、このクエーハ１
［定の大きさに切ると、第１図の融着材４を付ける前の
サラマウント部伺本俸となる〇一方％融着材４は、Ｐｂ
８ｎＡｇを引き沖はして）享さ３μｍの箔とし、それを
型で打抜いて得られる。FIG. 1 is a diagram showing the remainder of a submount member manufactured by a method according to an embodiment of the present invention. In the figure, the front and back sides of a silicon wafer 1 (la is a strip) are mKTi-Pt.
[Added to g2 and U3', and this Quaha 1
[If cut into a certain size, the actual size of the Saramount section before attaching the adhesive material 4 shown in Figure 1 will be obtained.〇On the other hand, the adhesive material 4 is made of Pb
It is obtained by drawing 8nAg into a foil with a thickness of 3μm and punching it with a die.
上記の型で打抜いたＰｂＳｎＡｇ箔４を、前に述べたシ
リコンのサブマウント部伺本体の表面の所定の位ｔ装置
き、ＰｂＳｎＡｇが溶けない程度に加熱し、同時に上か
ら圧力を加えると％第１図のサブマウント部材が得られ
る。このとき、融着材４は、サブマウント部材の移動の
とき、及びザブマウント部材に半轡体素子を取り付ける
作業のとき、取れた９位負がずれたりしない程度に付い
ていれはよい。The PbSnAg foil 4 punched out with the above mold is placed in a predetermined position on the surface of the main body of the silicon submount part described above, heated to an extent that the PbSnAg does not melt, and at the same time pressure is applied from above. The submount member shown in FIG. 1 is obtained. At this time, the fusing material 4 should adhere to the extent that the removed 9th position does not shift when moving the sub-mount member and when attaching the half body element to the sub-mount member.
第２図は上の実施例と同もｋのシリコンウェーハｌに、
シリコンウェーハを切る前に、融沼材ＰｂｓｎＡｇ５奮
貼ジ付けたものである。この場合、菊にしたＰｂ８ｎＡ
ｇ ｆ Ｉ）ボン状に所定の１１ノに切ハそれをシリコ
ンウェーハｌの表聞の所定の位油４ｃ載せ１、ｐ ｂ
８ ｎ Ａ ｇ が浴けないａ度に加熱しｌがら上がら
圧力會加えて融層材４を貼ジ付ける。そして、その融層
材を付け／ζシリコンウェーハを切ル「してザブマウン
ト部材を得ることができる。この場合。Figure 2 shows the same silicon wafer l as in the above embodiment.
Before cutting the silicon wafer, a PbsnAg5 adhesive was applied. In this case, Pb8nA made into chrysanthemum
g f I) Cut a predetermined 11 holes into a bong shape and place it on a silicon wafer l by a predetermined amount of oil 4c 1, p b
8 n A g is heated to a degree such that it cannot be exposed to water, and pressure is applied while rising, and the fusing layer material 4 is pasted. Then, by applying the fusing material and cutting the ζ silicon wafer, a submount member can be obtained. In this case.
同じ形に融着材を貼り付けたシリコンウェーハから切断
する位置を変えることによって、第３図、第４図の形や
これ以外にも異なる形のサブマウント部材を得ることが
できる。By changing the cutting position from a silicon wafer having the same shape but with a bonding material attached, it is possible to obtain submount members having the shapes shown in FIGS. 3 and 4 and other shapes.
第５図は、シリコンウェーハｌに融着材を付けるもう一
つの方法を示す断面図である。あらかじめ、融着材Ａｕ
Ｓ口６は、直径３０μｍ程度のワイヤ状に引き伸ばしで
ある。このＡｕ８ｎワイヤ６を、表面に’ｌ’１−ＰＬ
電極を付けた台８の上のシリコンウェーハｌの上に所定
の間隔で平行に並べる。FIG. 5 is a cross-sectional view showing another method of attaching a fusion material to a silicon wafer 1. FIG. In advance, the fusion material Au
The S opening 6 is a wire-shaped wire with a diameter of about 30 μm. This Au8n wire 6 is placed on the surface of 'l'1-PL.
The wafers are arranged in parallel at predetermined intervals on silicon wafers l on a table 8 with electrodes attached.
ＡｕＳｎが溶けない程度に加熱し、その上を第５図のよ
うに、ＡｕＳロワイヤの長さ方向にローラ７をころがし
、Ａｕ８ｎワイヤを押しつぶすことによって、第２図の
ようなＡｕＳｎ箔５が付いたシリコンウェーハが得られ
る。後は前記の実施例と同様に切断してサブマウント部
材が得られる。The AuSn foil 5 is attached as shown in Fig. 2 by heating the AuSn to such an extent that it does not melt, and rolling the roller 7 over it in the length direction of the AuS wire as shown in Fig. 5 to crush the Au8n wire. A silicon wafer is obtained. After that, the submount member is obtained by cutting in the same manner as in the previous embodiment.
へ０発明の効果
以上述べたように、本発明の方法によれは、希望の厚さ
、形で均一な融層材が付いたサブマウント部材を、盛着
法によらないで作ることができる。Effects of the Invention As described above, by the method of the present invention, it is possible to make a submount member having a uniform fusing layer material of a desired thickness and shape without using a deposition method. .
また、上に述べた実施例の他に、材料ケシリコンの代わ
りにダイヤモンド、 ＧａＡｓ 、アルミナ、ベリリア
、ＳｉＣなどにすることができる。また、シリコンウェ
ーハ表、晟■の金楓奄極は必要に応じて有るものも無い
ものも作ることができる。融着材には、実施例で述べた
。 Ｐｂ８ｎＡｇ 、 ＡｕＳｎ以外にも、Ｐｂ５ｎ
、 Ｓｎ 、Ｉｎなどを使うことができる。In addition to the embodiments described above, the material may be diamond, GaAs, alumina, beryllia, SiC, etc. instead of silicon. In addition, silicon wafer surfaces and gold maple materials can be manufactured with or without gold maple as required. The fusing material is as described in Examples. In addition to Pb8nAg and AuSn, Pb5n
, Sn, In, etc. can be used.
第１図は本発明の一実施例により製造されたザブマウン
ト部材の斜視図、第２図、第３図及び第４図は本発明の
他の実施例の製造工程４示す平囲図％第５図は、第２図
に示すウェーハ状態のザブマウント部材を製造する一工
程ヲ胱明するための断面図である。
工・・・・・・シリコンウェーハ、１ａ・・・・・・シ
リコンミ１１片、２．３・・・・・・’ｌ’ ｉ Ｐ
を電極、４，５・・・・・・融層材、６・・°・・・融
着材料ででさたワイヤ、７・・・・・・ローラ、８・・
・・・・台。FIG. 1 is a perspective view of a submount member manufactured according to one embodiment of the present invention, and FIGS. 2, 3, and 4 are flat diagrams showing manufacturing process 4 of another embodiment of the present invention. This figure is a cross-sectional view for explaining one process of manufacturing the submount member in the wafer state shown in FIG. 2. Engineering...Silicon wafer, 1a...11 silicon pieces, 2.3...'l' i P
electrode, 4, 5...fusing material, 6...°...wire made of fusing material, 7...roller, 8...
...stand.
Claims (1)
着材紫被着してなるサブマウント部材の製造方法におい
て、前記融着材を希望の厚さ、形に形成し、その融着材
をサブマウント部材本体に加熱圧着によυ被着すること
全特徴とするサブマウント部材の製造方法。In a method for manufacturing a submount member in which a fusing material for attaching a semiconductor element is coated on a submount member main body, the fusing material is formed into a desired thickness and shape, and the fusing material is attached to the submount. A method for manufacturing a submount member, which is characterized in that υ is adhered to the main body of the member by heat compression bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP162184A JPS60145630A (en) | 1984-01-09 | 1984-01-09 | Manufacture of submounting member |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP162184A JPS60145630A (en) | 1984-01-09 | 1984-01-09 | Manufacture of submounting member |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60145630A true JPS60145630A (en) | 1985-08-01 |
Family
ID=11506596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP162184A Pending JPS60145630A (en) | 1984-01-09 | 1984-01-09 | Manufacture of submounting member |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60145630A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6717242B2 (en) | 1995-07-06 | 2004-04-06 | Hitachi Chemical Company, Ltd. | Semiconductor device and process for fabrication thereof |
| US6825249B1 (en) | 1994-12-26 | 2004-11-30 | Hitachi Chemical Co., Ltd. | Laminating method of film-shaped organic die-bonding material, die-bonding method, laminating machine and die-bonding apparatus, semiconductor device, and fabrication process of semiconductor device |
| US6855579B2 (en) | 1995-07-06 | 2005-02-15 | Hitachi Chemical Company, Ltd. | Semiconductor device and process for fabrication thereof |
-
1984
- 1984-01-09 JP JP162184A patent/JPS60145630A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6825249B1 (en) | 1994-12-26 | 2004-11-30 | Hitachi Chemical Co., Ltd. | Laminating method of film-shaped organic die-bonding material, die-bonding method, laminating machine and die-bonding apparatus, semiconductor device, and fabrication process of semiconductor device |
| US6717242B2 (en) | 1995-07-06 | 2004-04-06 | Hitachi Chemical Company, Ltd. | Semiconductor device and process for fabrication thereof |
| US6855579B2 (en) | 1995-07-06 | 2005-02-15 | Hitachi Chemical Company, Ltd. | Semiconductor device and process for fabrication thereof |
| US7012320B2 (en) | 1995-07-06 | 2006-03-14 | Hitachi Chemical Company, Ltd. | Semiconductor device and process for fabrication thereof |
| US7057265B2 (en) | 1995-07-06 | 2006-06-06 | Hitachi Chemical Co., Ltd. | Semiconductor device and process for fabrication thereof |
| US7078094B2 (en) | 1995-07-06 | 2006-07-18 | Hitachi Chemical Co., Ltd. | Semiconductor device and process for fabrication thereof |
| US7387914B2 (en) | 1995-07-06 | 2008-06-17 | Hitachi Chemical Company, Ltd. | Semiconductor device and process for fabrication thereof |
| US7781896B2 (en) | 1995-07-06 | 2010-08-24 | Hitachi Chemical Co., Ltd. | Semiconductor device and process for fabrication thereof |
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